Scribd
Upload
63 views

Sap 1

This document describes a simple computer architecture with an instruction set consisting of LDA, ADD, SUB, OUT, and HLT instructions. It loads values from memory addresses into an accumulator and performs arithmetic operations on those values. The control logic is implemented using microprogramming, where each control step is defined by a microinstruction stored in a control ROM. The microinstructions sequentially execute each instruction by controlling the datapath in 6 timing states produced by a ring counter.

Uploaded by

Sajana Islam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
63 views

Sap 1

This document describes a simple computer architecture with an instruction set consisting of LDA, ADD, SUB, OUT, and HLT instructions. It loads values from memory addresses into an accumulator and performs arithmetic operations on those values. The control logic is implemented using microprogramming, where each control step is defined by a microinstruction stored in a control ROM. The microinstructions sequentially execute each instruction by controlling the datapath in 6 timing states produced by a ring counter.

Uploaded by

Sajana Islam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

Simple As Possible

Computer
Block Diagram
Instruction Set
1. LDA <memory address>
accumulator=content of memory address
2. ADD <memory address>
accumulator<=acc. + content of mem.
3. SUB <memory address>
accumulator<=acc. - content of mem.

1,2,3: Memory Reference Instruction


Instruction Set
4. OUT
out register = accumator

5. HLT
-stops clock
Example
25-9+10-18=?

-Load 25 in accumulator
-Subtract 9 from 25
-Add 10 with the result
-Subtract 18
-Show output
Example
25-9+10-18=?
F 00010010 7 XXXXXXXX
Source Machine
E 00001010 6 XXXXXXXX
Code Code
D 00001001 5 1111XXXX
LDA CH 00001100
C 00011001 4 1110XXXX
SUB DH 00101101
B XXXXXXXX 3 00101111
ADD EH 00011110
A XXXXXXXX 2 00011110
SUB FH 00101111
9 XXXXXXXX 1 00101101
OUT 1110XXXX
8 XXXXXXXX 0 00001100
HLT 1111XXXX
Control Word
CON=

= 00 1 1 1 1 1 0 0011

=3E3 H
Timing (T) States
• Controller/Sequencer controls all the
operations. Each instruction is executed
through a series of step. Each such step
is called a Timing state (T state)
• The 6 bit Ring Counter produces 6 T
states for SAP-1
• Different CON words are produced in
different T states
T states
Fetch Cycle : T1

CON= 0101 1110 0011


=5E3 H

T1: Address State


Fetch Cycle : T2

CON= 1011 1110 0011


=BE3 H

T2:Increment State
Fetch Cycle : T3

CON= 0010 0110 0011


= 26 3 H

T3: Memory State


Execution Cycle : T4 <LDA>

CON= 0001 1010 0011


= 1A3 H
Execution Cycle : T5 <LDA>

CON= 0010 1100 0011


= 2C3 H

Md. Ayaz Masud


EEE 315: MICROPROCESSOR & INTERFACING
5/14/2020 Lecturer, Dept of EEE, BUET
Execution Cycle : T6 <LDA>

CON= 0011 1110 0011


= 3E3 H

NOP

Md. Ayaz Masud


EEE 315: MICROPROCESSOR & INTERFACING
5/14/2020 EEE 315: MICROPROCESSOR & INTERFACING Lecturer, DeptMd. AyazBUET
of EEE, Masud
5/14/2020 Lecturer, Dept of EEE, BUET
Microprogramming
• Each control word is called a microinstruction

• Microprogramming is an alternate way of


building controller-sequencer by storing
every microinstruction in a ROM sequentially.

-starting address of routine


-stepping through the routine addresses
-applying them to control ROM
ADDRESS CONTENT ROUTINE
0 5E3 FETCH
1 BE3 Microprogramming
2 263
3 1A3 LDA
4 2C3 Control ROM
5 3E3
6 1A3 ADD
7 2E1 Address ROM
8 3C7
ADDRESS CONTENT
9 1A3 SUB
0000 3
A 2E1
0001 6
B 3CF
0010 9
C 3F2 OUT
……
D 3E3
1110 c
E 3E3
F X
Microprogramming

You might also like