Advancements in Flip Chip

Reinforcement and Durability

Tomas Sakatani
 Abstract
The Flip Chip, also known as C4, is currently the most efficient electronic

packaging interconnection for small form factor integrations. Flip chip is a high

density, high I/O port application of silicon interconnections, but the method is flawed

when it comes to accounting for bending stress of the carrier substrate. This bending

stress is known to be the culprit for delamination of the interconnect solder joints.

This paper will showcase techniques introduced by the Taiwan Semiconductor

Manufacturing Company, Phoenix Pioneer Technology Company, and Sensors Unlimited,

Incorporated. These techniques focus on reinforcing the solder joint interconnection as well as

minimizing bending caused by the high density of solder joints. The techniques show an array

of ideas, such as replacing bumps with copper poles, adding metal poles in order to add

rigidity to the carrier substrate, addition of a glass plate on the Si die, and lastly laser cutting

an insulating material layer that isolates raised conductive poles to replace solder bumps and

reinforcing the interconnect solder joints.

 Content

Content
1. INTRODUCTION ........................................................................................... 1

2. CARRIER SUBSTRATE REINFORCEMENT .......................................... 2

1.1 TSMC INVENTIONS ............................................................................................. 2
1.2 SENSORS UNLIMITED INVENTION ........................................................................ 5
1.3 PPT INVENTION ................................................................................................... 7

3. CONCLUSION | DISCUSSION .................................................................... 8

4. APPENDIX .................................................................................................... 10
1.4 REFERENCES ...................................................................................................... 10

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 1.Introduction
Since the inception of the Integrated Circuit (IC), semiconductor technologies were

developed such that hardware focuses on optimizing spatial footprint of the IC, as well as the

performance and reliability of the package. Advancements in semiconductor technologies,

has led to a rapid growth for technology with a focus on portability and high performance.

technologies such as virtual Reality (VR), Artificial intelligence (AI), Augmented Reality

(AR), and 5G high frequency communications have outlined the shortcomings of the current

IC interconnection process. The heat generation that comes with high performance computing

and the vibrations from mobile integrations, are known to be the main culprit of bending

stress in IC chips. These new emerging technologies require a higher core layer count, as well

as larger packages to increase the density of electrical contacts. As the industry trends into

more intricate software processes the hardware manufacturing processes must follow; Thus,

the need to study ways in which the industry must move to implement these processes is

crucial for the advancement in IC technologies.

To move the industry forward, the way the IC interconnection is deployed must be

reviewed. The current standard in interconnection technologies is the use of a solder bumps

that are reinforced with a resin underfill. The use of underfill epoxy is prevalent in organic

flip chip packages to reduce shear strains in flip chip solder joints and thus enhance their

reliability. Although the underfill serves as a reinforcement, it has its own shortcomings; the

underfill is often susceptible to interfacial delamination and delamination due to inadequate

underfill adhesion [4]. Furthermore, underfill substrate failure is often associated with the

crystallization rate of the resin compared to the solder joint, and the stresses related to the

thermal expansion and contraction of the underfill resin. Underfill delamination originates at

the die periphery around the fillet region, especially at die corners where the die experiences

the most stresses. Under temperature cycling testing, or under field use condition, the

delamination at the die corner propagates through the flip chip bumps causing functional

failure of the chip [4]. With the exponential growth of mobile technologies reinforcement for

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higher-than-normal temperatures as well as drop/impact reliability measures should be

considered.

Flip Chips as a standard practice, are manufactured with the use of an epoxy underfill that aids the

rigidity of the interconnection. Universal industries study [5] showcases the effects of mismatched

thermal expansion stress on the flip chip and the causes of it. The underfill of flip chips are much to

blame. The thermal expansion coefficients of solder and the underfill resin are different so the thermal

stresses developed. Furthermore, it was found that the underfill not only adhere weakly to the solder

joint but sometimes not at all, this is mainly towards the inner side of the dies and does not produce

imminent failure. If there was a delamination developed in the edge of the underfill, solder joint

failure tends to me almost instant. The use of alternatives to underfill are to be examined and to be

showcased as a viable replacement for resin underfill.

This report examines the both the root causes of flip chip underfill delamination as well

as the new trends in flip chip implementation design that allow chips to be both efficient and

mechanically robust. Manufacturers such as PPT [1] and TSMC [2][3], are developing new

ways to implement flip chips for new technology use, the vast majority being mobile use.

PPT and TSMC’s designs are aided by using underfill but reinforcing the solder joints from

IC to chip substrate, as well as replacing solder pads with raised copper poles. Similarly,

TSMC is also working on an IC package that would not require underfill resin which

mitigates some of the issues related to thermals and delamination. Other manufacturer

investigated in this report, focuses on eliminating shorting of interconnections, which is an

issue related to solder bumps.

2.Carrier Substrate Reinforcement

1.1 TSMC Inventions
The Taiwan Semiconductor Manufacturing Company (TSMC) is a Taiwanese multinational

semiconductor contract manufacturing and design company. TSMC has been on the forefront

of the development of new flip chip solder joint reinforcement technologies as of recent years.
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The increasing demand for mobility has driven the technology for looking for ways to make

chips more reliable.

One main technology developed by TSMC was US patent number US 8,810,025 B2 [3],

this development was a periphery reinforcement; it is industry knowledge that the edges of a

carrier substrate have the most shear stresses in a flip chip design. This phenomenon is cause

by bending of the chip carrier, which in part ends delaminating the solder joints. TSMC’s

design was to reinforce the edges of the carrier substrate, by adding an array of metal poles

(usually made of aluminum or copper) around the periphery of the substrate. This creates

added strengths that help counteract the bending, thus decreasing the delamination of the

solder joint and increase reliability.

Figure 1: US 8,810,025 B2, flip chip design. Cross section shows the location of the poles

within the carrier substrate with respect to the Si die.

Furthermore, the increase of strength in the substrate enables the SI die to be integrated

without the use of an extraneous substances or resin. This technique follows proven methods

for mechanical reinforcement used in the construction industry, i.e. The use of rebar in

concrete to add rigidity to the structure. The drawbacks of this type of structure and
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reinforcement would be spatial. The space taken up by the poles means that the space that

could be used to create extra interconnections, is not used to create more rigidity to the flip

chip.

Capitalizing on creative ways to mitigate bending of the substrate TSMC Idealized a new

technique as shown in US 2016/0315057 A1 [2]. As the title states “REINFORCEMENT

STRUCTURE AND METHOD FOR CONTROLLING WARPAGE OF CHIP MOUNTED

ON SUBSTRATE” this technique also focused on the root cause of interconnection failure.

This patent tackles this warping issue by increasing the thickness of the Si die by attaching a

glass layer on top. Furthermore, the patent goes as far as adding a layer of glass under the

carrier and adding notches into the glass layer so the layer attaches to the die more securely.

Figure 2: Reinforcement plate adhered to the top of the Si die interface.

Figure 3: Reinforcement plate adhered to the bottom of the Si die interface.

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 Figure 4: Reinforcement plate adhered to the top of the Si die interface, with reinforcement

notches added.

As shown above this method of reinforcement adds rigidity to the Si die/substrate interface,

through addition of a more mechanically strong material. the Si die is constricted by the plate

and it is sandwiched between the substrate and the plate. Noting that the addition of a plate

also adds more thickness, which itself deters the portability of the chip but it is deemed a

necessary addition for performance. Another drawback of this design is the thermal

conductivity of the Si die. Having to cool these chips would be deterred by the addition of 2

more layers to the heat transfer calculations. As seen on fig. 3, addition of notches to the top

of the Si die further adds to the rigidity by having greater surface area as well as diverting

stress concentrations developed in the substrate interface.

1.2 Sensors Unlimited invention

Sensors Unlimited is a defense company that is known for their focus on lasers and optics.

They recently acquired a patent for reinforcement of interconnect bump structures, that is

very peculiar coming from an optics and laser company. This patent is not necessarily for

reliability of flip chips but for Focal Plane Array (FPA) instruments that uses flip chip

hybridization. Because of the flip chip’s high density of I/O ports and ease of integration, it

was deemed an ideal use for integration between the photodiode array (PDA) and the

readout integrated circuit (ROIC)because of its small footprint.

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 In the patent by Sensors Unlimited the flip chip interconnection is handled by way of

introducing an insulating layer to the substrate as well as coating the insulating later with

dielectric material to introduce height, these layers are then etched into pockets where both

ends are opposite copies of each other. A final conductive material is added to make the

solder bump connection. The final result as follows:

Figure 5: separated interconnect architecture of the flip chip integration[6]. Where 122 is the
Si die and 102 is the carrier substrate.

Figure 6: fully integrated invention[6]. Where 122 is the Si die and 102 is the carrier substrate.

The insulating material serves as a protective barrier for the solder bumps to make good

physical contact with eachother and for there not to be a short between bumps. This method
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also does not include the use of epoxy resin to afix the Si die to the Substrate; the

interconnections are secured by both the dielectric material and the insulating material, which

brings rigidity that is achieved with epoxy otherwise. This design implementation requires

higher manufacturing costs and more advanced manufacturing techniques that would’t be

viable in the mass production market.

1.3 PPT Invention

Phoenix Pioneer Technology Company (PPT) is a semiconductor distribution and manufacturing

company that developed a similar interconnection scheme as Sensors Unlimited. For the same

reasonings as all the aforementioned companies, phoenix tackled these problems using raised solder

pads. They focused on the causes for delamination between the solder joint and solder pad; due to

bending of the die and substrate, solder joints tend to delaminate towards the copper pad joint on

the bottom. This is due the addition of torques caused by the bending. PPT decided t raise the

copper pad so it matches the height of the solder bump, thus requiring less solder to attach and

making the interconnection much more rigid.

Figure 7: the carrier substrate before the implementation of the Si die. Shows the conductive pols

with the solder drops to attach to the die.

Another layer of reinforcement added to the substrate was the conductive pillars in the core

layer of the carrier substrate. These pillars due to their positioning on the substrate and change in

shape down the core, the pillar adds rigidity and helps combat bending. Although this is a

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multilayered reinforcement, the Si die chip still requires a resin underfill to help with the bending of

the chip.

Figure 8: the fill assembly of the Flip Chip as intended by PPT.

Noting the underfill and the poles on both the die and the substrate, the structure takes on an

intricate shape that indicates a more solid interconnection to the Silicone.

3.Conclusion | Discussion
Underfill resin is both the current solution for premature flip chip failure and also a

stressor and aide for solder joint failure. The main focus of this report is to showcase

companies that are devising ways to mitigate the stresses. These stresses are caused by

mismatched thermals of underfill, as well as the bending stresses that come with flip chip

interconnections. TSMC’s inventions worked by Isolating a single problem with flip chip

integration. The Idea of placing reinforcement poles to reduce bending is a creative solution

to a problem, but the extra space that needed to be introduced defeats the point of making

technology smaller for certain applications. Furthermore, TSMC’s Idea of putting a Glass

substrate on top of the Si die was not properly executed. Both designs by TSMC add weight

that in part increases the chances of solder bumps touching each other as well as extra shear

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stresses when the chip is not implemented with the solder pads facing down. PPT’s design

was clever, by having copper poles replace the solder bump, one decreases the wetting

angle of the solder interconnection that in part makes the interconnection stronger. But the

use of underfill in the design begs the question of how much more reliable this could be

instead of solder bumps. Lastly Sensors United’s Design was very well implemented, the

use of an insulator to virtually encapsulate solder joints and raise the pads so they meet in

the middle was a brilliant idea in terms of making sure the solder interconnect doesn’t bleed

into other joints as well as creating a more rigid structure between Si die and carrier

substrate. Also this is the most ideal design out there, one can ask the question of how does

te interconnection perform under heavy loads as well as the efficacy of the structure in term

of rigidity.

Despite this being an ever advancing technology,

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 4.Appendix
1.4 References
[1]Phoenix Pioneer Technology CO., LTD., "FLIP-CHIP PACKAGE SUBSTRATE AND
METHOD FOR PREPARING THE SAME", US 2020/0066624 A1, 2020.
[2]Taiwan Semiconductor Manufacturing Company LTD, "REINFORCEMENT
STRUCTURE AND METHOD FOR CONTROLLING WARPAGE OF CHIP
MOUNTED ON SUBSTRATE", US 2016/0315057 A1, 2020.
[3]Taiwan Semiconductor Manufacturing Company, Ltd., "REINFORCEMENT
STRUCTURE FOR FLIP-CHIP PACKAGNG", US 8,810,025 B2, 2021.
[4]K. Sidharth, A. Dubey, C. Zhai and R. Blish, "Impact of Underfill Fillet Geometry on
Interfacial Delamination in Organic Flip Chip Packages", 56th Electronic Components
and Technology Conference 2006. Available: 10.1109/ectc.2006.1645871 [Accessed 7
March 2021].
[5]Universal Instruments, "Flip Chip Reliability", [Accessed 7 March 2021].
[6]Sensors Unlimited, Inc., "Bump structures for high density flip chip interconnection", US
10879204, 2020.

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