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William Stallings Computer Organization and Architecture 7th Edition Internal Memory Semiconductor Memory Types

This document discusses different types of semiconductor memory, including RAM, ROM, DRAM, and SRAM. It describes the basic operation and characteristics of dynamic RAM (DRAM) and static RAM (SRAM). DRAM uses capacitors to store bits that need periodic refreshing, while SRAM uses flip-flops that retain data indefinitely. The document also covers more advanced memory technologies like error correction, synchronous DRAM (SDRAM), and cache DRAM.

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71 views

William Stallings Computer Organization and Architecture 7th Edition Internal Memory Semiconductor Memory Types

This document discusses different types of semiconductor memory, including RAM, ROM, DRAM, and SRAM. It describes the basic operation and characteristics of dynamic RAM (DRAM) and static RAM (SRAM). DRAM uses capacitors to store bits that need periodic refreshing, while SRAM uses flip-flops that retain data indefinitely. The document also covers more advanced memory technologies like error correction, synchronous DRAM (SDRAM), and cache DRAM.

Uploaded by

Zakinuddin
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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William Stallings Semiconductor Memory Types

Computer Organization
and Architecture
7th Edition

Chapter 5
Internal Memory

Semiconductor Memory Memory Cell Operation


• RAM
—Misnamed as all semiconductor memory is
random access
—Read/Write
—Volatile
—Temporary storage
—Static or dynamic
Dynamic RAM Dynamic RAM Structure
• Bits stored as charge in capacitors
• Charges leak
• Need refreshing even when powered
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits
• Slower
• Main memory
• Essentially analogue
—Level of charge determines value

DRAM Operation Static RAM


• Address line active when bit read or written • Bits stored as on/off switches
— Transistor switch closed (current flows)
• No charges to leak
• Write
— Voltage to bit line • No refreshing needed when powered
– High for 1 low for 0 • More complex construction
— Then signal address line
– Transfers charge to capacitor • Larger per bit
• Read • More expensive
— Address line selected • Does not need refresh circuits
– transistor turns on
— Charge from capacitor fed via bit line to sense amplifier • Faster
– Compares with reference value to determine 0 or 1 • Cache
— Capacitor charge must be restored
• Digital
—Uses flip-flops
Stating RAM Structure Static RAM Operation
• Transistor arrangement gives stable logic
state
• State 1
—C1 high, C2 low
—T1 T4 off, T2 T3 on
• State 0
—C2 high, C1 low
—T2 T3 off, T1 T4 on
• Address line transistors T5 T6 is switch
• Write – apply value to B & compliment to
B
• Read – value is on line B

SRAM v DRAM Read Only Memory (ROM)


• Both volatile • Permanent storage
—Power needed to preserve data —Nonvolatile
• Dynamic cell • Microprogramming (see later)
—Simpler to build, smaller • Library subroutines
—More dense • Systems programs (BIOS)
—Less expensive
• Function tables
—Needs refresh
—Larger memory units
• Static
—Faster
—Cache
Types of ROM Organisation in detail
• Written during manufacture • A 16Mbit chip can be organised as 1M of
—Very expensive for small runs 16 bit words
• Programmable (once) • A bit per chip system has 16 lots of 1Mbit
—PROM chip with bit 1 of each word in chip 1 and
—Needs special equipment to program so on
• Read “mostly” • A 16Mbit chip can be organised as a 2048
—Erasable Programmable (EPROM) x 2048 x 4bit array
– Erased by UV —Reduces number of address pins
—Electrically Erasable (EEPROM) – Multiplex row address and column address
– Takes much longer to write than read – 11 pins to address (211=2048)
—Flash memory – Adding one more pin doubles range of values so x4
capacity
– Erase whole memory electrically

Refreshing Typical 16 Mb DRAM (4M x 4)


• Refresh circuit included on chip
• Disable chip
• Count through rows
• Read & Write back
• Takes time
• Slows down apparent performance
256kByte Module
Packaging Organisation

1MByte Module Organisation Error Correction


• Hard Failure
—Permanent defect
• Soft Error
—Random, non-destructive
—No permanent damage to memory
• Detected using Hamming error correcting
code
Error Correcting Code Function Advanced DRAM Organization
• Basic DRAM same since first RAM chips
• Enhanced DRAM
—Contains small SRAM as well
—SRAM holds last line read (c.f. Cache!)
• Cache DRAM
—Larger SRAM component
—Use as cache or serial buffer

Synchronous DRAM (SDRAM) SDRAM


• Access is synchronized with an external clock
• Address is presented to RAM
• RAM finds data (CPU waits in conventional
DRAM)
• Since SDRAM moves data in time with system
clock, CPU knows when data will be ready
• CPU does not have to wait, it can do something
else
• Burst mode allows SDRAM to set up stream of
data and fire it out in block
• DDR-SDRAM sends data twice per clock cycle
(leading & trailing edge)
SDRAM Read Timing RAMBUS
• Adopted by Intel for Pentium & Itanium
• Main competitor to SDRAM
• Vertical package – all pins on one side
• Data exchange over 28 wires < cm long
• Bus addresses up to 320 RDRAM chips at
1.6Gbps
• Asynchronous block protocol
—480ns access time
—Then 1.6 Gbps

RAMBUS Diagram DDR SDRAM


• SDRAM can only send data once per clock
• Double-data-rate SDRAM can send data
twice per clock cycle
—Rising edge and falling edge
Cache DRAM Reading
• Mitsubishi • The RAM Guide
• Integrates small SRAM cache (16 kb) onto • RDRAM
generic DRAM chip
• Used as true cache
—64-bit lines
—Effective for ordinary random access
• To support serial access of block of data
—E.g. refresh bit-mapped screen
– CDRAM can prefetch data from DRAM into SRAM
buffer
– Subsequent accesses solely to SRAM

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