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N Bit Adder: VHDL Code

The document describes a VHDL code for an n-bit adder. It contains the code for the n-bit adder entity using full adders as components. It also contains a test bench that instantiates the n-bit adder and applies test vectors to verify its functionality. The test bench applies different input combinations to the adder and checks that the output sum is calculated correctly.

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abhay kumar
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Download as DOCX, PDF, TXT or read online on Scribd
172 views

N Bit Adder: VHDL Code

The document describes a VHDL code for an n-bit adder. It contains the code for the n-bit adder entity using full adders as components. It also contains a test bench that instantiates the n-bit adder and applies test vectors to verify its functionality. The test bench applies different input combinations to the adder and checks that the output sum is calculated correctly.

Uploaded by

abhay kumar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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N bit adder

VHDL code:

library IEEE; 
 use IEEE.STD_LOGIC_1164.ALL; 
 use IEEE.STD_LOGIC_ARITH.ALL; 
 use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 entity nbitadder is 
 generic(n:positive:=4); 
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0); 
       InB : in STD_LOGIC_VECTOR (n-1 downto 0); 
       C_terms : in STD_LOGIC_VECTOR (n-1 downto 0); 
       sum : out STD_LOGIC_VECTOR (n-1 downto 0); 
       c_out : out STD_LOGIC); 
 end nbitadder; 
 architecture Behavioral of nbitadder is 
           component fulladder 
                 Port ( a : in STD_LOGIC; 
                           b : in STD_LOGIC; 
                           cin : in STD_LOGIC; 
                           sum : out STD_LOGIC; 
                           cout : out STD_LOGIC); 
           end component; 
 signal not_connected: STD_LOGIC_VECTOR(n-2 downto 0); 
 begin 
                     inst:for i in n-1 downto 0 generate 
                                    lastbit:if i=n-1 generate 
                                    A: fulladder port map
(InA(i),InB(i),C_terms(i),sum(i),c_out); 
                                    end generate; 
                                    otherbits: if i/=n-1 generate 
                                    B: fulladder port
map(InA(i),InB(i),C_terms(i),sum(i),not_connected(i)); 
                                    end generate; 
                     end generate; 
 end Behavioral; 
Test bench:

LIBRARY ieee; 
 USE ieee.std_logic_1164.ALL; 
 ENTITY nbitaddertestbench IS 
 END nbitaddertestbench; 
 ARCHITECTURE behavior OF nbitaddertestbench IS  
   -- Component Declaration for the Unit Under Test (UUT) 
   COMPONENT nbitadder 
   PORT( 
      InA : IN std_logic_vector(3 downto 0); 
      InB : IN std_logic_vector(3 downto 0); 
      C_terms : IN std_logic_vector(3 downto 0); 
      sum : OUT std_logic_vector(3 downto 0); 
      c_out : OUT std_logic 
     ); 
   END COMPONENT; 
   --Inputs 
   signal InA : std_logic_vector(3 downto 0) := (others => '0'); 
   signal InB : std_logic_vector(3 downto 0) := (others => '0'); 
   signal C_terms : std_logic_vector(3 downto 0) := (others => '0'); 
       --Outputs 
   signal sum : std_logic_vector(3 downto 0); 
   signal c_out : std_logic; 
   -- No clocks detected in port list. Replace <clock> below with  
   -- appropriate port name  
   constant <clock>_period : time := 10 ns; 
 BEGIN 
      -- Instantiate the Unit Under Test (UUT) 
   uut: nbitadder PORT MAP ( 
      InA => InA, 
      InB => InB, 
      C_terms => C_terms, 
      sum => sum, 
      c_out => c_out 
     ); 
   -- Clock process definitions 
   <clock>_process :process 
   begin 
           <clock> <= '0'; 
           wait for <clock>_period/2; 
           <clock> <= '1'; 
           wait for <clock>_period/2; 
   end process; 
   -- Stimulus process 
   stim_proc: process 
   begin           
    wait for 100 ns; 
           InA <= "0000"; 
    InB <= "0000"; 
    C_terms <= "0000"; 
    sum <= "0000"; 
           wait for 100 ns; 
           InA <= "0000"; 
    InB <= "0001"; 
    C_terms <= "0000"; 
    sum <= "0001"; 
           wait for 100 ns; 
       InA <= "0001"; 
    InB <= "0001"; 
    C_terms <= "0000"; 
    sum <= "0000"; 
           wait for 100 ns; 
           InA <= "0010"; 
    InB <= "0001"; 
    C_terms <= "0000"; 
    sum <= "0001"; 
           wait for 100 ns; 
           InA <= "0010"; 
    InB <= "0011"; 
    C-Terms <= "0000"; 
    sum <= "0001"; 
    wait; 
   end process; 
 END; 

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