8-Bit Microcontroller With 1K Byte Flash AT89C1051: Features
8-Bit Microcontroller With 1K Byte Flash AT89C1051: Features
Pin Configuration
PDIP/SOIC
0366D-A–12/97
4-3
Block Diagram
VCC
PROGRAM
B STACK ADDRESS
REGISTER ACC POINTER REGISTER
BUFFER
TMP2 TMP1
PC
ALU INCREMENTER
INTERRUPT,
AND TIMER BLOCKS
PROGRAM
PSW COUNTER
TIMING INSTRUCTION
RST AND REGISTER DPTR
CONTROL
PORT 1 PORT 3
ANALOG LATCH LATCH
COMPARATOR
+
-
OSC
PORT 1 DRIVERS PORT 3 DRIVERS
4-4 AT89C1051
AT89C1051
4-5
Special Function Registers Restrictions on Certain Instructions
A map of the on-chip memory area called the Special Func- The AT89C1051 is an economical and cost-effective mem-
tion Register (SFR) space is shown in the table below. ber of Atmel’s growing family of microcontrollers. It con-
tains 1K byte of flash program memory. It is fully compati-
Note that not all of the addresses are occupied, and unoc-
ble with the MCS-51 architecture, and can be programmed
cupied addresses may not be implemented on the chip.
using the MCS-51 instruction set. However, there are a
Read accesses to these addresses will in general return few considerations one must keep in mind when utilizing
random data, and write accesses will have an indetermi- certain instructions to program this device.
nate effect.
All the instructions related to jumping or branching should
User software should not write 1s to these unlisted loca- be restricted such that the destination address falls within
tions, since they may be used in future products to invoke
the physical program memory space of the device, which is
new features. In that case, the reset or inactive values of
1K for the AT89C1051. This should be the responsibility of
the new bits will always be 0. the software programmer. For example, LJMP 3FEH
would be a valid instruction for the AT89C1051 (with 1K of
memory), whereas LJMP 410H would not.
Table 1. AT89C1051 SFR Map and Reset Values
0F8H 0FFH
0F0H B 0F7H
00000000
0E8H 0EFH
0C0H 0C7H
0B8H IP 0BFH
XXX00000
0B0H P3 0B7H
11111111
0A8H IE 0AFH
0XX00000
0A0H 0A7H
98H 9FH
90H P1 97H
11111111
88H TCON TMOD TL0 TH0 8FH
00000000 00000000 00000000 00000000
80H SP DPL DPH PCON 87H
00000111 00000000 00000000 0XXX0000
4-6 AT89C1051
AT89C1051
4-7
Programming Algorithm: To program the AT89C1051, Data Polling: The AT89C1051 features Data Polling to
the following sequence is recommended. indicate the end of a write cycle. During a write cycle, an
1. Power-up sequence: attempted read of the last byte written will result in the com-
Apply power between VCC and GND pins plement of the written data on P1.7. Once the write cycle
Set RST and XTAL1 to GND has been completed, true data is valid on all outputs, and
2. Set pin RST to ‘H’ the next cycle may begin. Data Polling may begin any time
Set pin P3.2 to ‘H’ after a write cycle has been initiated.
3. Apply the appropriate combination of ‘H’ or ‘L’ logic Ready/Busy: The Progress of byte programming can also
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the be monitored by the RDY/BSY output signal. Pin P3.1 is
programming operations shown in the PEROM Pro- pulled low after P3.2 goes High during programming to indi-
gramming Modes table. cate BUSY. P3.1 is pulled High again when programming is
To Program and Verify the Array: done to indicate READY.
4. Apply data for Code byte at location 000H to P1.0 to Program Verify: If lock bits LB1 and LB2 have not been
P1.7. programmed code data can be read back via the data lines
5. Raise RST to 12V to enable programming. for verification:
6. Pulse P3.2 once to program a byte in the PEROM array 1. Reset the internal address counter to 000H by bringing
or the lock bits. The byte-write cycle is self-timed and RST from ’L’ to ’H’.
typically takes 1.2 ms. 2. Apply the appropriate control signals for Read Code data
7. To verify the programmed data, lower RST from 12V to and read the output data at the port P1 pins.
logic ‘H’ level and set pins P3.3 to P3.7 to the appropiate 3. Pulse pin XTAL1 once to advance the internal address
levels. Output data can be read at the port P1 pins. counter.
8. To program a byte at the next address location, pulse 4. Read the next code data byte at the port P1 pins.
XTAL1 pin once to advance the internal address counter. 5. Repeat steps 3 and 4 until the entire array is read.
Apply new data to the port P1 pins. The lock bits cannot be verified directly. Verification of the
9. Repeat steps 5 through 8, changing data and advancing lock bits is achieved by observing that their features are
the address counter for the entire 1K byte array or until enabled.
the end of the object file is reached.
10.Power-off sequence:
set XTAL1 to ‘L’
set RST to ‘L’
Turn VCC power off
Flash Programming Modes
Mode RST/VPP P3.2/PROG P3.3 P3.4 P3.5 P3.7
Write Code Data(1)(3) 12V L H H H
Bit-2 12V H H L L
4-8 AT89C1051
AT89C1051
Chip Erase: The entire PEROM array (1K byte) and the Programming Interface
two Lock Bits are erased electrically by using the proper
Every code byte in the Flash array can be written and the
combination of control signals and by holding P3.2 low for
entire array can be erased by using the appropriate combi-
10 ms. The code array is written with all “1”s in the Chip
nation of control signals. The write operation cycle is self-
Erase operation and must be executed before any non-
timed and once initiated, will automatically time itself to
blank memory byte can be re-programmed.
completion.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 001H, and 002H, except that P3.5 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 11H indicates 89C1051
Figure 3. Programming the Flash Memory Figure 4. Verifying the Flash Memory
5V 5V
AT89C1051 AT89C1051
RDY/BSY P3.1 VCC VCC
4-9
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol Parameter Min Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 µA
tDVGL Data Setup to PROG Low 1.0 µs
tGHDX Data Hold After PROG 1.0 µs
tEHSH P3.4 (ENABLE) High to VPP 1.0 µs
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold After PROG 10 µs
tGLGH PROG Width 1 110 µs
tELQV ENABLE Low to Data Valid 1.0 µs
tEHQZ Data Float After ENABLE 0 1.0 µs
tGHBL PROG High to BUSY Low 50 ns
tWC Byte Write Cycle Time 2.0 ms
tBHIH RDY/BSY to Increment Clock Delay 1.0 µs
tIHIL Increment Clock High 200 ns
Note: Only used in 12-volt programming mode.
4-10 AT89C1051
AT89C1051
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol Parameter Condition Min Max Units
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage(1) IOL = 20 mA, VCC = 5V 0.50 V
(Ports 1, 3) IOL = 10 mA, VCC = 2.7V
VOH Output High Voltage IOH = -80 µA, VCC = 5V ± 10% 2.4 V
(Ports 1, 3)
IOH = -30 µA 0.75 VCC V
IOH = -12 µA 0.9 VCC V
IIL Logical 0 Input Current VIN = 0.45V -50 µA
(Ports 1, 3)
ITL Logical 1 to 0 Transition VIN = 2V, VCC = 5V ± 10% -750 µA
Current (Ports 1, 3)
ILI Input Leakage Current 0 < VIN < VCC ±10 µA
(Port P1.0, P1.1)
VOS Comparator Input Offset VCC = 5V 20 mV
Voltage
VCM Comparator Input Common 0 VCC V
Mode Voltage
RRST Reset Pulldown Resistor 50 300 KΩ
CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
ICC Power Supply Current Active Mode, 12 MHz, VCC = 6V/3V 15/5.5 mA
Idle Mode, 12 MHz, VCC = 6V/3V P1.0 & 5/1 mA
P1.1 = 0V or VCC
Power Down Mode(2) VCC = 6V P1.0 & P1.1 = 0V or VCC 100 µA
VCC = 3V P1.0 & P1.1 = 0V or VCC 20 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 20 mA
Maximum total IOL for all output pins: 80 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power Down is 2V.
4-11
External Clock Drive Waveforms
Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a Note: 1. For timing purposes, a port pin is no longer float-
logic 1 and 0.45V for a logic 0. Timing measurements ing when a 100 mV change load voltage occurs. A
are made at VIH min. for a logic 1 and VIL max. for a port pin begins to float when a 100 mV change
logic 0. from the loaded VOH/VOL level occurs.
4-12 AT89C1051
AT89C1051
AT89C1051
TYPICAL ICC - ACTIVE (85°C)
20
Vcc=6.0V
I 15
C Vcc=5.0V
C 10
Vcc=3.0V
m
A 5
0
0 6 12 18 24
FREQUENCY (MHz)
AT89C1051
TYPICAL ICC - IDLE (85°C)
3
Vcc=6.0V
I
C 2 Vcc=5.0V
C
m 1
A
Vcc=3.0V
0
0 3 6 9 12
FREQUENCY (MHz)
AT89C1051
TYPICAL ICC vs. VOLTAGE- POWER DOWN (85°C)
20
I 15
C
C 10
µ
A 5
0
3.0V 4.0V 5.0V 6.0V
Vcc VOLTAGE
4-13
Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
12 2.7V to 6.0V AT89C1051-12PC 20P3 Commercial
AT89C1051-12SC 20S (0°C to 70°C)
AT89C1051-12PI 20P3 Industrial
AT89C1051-12SI 20S (-40°C to 85°C)
AT89C1051-12PA 20P3 Automotive
AT89C1051-12SA 20S (-40°C to 105°C)
24 4.0V to 6.0V AT89C1051-24PC 20P3 Commercial
AT89C1051-24SC 20S (0°C to 70°C)
AT89C1051-24PI 20P3 Industrial
AT89C1051-24SI 20S (-40°C to 85°C)
Package Type
20P3 20 Lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)
20S 20 Lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)
4-14 AT89C1051