Features

• Compatible with MCS-51™ Products

• 1K Byte of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-Level Program Memory Lock
• 64 bytes SRAM
• 15 Programmable I/O Lines
• One 16-Bit Timer/Counter
•
•
Three Interrupt Sources
Direct LED Drive Outputs
8-Bit
•
•
On-Chip Analog Comparator
Low Power Idle and Power Down Modes
Microcontroller
with 1K Byte
Description
The AT89C1051 is a low-voltage, high-performance CMOS 8-bit microcomputer with Flash
1K byte of Flash programmable and erasable read only memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51™ instruction set. By combining
a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C1051 is a pow- AT89C1051
erful microcomputer which provides a highly flexible and cost effective solution to
many embedded control applications.
The AT89C1051 provides the following standard features: 1K Byte of Flash, 64 bytes
of RAM, 15 I/O lines, one 16-bit timer/counter, a three vector two-level interrupt archi-
tecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addi-
tion, the AT89C1051 is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port and interrupt system to con-
tinue functioning. The Power Down Mode saves the RAM contents but freezes the
oscillator disabling all other chip functions until the next hardware reset.

Pin Configuration
PDIP/SOIC

0366D-A–12/97

4-3
Block Diagram
VCC

RAM ADDR. RAM

REGISTER FLASH
GND

PROGRAM
B STACK ADDRESS
REGISTER ACC POINTER REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT,
AND TIMER BLOCKS

PROGRAM
PSW COUNTER

TIMING INSTRUCTION
RST AND REGISTER DPTR
CONTROL

PORT 1 PORT 3
ANALOG LATCH LATCH
COMPARATOR
+
-
OSC
PORT 1 DRIVERS PORT 3 DRIVERS

P1.0 - P1.7 P3.0 - P3.5 P3.7

4-4 AT89C1051
 AT89C1051

Pin Description Oscillator Characteristics

VCC XTAL1 and XTAL2 are the input and output, respectively,
Supply voltage. of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
GND
crystal or ceramic resonator may be used. To drive the
Ground.
device from an external clock source, XTAL2 should be left
Port 1 unconnected while XTAL1 is driven as shown in Figure 2.
Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to There are no requirements on the duty cycle of the external
P1.7 provide internal pullups. P1.0 and P1.1 require exter- clock signal, since the input to the internal clocking circuitry
nal pullups. P1.0 and P1.1 also serve as the positive input is through a divide-by-two flip-flop, but minimum and maxi-
(AIN0) and the negative input (AIN1), respectively, of the mum voltage high and low time specifications must be
on-chip precision analog comparator. The Port 1 output observed.
buffers can sink 20 mA and can drive LED displays directly.
Figure 1. Oscillator Connections
When 1s are written to Port 1 pins, they can be used as
inputs. When pins P1.2 to P1.7 are used as inputs and are
externally pulled low, they will source current (IIL) because
of the internal pullups.
Port 1 also receives code data during Flash programming
and verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O
pins with internal pullups. P3.6 is hard-wired as an input to
the output of the on-chip comparator and is not accessible
as a general purpose I/O pin. The Port 3 output buffers can
sink 20 mA. When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as
inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C1051 as listed below:
Note: C1, C2 = 30 pF ± 10 pF for Crystals
Port Pin Alternate Functions = 40 pF ± 10 pF for Ceramic Resonators
P3.2 INT0 (external interrupt 0) Figure 2. External Clock Drive Configuration
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)

Port 3 also receives some control signals for Flash pro-

gramming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST
goes high. Holding the RST pin high for two machine cycles
while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.

4-5
Special Function Registers Restrictions on Certain Instructions
A map of the on-chip memory area called the Special Func- The AT89C1051 is an economical and cost-effective mem-
tion Register (SFR) space is shown in the table below. ber of Atmel’s growing family of microcontrollers. It con-
tains 1K byte of flash program memory. It is fully compati-
Note that not all of the addresses are occupied, and unoc-
ble with the MCS-51 architecture, and can be programmed
cupied addresses may not be implemented on the chip.
using the MCS-51 instruction set. However, there are a
Read accesses to these addresses will in general return few considerations one must keep in mind when utilizing
random data, and write accesses will have an indetermi- certain instructions to program this device.
nate effect.
All the instructions related to jumping or branching should
User software should not write 1s to these unlisted loca- be restricted such that the destination address falls within
tions, since they may be used in future products to invoke
the physical program memory space of the device, which is
new features. In that case, the reset or inactive values of
1K for the AT89C1051. This should be the responsibility of
the new bits will always be 0. the software programmer. For example, LJMP 3FEH
would be a valid instruction for the AT89C1051 (with 1K of
memory), whereas LJMP 410H would not.
Table 1. AT89C1051 SFR Map and Reset Values
0F8H 0FFH

0F0H B 0F7H
00000000
0E8H 0EFH

0E0H ACC 0E7H

00000000
0D8H 0DFH

0D0H PSW 0D7H

00000000
0C8H 0CFH

0C0H 0C7H

0B8H IP 0BFH
XXX00000
0B0H P3 0B7H
11111111
0A8H IE 0AFH
0XX00000
0A0H 0A7H

98H 9FH

90H P1 97H
11111111
88H TCON TMOD TL0 TH0 8FH
00000000 00000000 00000000 00000000
80H SP DPL DPH PCON 87H
00000111 00000000 00000000 0XXX0000

4-6 AT89C1051
 AT89C1051

1. Branching instructions: Idle Mode

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR
In idle mode, the CPU puts itself to sleep while all the on-
These unconditional branching instructions will execute chip peripherals remain active. The mode is invoked by
correctly as long as the programmer keeps in mind that the software. The content of the on-chip RAM and all the spe-
destination branching address must fall within the physical cial functions registers remain unchanged during this
boundaries of the program memory size (locations 00H to mode. The idle mode can be terminated by any enabled
3FFH for the 89C1051). Violating the physical space limits interrupt or by a hardware reset.
may cause unknown program behavior.
P1.0 and P1.1 should be set to ‘0’ if no external pullups are
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With used, or set to ‘1’ if external pullups are used.
these conditional branching instructions the same rule
It should be noted that when idle is terminated by a hard-
above applies. Again, violating the memory boundaries
ware reset, the device normally resumes program execu-
may cause erratic execution.
tion, from where it left off, up to two machine cycles before
For applications involving interrupts the normal interrupt the internal reset algorithm takes control. On-chip hardware
service routine address locations of the 80C51 family archi- inhibits access to internal RAM in this event, but access to
tecture have been preserved. the port pins is not inhibited. To eliminate the possibility of
2. MOVX-related instructions, Data Memory: an unexpected write to a port pin when Idle is terminated by
The AT89C1051 contains 64 bytes of internal data mem- reset, the instruction following the one that invokes Idle
ory. Thus, in the AT89C1051 the stack depth is limited to should not be one that writes to a port pin or to external
64 bytes, the amount of available RAM. External DATA memory.
memory access is not supported in this device, nor is exter-
nal PROGRAM memory execution. Therefore, no MOVX Power Down Mode
[...] instructions should be included in the program.
In the power down mode the oscillator is stopped, and the
A typical 80C51 assembler will still assemble instructions, instruction that invokes power down is the last instruction
even if they are written in violation of the restrictions men- executed. The on-chip RAM and Special Function Regis-
tioned above. It is the responsibility of the controller user to ters retain their values until the power down mode is termi-
know the physical features and limitations of the device nated. The only exit from power down is a hardware reset.
being used and adjust the instructions used correspond- Reset redefines the SFRs but does not change the on-chip
ingly. RAM. The reset should not be activated before V CC is
restored to its normal operating level and must be held
Program Memory Lock Bits active long enough to allow the oscillator to restart and sta-
bilize.
On the chip are two lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi- P1.0 and P1.1 should be set to ’0’ if no external pullups are
tional features listed in the table below: used, or set to ’1’ if external pullups are used.

Lock Bit Protection Modes(1) Programming The Flash

The AT89C1051 is shipped with the 1K byte of on-chip
Program Lock Bits PEROM code memory array in the erased state (i.e., con-
LB1 LB2 Protection Type tents = FFH) and ready to be programmed. The code mem-
1 U U No program lock features. ory array is programmed one byte at a time. Once the array
is programmed, to re-program any non-blank byte, the
2 P U Further programming of the Flash entire memory array needs to be erased electrically.
is disabled.
Internal Address Counter: The AT89C1051 contains an
3 P P Same as mode 2, also verify is internal PEROM address counter which is always reset to
disabled. 000H on the rising edge of RST and is advanced by apply-
Note: 1. The Lock Bits can only be erased with the Chip Erase ing a positive going pulse to pin XTAL1.
operation.

4-7
Programming Algorithm: To program the AT89C1051, Data Polling: The AT89C1051 features Data Polling to
the following sequence is recommended. indicate the end of a write cycle. During a write cycle, an
1. Power-up sequence: attempted read of the last byte written will result in the com-
Apply power between VCC and GND pins plement of the written data on P1.7. Once the write cycle
Set RST and XTAL1 to GND has been completed, true data is valid on all outputs, and
2. Set pin RST to ‘H’ the next cycle may begin. Data Polling may begin any time
Set pin P3.2 to ‘H’ after a write cycle has been initiated.
3. Apply the appropriate combination of ‘H’ or ‘L’ logic Ready/Busy: The Progress of byte programming can also
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the be monitored by the RDY/BSY output signal. Pin P3.1 is
programming operations shown in the PEROM Pro- pulled low after P3.2 goes High during programming to indi-
gramming Modes table. cate BUSY. P3.1 is pulled High again when programming is
To Program and Verify the Array: done to indicate READY.
4. Apply data for Code byte at location 000H to P1.0 to Program Verify: If lock bits LB1 and LB2 have not been
P1.7. programmed code data can be read back via the data lines
5. Raise RST to 12V to enable programming. for verification:
6. Pulse P3.2 once to program a byte in the PEROM array 1. Reset the internal address counter to 000H by bringing
or the lock bits. The byte-write cycle is self-timed and RST from ’L’ to ’H’.
typically takes 1.2 ms. 2. Apply the appropriate control signals for Read Code data
7. To verify the programmed data, lower RST from 12V to and read the output data at the port P1 pins.
logic ‘H’ level and set pins P3.3 to P3.7 to the appropiate 3. Pulse pin XTAL1 once to advance the internal address
levels. Output data can be read at the port P1 pins. counter.
8. To program a byte at the next address location, pulse 4. Read the next code data byte at the port P1 pins.
XTAL1 pin once to advance the internal address counter. 5. Repeat steps 3 and 4 until the entire array is read.
Apply new data to the port P1 pins. The lock bits cannot be verified directly. Verification of the
9. Repeat steps 5 through 8, changing data and advancing lock bits is achieved by observing that their features are
the address counter for the entire 1K byte array or until enabled.
the end of the object file is reached.
10.Power-off sequence:
set XTAL1 to ‘L’
set RST to ‘L’
Turn VCC power off
Flash Programming Modes
Mode RST/VPP P3.2/PROG P3.3 P3.4 P3.5 P3.7
Write Code Data(1)(3) 12V L H H H

Read Code Data(1) H H L L H H

Write Lock Bit-1 12V H H H H

Bit-2 12V H H L L

Chip Erase 12V (2) H L L L

Read Signature Byte H H L L L L

Note: 1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
XTAL1 pin.
2. Chip Erase requires a 10-ms PROG pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY.

4-8 AT89C1051
 AT89C1051

Chip Erase: The entire PEROM array (1K byte) and the Programming Interface
two Lock Bits are erased electrically by using the proper
Every code byte in the Flash array can be written and the
combination of control signals and by holding P3.2 low for
entire array can be erased by using the appropriate combi-
10 ms. The code array is written with all “1”s in the Chip
nation of control signals. The write operation cycle is self-
Erase operation and must be executed before any non-
timed and once initiated, will automatically time itself to
blank memory byte can be re-programmed.
completion.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 001H, and 002H, except that P3.5 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 11H indicates 89C1051

Figure 3. Programming the Flash Memory Figure 4. Verifying the Flash Memory
5V 5V
AT89C1051 AT89C1051
RDY/BSY P3.1 VCC VCC

PROG P3.2 P1 PGM VI H P1 PGM

P3.2
DATA DATA
P3.3 P3.3
SEE FLASH P3.4 SEE FLASH P3.4
PROGRAMMING PROGRAMMING
MODES TABLE P3.5 MODES TABLE P3.5
P3.7 P3.7

XTAL1 RST VI H/ VPP XTAL1 RST VI H

TO INCREMENT GND GND
ADDRESS COUNTER

4-9
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol Parameter Min Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 µA
tDVGL Data Setup to PROG Low 1.0 µs
tGHDX Data Hold After PROG 1.0 µs
tEHSH P3.4 (ENABLE) High to VPP 1.0 µs
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold After PROG 10 µs
tGLGH PROG Width 1 110 µs
tELQV ENABLE Low to Data Valid 1.0 µs
tEHQZ Data Float After ENABLE 0 1.0 µs
tGHBL PROG High to BUSY Low 50 ns
tWC Byte Write Cycle Time 2.0 ms
tBHIH RDY/BSY to Increment Clock Delay 1.0 µs
tIHIL Increment Clock High 200 ns
Note: Only used in 12-volt programming mode.

Flash Programming and Verification Waveforms

4-10 AT89C1051
 AT89C1051

Absolute Maximum Ratings

Operating Temperature ........................-55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ...........................-65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground........................... -1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage...................................6.6V conditions for extended periods may affect device
reliability.
DC Output Current ............................................25.0 mA

DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol Parameter Condition Min Max Units
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage(1) IOL = 20 mA, VCC = 5V 0.50 V
(Ports 1, 3) IOL = 10 mA, VCC = 2.7V
VOH Output High Voltage IOH = -80 µA, VCC = 5V ± 10% 2.4 V
(Ports 1, 3)
IOH = -30 µA 0.75 VCC V
IOH = -12 µA 0.9 VCC V
IIL Logical 0 Input Current VIN = 0.45V -50 µA
(Ports 1, 3)
ITL Logical 1 to 0 Transition VIN = 2V, VCC = 5V ± 10% -750 µA
Current (Ports 1, 3)
ILI Input Leakage Current 0 < VIN < VCC ±10 µA
(Port P1.0, P1.1)
VOS Comparator Input Offset VCC = 5V 20 mV
Voltage
VCM Comparator Input Common 0 VCC V
Mode Voltage
RRST Reset Pulldown Resistor 50 300 KΩ
CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
ICC Power Supply Current Active Mode, 12 MHz, VCC = 6V/3V 15/5.5 mA
Idle Mode, 12 MHz, VCC = 6V/3V P1.0 & 5/1 mA
P1.1 = 0V or VCC
Power Down Mode(2) VCC = 6V P1.0 & P1.1 = 0V or VCC 100 µA
VCC = 3V P1.0 & P1.1 = 0V or VCC 20 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 20 mA
Maximum total IOL for all output pins: 80 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power Down is 2V.

4-11
External Clock Drive Waveforms

External Clock Drive

Symbol Parameter VCC = 2.7V to 6.0V VCC = 4.0V to 6.0V Units
Min Max Min Max
1/tCLCL Oscillator Frequency 0 12 0 24 MHz
tCLCL Clock Period 83.3 41.6 ns
tCHCX High Time 30 15 ns
tCLCX Low Time 30 15 ns
tCLCH Rise Time 20 20 ns
tCHCL Fall Time 20 20 ns

AC Testing Input/Output Waveforms(1) Float Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a Note: 1. For timing purposes, a port pin is no longer float-
logic 1 and 0.45V for a logic 0. Timing measurements ing when a 100 mV change load voltage occurs. A
are made at VIH min. for a logic 1 and VIL max. for a port pin begins to float when a 100 mV change
logic 0. from the loaded VOH/VOL level occurs.

4-12 AT89C1051
 AT89C1051

AT89C1051
TYPICAL ICC - ACTIVE (85°C)
20
Vcc=6.0V

I 15
C Vcc=5.0V
C 10
Vcc=3.0V
m
A 5

0
0 6 12 18 24
FREQUENCY (MHz)

AT89C1051
TYPICAL ICC - IDLE (85°C)
3
Vcc=6.0V

I
C 2 Vcc=5.0V
C

m 1
A
Vcc=3.0V

0
0 3 6 9 12
FREQUENCY (MHz)

AT89C1051
TYPICAL ICC vs. VOLTAGE- POWER DOWN (85°C)
20

I 15
C
C 10

µ
A 5

0
3.0V 4.0V 5.0V 6.0V
Vcc VOLTAGE

Notes: 1. XTAL1 tied to GND for ICC (power down)

2. P.1.0 and P1.1 = VCC or GND
3. Lock bits programmed

4-13
Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
12 2.7V to 6.0V AT89C1051-12PC 20P3 Commercial
AT89C1051-12SC 20S (0°C to 70°C)
AT89C1051-12PI 20P3 Industrial
AT89C1051-12SI 20S (-40°C to 85°C)
AT89C1051-12PA 20P3 Automotive
AT89C1051-12SA 20S (-40°C to 105°C)
24 4.0V to 6.0V AT89C1051-24PC 20P3 Commercial
AT89C1051-24SC 20S (0°C to 70°C)
AT89C1051-24PI 20P3 Industrial
AT89C1051-24SI 20S (-40°C to 85°C)

Package Type
20P3 20 Lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)
20S 20 Lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

4-14 AT89C1051