Main
Main
use IEEE.std_logic_1164.all;
entity main is
port(a,b:in std_logic_vector(3 downto 0);
as: in std_logic;
carry: out std_logic ;
y:out std_logic_vector(6 downto 0));
end;
component addsous is
a,b : in std_logic_vector(3 downto 0);
as: in std_logic;
component aff7seg is
port (
num: in STD_LOGIC_VECTOR (3 downto 0);
seg: out STD_LOGIC_VECTOR (6 downto 0));
end component;
end;