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Lab 07: Digital Photo Frame: Submission Deadlines: Source Code: 18:30, Nov. 26, 2019 23:59, Dec. 1, 2019

This document provides instructions for Lab 07 on designing a digital photo frame with transition effects using Verilog. Students are asked to implement a VGA controller with two modes: (1) make an image scroll left or right on the display; and (2) operate in shift or split mode using buttons to transition the image in different directions. Source code is due on November 26th and a report is due on December 1st. The lab objectives are to practice modeling finite state machines and controlling VGA display and I/Os on an FPGA board.

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Jonathan Jufeno
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33 views

Lab 07: Digital Photo Frame: Submission Deadlines: Source Code: 18:30, Nov. 26, 2019 23:59, Dec. 1, 2019

This document provides instructions for Lab 07 on designing a digital photo frame with transition effects using Verilog. Students are asked to implement a VGA controller with two modes: (1) make an image scroll left or right on the display; and (2) operate in shift or split mode using buttons to transition the image in different directions. Source code is due on November 26th and a report is due on December 1st. The lab objectives are to practice modeling finite state machines and controlling VGA display and I/Os on an FPGA board.

Uploaded by

Jonathan Jufeno
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Lab 07: Digital Photo Frame

(Nov. 14, 2019)

Submission deadlines:
Source Code: 18:30, Nov. 26, 2019
Report 23:59, Dec. 1, 2019

Objective
➢ To be familiar with modeling finite state machines with Verilog.
➢ To be familiar with the control of VGA Display and other I/Os
on the FPGA demo-board.

Action Items

In this lab, you are asked to implement a digital photo frame


with some transition effects on the VGA display.
Choose the image you want and use PicTrans.exe to generate
your own .coe file (make sure it is an appropriate image).

1. (30%) Design a VGA controller that make your image scrolls left

or right.

The behavior of the design is explained as follows：


● In the beginning or when pressing the rst button, the VGA display will
show the image at the origin position.
● When en = 1, dir = 0, the image scrolls to the left in a column-by-column
manner at the frequency of 100MHz divided by 222

1
● When en = 1, dir = 1, the image scrolls to the right in a column-by-
column manner at the frequency of 100MHz divided by 222

● When en = 0, the image holds and stops scrolling.


The controller has the following input ports:
input clk,
input rst,
input en,
input dir,
and the following output ports:

2
output [3:0] vgaRed,
output [3:0] vgaGreen,
output [3:0] vgaBlue,
output hsync,
output vsync,
IO Connection:
clk connected to W5
rst connected to U18 (btnC)
dir connected to V16
en connected to V17
vgaRed connected to pin N19, J19, H19, G19
vgaGreen connected to pin J18, K18, L18, N18
vgaBlue connected to pin D17, G17, H17, J17
hsync connected to pin P19
vsync connected to pin R19

Demo Video:
https://youtu.be/xF6bc_ROIBA

2. (70%) Design a VGA controller with two modes to operate by

the corresponding buttons.

The behavior of the design is explained as follows：


● In the beginning or when pressing the rst button, the VGA display will
show the image at the origin position
● When the button shift is pressed, the image disappears from right to left
and then the same picture appears from top to bottom.

3
● When the button split is pressed, the image is split into 4 pieces with 4
different directions to shift and disappear. The image will show again
after the image completely disappears (after a cycle).
a. The top left piece shifts upward.
b. The top right piece shifts rightward.
c. The bottom right piece shifts leftward.
d. The bottom left piece shifts downward.

● When the VGA controller operates in either the shift or split mode, only
the rst button is effective.

4
The controller has the following input ports:
input clk,
input rst,
input shift,
input split,
and the following output ports:
output [3:0] vgaRed,
output [3:0] vgaGreen,
output [3:0] vgaBlue,
output hsync,
output vsync,
IO Connection:
clk connected to W5
rst connected to U18 (btnC)
shift connected to T17 (btnR)
split connected to W19 (btnL)
vgaRed connected to pin N19, J19, H19, G19
vgaGreen connected to pin J18, K18, L18, N18
vgaBlue connected to pin D17, G17, H17, J17
hsync connected to pin P19
vsync connected to pin R19

Demo Video:
https://youtu.be/n_S_Jtj8iEQ

Attention:
1. You should hand in the file named lab07_1.v and lab07_2.v as top
module. If you create several modules for your design, upload them
all.
2. You should also hand in your report as lab07_report_StudentID.pdf
(i.e., lab07_report_105062224.pdf).
3. You should be able to answer questions of this lab from TA during the
demo.
4. You need to generate bitstream before demo.

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