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Digital Systems 2 - Chapter 7 - Assignment 1 - Latches

1) The document discusses different types of latches including S-R latches and D latches. It provides truth tables and examples of how the latches work. 2) Several problems are presented involving determining the output waveforms of S-R latches and D latches based on given input waveforms. 3) The final problem describes how a latch can be used as a contact bounce eliminator by holding the output steady until the input contact bounce settles.

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Bonolo Tsela
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281 views

Digital Systems 2 - Chapter 7 - Assignment 1 - Latches

1) The document discusses different types of latches including S-R latches and D latches. It provides truth tables and examples of how the latches work. 2) Several problems are presented involving determining the output waveforms of S-R latches and D latches based on given input waveforms. 3) The final problem describes how a latch can be used as a contact bounce eliminator by holding the output steady until the input contact bounce settles.

Uploaded by

Bonolo Tsela
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Digital Systems 2 (EIDSY2A) Chapter 7: Assignment 1 Latches

1. Check-up: (6 marks)

1.1 List three types of latches.


1.2 Develop the truth table for the active-HIGH input S-R latch in Figure 1.

Figure 1
1.3 What is the Q output of a D latch when EN = 1 and D = 1?

2. Self-Test: (3 marks)

Choose the correct answer:

2.1 An active HIGH input S-R latch is formed by the cross-coupling of:
(a) two NOR gates (b) two NAND gates (c) two OR gates (d) two AND gates

2.2 Which of the following is not true for an active LOW input S-R latch:
(a) S = 1, R = 1, Q = NC, Q = NC (b) S = 0, R = 1, Q = 1, Q = 0
(c) S = 1, R = 0, Q = 1, Q = 0 (d) S = 0, R = 0, Q = 1, Q = 1

2.3 For what combinations of the inputs D and EN will a D latch reset:
(a) D = LOW, EN = LOW (b) D = LOW, EN = HIGH
(c) D = HIGH, EN = LOW (d) D = HIGH, EN = HIGH

3. Problems: (20 marks)

3.1 If the waveforms in Figure 2 are applied to an active-LOW S-R latch, draw the resulting Q output
waveform in relation to the inputs. Assume that Q starts LOW.

Figure 2

3.2 Solve Problem 3.1 for the input waveforms in Figure 3 applied to an active-High S - R latch.

R
Figure 3

3.3 Solve Problem 3.1 for the input waveform in Figure 4.

R
Figure 4
Digital Systems 2 (EIDSY2A) Chapter 7: Assignment 1 Latches

3.4 For a gated S-R latch, determine the Q and Q outputs for the inputs in Figure 5. Show them in proper relation
to the enable input. Assume that Q starts LOW.

Figure 5

3.5 Determine the output of a gated D latch for the inputs in Figure 6.

Figure 6

3.6 Determine the output of a gated D latch for the inputs in Figure 7.

Figure 7

3.7 For a gated D latch, the waveforms shown in Figure 8 are observed on its inputs. Draw the timing diagram
showing the output waveform you would expect to see at Q if the latch is initially RESET.

Figure 8

3.8 Sketch the circuit and describe the operation of a Latch as a Contact-Bounce Eliminator.

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