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Digital Systems 2 - Chapter 7 - Assignment 2 - Flip Flops

This document discusses flip-flops and their operation. It includes self-test questions and problems involving drawing output waveforms of D and J-K flip-flops based on given clock and input signals. The problems involve edge-triggered positive and negative flip-flops analyzing how the output changes in response to inputs.

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Bonolo Tsela
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77 views3 pages

Digital Systems 2 - Chapter 7 - Assignment 2 - Flip Flops

This document discusses flip-flops and their operation. It includes self-test questions and problems involving drawing output waveforms of D and J-K flip-flops based on given clock and input signals. The problems involve edge-triggered positive and negative flip-flops analyzing how the output changes in response to inputs.

Uploaded by

Bonolo Tsela
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Digital Systems 2 (EIDSY2A) Chapter 7: Assignment 2 Flip-Flops

1. Check-up: (8 marks)

1.1 Describe the main difference between a gated D latch and an edge-triggered D flip-flop.
1.2 How does a J-K flip-flop differ from a D flip-flop in its basic operation?
1.3 Assume that the flip-flop in Figure 1 is negative edge-triggered. Describe the output waveform for the same
CLK and D waveforms.

Figure 1

2. Self-Test: (6 marks)

Choose the correct answer.

2.1 A flip-flop changes its state during the:


(a) complete operational cycle (b) falling edge of the clock pulse
(c) rising edge of the clock pulse (d) both answers (b) and (c)

2.2 The purpose of the clock input to a flip-flop is to:


(a) clear the device (b) set the device
(c) always cause the output to change states
(d) cause the output to assume a state dependent on the controlling (J-K or D) inputs.

2.3 For an edge-triggered D flip-flop:


(a) a change in the state of the flip-flop can occur only at a clock pulse edge
(b) the state that the flip-flop goes to depends on the D input
(c) the output follows the input at each clock pulse
(d) all of these answers

2.4 A feature that distinguishes the J-K flip-flop from the D flip-flop is the:
(a) toggle condition (b) preset input
(c) type of clock (d) clear input

2.5 A flip-flop is SET when:


(a) J = 0, K = 0 (b) J = 0, K = 1 (c) J = 1, K = 0 (d) J = 1, K = 1

2.6 A J-K flip-flop with J = 1 and K = 1 has a 10 kHz clock input. The Q output is:
(a) constantly HIGH (b) constantly LOW
(c) a 10 kHz square wave (d) a 5 kHz square wave

3. Problems: (27 marks)

3.1 Two edge-triggered J-K flip-flops are shown in Figure 2. If the inputs are as shown, draw the Q output of
each flip-flop relative to the clock, and explain the difference between the two. The flip-flops are initially
RESET.

Figure 2
Digital Systems 2 (EIDSY2A) Chapter 7: Assignment 2 Flip-Flops

3.2 The Q output of an edge-triggered D flip-flop is shown in relation to the clock signal in Figure 3. Determine the
input waveform on the D input that is required to produce this output if the flip-flop is a positive edge-triggered
type.

Figure 3

3.3 Draw the Q output relative to the clock for a D flip-flop with the inputs as shown in Figure 4. Assume positive
edge-triggering and Q initially LOW.

Figure 4

3.4 Solve Problem 3.3 for the inputs in Figure 5.

Figure 5

3.5 For a positive edge-triggered D flip-flop with the input as shown in Figure 6, determine the Q output relative
to the clock. Assume that Q starts LOW.

Figure 6

3.6 Solve Problem 3.5 for the input in Figure 7.

Figure 7

3.7 Determine the Q waveform relative to the clock if the signals shown in Figure 8 are applied to the inputs of the
J-K flip-flop. Assume that Q is initially LOW.

Figure 8
Digital Systems 2 (EIDSY2A) Chapter 7: Assignment 2 Flip-Flops

3.8 For a negative edge-triggered J-K flip-flop with the inputs in Figure 9, develop the Q output waveform relative to
the clock. Assume that Q is initially LOW.

Figure 9

3.9 The following serial data are applied to the flip-flop through the AND gates as indicated in Figure 10. Determine
the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is
initially 0 and that PRE and CLR are HIGH. Rightmost bits are applied first.
J1: 1 0 1 0 0 1 1; J2: 0 1 1 1 0 1 0; J3: 1 1 1 1 0 0 0;
K1: 0 0 0 1 1 1 0; K2: 1 1 0 1 1 0 0; K3: 1 0 1 0 1 0 1 17.

3.10 For the circuit in Figure 10, complete the timing diagram in Figure 11 by showing the Q output (which is
initially LOW). Assume PRE and CLR remain HIGH.

Figure 10 Figure 11

3.11 Solve Problem 3.10 with the same J and K inputs but with the PRE and CLR inputs as shown in Figure 12 in
relation to the clock.

Figure 12

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