ASIC DESIGN TYPES

ASIC is mainly Divided into two Divisions

1)Logical Design(LD)
2)Physical Design(PD)

Physical Design is Physical implementation of Design

● In Physical Design mainly Six inputs are present
1. Logical libraries --> format is .lib --->given by Vendors
2. Physical libraries -->format is .lef --->given by vendors
3. Technology file -->format is .tf --->given by fabrication peoples
4. TLU+ file -->format is .TLUP-->given by fabrication people
5. Netlist --->format is .v -->given by Synthesis People
6. Synthesis Design Constraints -->format is .SDC -->given by Synthesis People

PHYSICAL DESIGN PROCESS.

1. DATA PREPARATION.
2. FLOOR PLAN.
3. POWER PLAN-->POWER ROUTING [PRE ROUTE]
4. PLACEMENT.
5. CLOCK TREE SYNTHESIS.-->CLOCK ROUTING.
6. ROUTING.-->DATA ROUTING.-->[POST ROUTE]
7. CHIP FINISHING.
8. VERIFICATION.
9. GDSII FILE.

LOGIC LIBRARIES
Logical libraries :Format is .lib(liberty)
1. Timing information of Standard cells,Soft macros,Hard macros.
2. Functionality information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold,Recovery,Removal time are
present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models, Non linear delay
models,CCS models.
8. Functionality is used for Optimization Purpose.
9. And also Contain Power information.
 10. And contains Leakage power for Default cell,Leakage Power Density for
cell,Default Input voltage , Out put voltage.

And PVT contains ------------>On Chip Variations(BC,WC)

------------>Cell leakage Power
---------->Internal Power
---------->Rise Transition
----------->Fall transition
---------->>Setup rise
----------->Setup fall
----------->Hold rise
------------>Hold fall
------------>Minimum pulse width high
------------->Minimum pulse width low
------------->Recovery rise
-------------->Removal fall
--------------->Cell rise
-------------->Cell fall
-------------->Pin Capacitance

Cell level information

1. Cell name
2. Area(represent with Nand Equ Area)
3. Power (Funtion of input transition, Total output net Cap )
4. Funtionality
5. Delay
6. Max Cap
7. Max Trans
8. Foot Print

And it also Contains K-Factor

And it also contain WIRE LOAD MODELS

And it contains A view(sub directory) i.e. LM (Logical Model view)view.

It contains logical libraries.

PHYSICAL LIBRARIES
Physical libraries: format is .lef(Layout Exchange Format):
1. physical information of std cells,macros,pads.
2. Pin information.
3. Define unit tile(sites) placement.
4. Minimum Width of Resolution.
 5. Hight of the placement Rows .
6. Preferred routing Directions.
7. Pitch of the routing tracks.
8. Antena Rules.
9. Routing Blockages,Macro Blockage

Macro/Stad Cells :-------------->Cell neame

-------------->Size(Dimensions,Area)
------------->Pin
------------->Port
------------->Layer
------------->Direction

Pins information : --------------->Direction(Input,Output,INOUT)

--------------->Use(Signal,Power,Ground)
--------------->Antena Gate Area
--------------->layer

LEFs are 3 Types : .Macro lef (Macro Info)

.StdCell lef(Standard Cell Info )
.Tech lef(Layer,Via Info)

In physical info height,area,width are present.

and also it contains two views
1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route

TECHNOLOGY FILE
Technology file: format is .tf:
1. It contains Name,Number conventions of layer and via
2. It contains Physical,electrical characteristics of layer and via
3. In Physical characteristics Min width,Min Spacing,Min Height are present.
4. In Electrical characteristics Max Current Density is present.
5. Units and Precisions of layer and via .
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via
are present.

Layer Info :
 1. Mask Name
2. Visible
3. Selectable
4. Line Style(Solid)
5. Pattern
6. Pitch
7. Cut Layer

TLU+ files: format is .TLUP:

1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+,Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names.

SDC
SDC :Format is .SDC :
These Constraints are timing Constraints .
These Constraints are used for to meet timing requirements.

Constraints are
1. CLOCK DEFINITIONS:Create Clock Period.
2. Generated Clock Definitions
3. Input Delay
4. Output Delay
5. I/O delay
6. Max delay
7. Min Delay
8. --------------->Exceptions<-------------------------
9. Multi cycle path
10. False path
11. Half cycle path
12. Disable timing arcs
13. Case Analysis
Multi cycle path, False path are Exceptions.

And it also contains

--------------->Clock latency
--------------->Clock Uncertainty
--------------->Clock Transition

--------------->Clock Gating setup

--------------->Clock Gating Hold
--------------->Clock Driving cell

TLU+
TLU+ files: format is .TLUP:
1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+,Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names.

NETLIST
Netlist: Format is .V
It contains Logical connectivity Of all Cell(Std cells,Macros).
It contain List of nets.
In the design, for Knowing the connectivity by using Fly lines.

.V ---------->Logical Connectivity
.ddc-------->logical connectivity, Scan chain info, .Scandef file info, Gate level
Description

FLOOR PLAN
FLOOR PLAN:
AT CHIP LEVEL:

FLOOR PLAN IS A STEP WHERE WE CREATING THE PAD CELLS .

AND SPACIFYING POSITIONS, PLACING PAD CELLS.

AND INSERTING PAD FILLER CELLS,FOR WELL CONTINUITY.

WELL CONTINUITY , WELL CONTINUITY MEANS IF THE WELL IS NOT CONTINUOUS

THEN WE HAVE TO CREATE SPECIAL MASKS.

IF WELL IS CONTINUOUS THEN THERE IS NO NEED OF CREATING SPECIAL MASKS.

IN FLOOR PLAN MAIN IMPORTANT IS MACRO PLACEMENT.

MACRO IS NOTHING BUT IP'S, MEMORY CELLS.

IF WE HAVE A LARGE CIRCUIT THEN THERE IS NO NEED OF CREATING EVERY

TIME.

THE CIRCUIT IS AVAILABLE IN THE MARKET IN THE FORM OF MACRO OR IP.

MACROS ARE TWO TYPES:(i)HARD MACRO.

(ii)SOFT MACRO.

HARD MACRO:THE CIRCUIT IS FIXED. AND WE DON'T NO WHICH TYPE OF GATES

USING INSIDE.WE KNOW THE ONLY TIMING INFORMATION.WE DON'T KNOW THE
FUNCTIONALITY INFORMATION.

SOFT MACRO:THE CIRCUIT IS NOT FIXED.WE KNOW WHICH TYPE OF GATES USING
INSIDE.WE KNOW THE TIMING INFORMATION. WE KNOW THE FUNCTIONALITY
INFORMATION.

AND IN FLOORPLAN WE ALSO CREATING THE BLOCKAGES.

BLOCKAGES:BLOCKAGES ARE THE IF LET TAKE WE WANT SOME AREA

WHERE NO ONE STD CELL PLACE. FOR THAT PURPOSE WE ARE USING
BLOCKAGES.

BLOCKAGES ARE TWO TYPES:(i)SOFT BLOCKAGES

(ii)HARD BLOCKAGES.

SOFT BLOCKAGES MEANS NO ONE STD CELLS PLACED FIRST, BUT AT THE TIME
OF OPTIMIZATION ONLY BUFFERS ARE PLACED, AND THESE ARE USED AT
(i)BETWEEN TWO MACROS,
(ii)AND BETWEEN MACRO AND BOARDERS.
HARD BLOCKAGES MEANS NO ONE STD CELLS PLACED.AND THESE ARE USED AT
THE AROUND THE MACRO.BECAUSE PIN ACCESSING.

IN THE FLOOR PLAN MAIN OBJECTS ARE MACRO PLACEMENT.,

DEFINE ASPECT
RATIO(HEIGHT/WIDTH).
I/O PLACEMENTS.
CORE AREA INITIALIZATION.

CORE AREA :CORE AREA IS DEFINED FOR THE PLACEMENT OF STD CELLS,AND
MACROS.

CORE AREA DEPENDS ON (i)ASPECT RATIO

(ii)UTILIZATION.

UTILIZATION=(STD CELL AREA+MACRO AREA+BLOCKAGE AREA)/TOTAL AREA.

STD CELL UTILIZATION=(STD CELL AREA)/

(TOTAL CORE AREA -(MACRO AREA+BLOCKAGE AREA)).

THESE STD CELLS ARE PLACED IN ROWS.

----->I/O PLACEMENT.
IN I/O PLACEMENT WE HAVING PADS.

PADS ARE USED FOR INTERFACING PURPOSE,AND THESE ARE USED FOR
PROVIDING POWER SUPPLY, DATA SIGNAL,CLOCK SIGNAL.

EASILY THESE CAN BE USED AS PORTS.

PADS ARE DIFFERENT TYPES: (i)POWER PADS,

(ii)SIGNAL PADS.
(iii)CORNER PADS.
(iv)I/O PADS.

MACRO PLACEMENT (GUIDE LINES)

Macro Placement Depend On

1. FLY LINES
2. PORTS COMMUNICATIONS.
3. MACRO'S ARE PLACED AT BOUNDARIES-->Uniform area for Stad cells
4. MACRO GROUPING [LOGICAL HIERARCHY]
 5. SPACING BETWEEN MACRO'S
6. MACRO ALIGNMENT
7. NOTCHES AVOIDING
8. ORIENTATION
9. BLOCKAGES
10. AVOID CRIS CROSS PLACEMENT OF MACROS
● MACROS ARE ROTATED AS REQUIRED TO OPTIMIZE WIRE LENGTH DURING
AUTOMATIC MACRO PLACEMENT.
● TYPICALLY , MACROS ARE PLACED AROUND EDGES OF BLOCKS,KEEPING
ARE LARGE MAIN AREA FOR STD CELLS
● LEAVE A HALO SPACE BETWEEN MACROS ON ALL SIDES
● FOR A NON PIN SIDES OF MACROS A MINIMAL SEPARATION .IS ADEQUATE.
● FOR PIN SIDES OF MACROS A LARGER SEPARATION IS APPROPRIATE.
● ALLOW CHANNELS FOR ROUTING PIN ACCESS AND POSSIBLE BUFFER
INSERTION
● LEAVE SPACE BETWEEN MACRO AND THE EDGE OF CHIP/BLOCK, TO
ALLOW FOR BUFFERS INSERTION AND POWER STRIPES TO FEED STD CELL
ROWS BETWEEN MACRO AND BLOCK EDGE.

CALCULATION FOR DISTANCE BETWEEN MACROS:

NO.OF PINS (X) PITCH

DISTANCE BETWEEN MACROS= ------------------------------------------------------
AVAILABLE LAYERS/TOTAL LAYERS

FLOOR PLAN (PAD CELLS)

IN FLOOR PLAN

1. CREATE PHYSICAL ONLY PAD CELLS. PHYSICAL ONLY CELLS MEANS ONLY
THOSE HAVING PHYSICAL INFORMATION ONLY. NO LOGICAL INFORMATION
PRESENT. AND THEY DON'T HAVE TIMING INFORMATION ALSO.
2. PHYSICAL ONLY PAD CELLS ARE (i)VDD,VSS PADC CELLS,(ii)CORNER PAD
CELLS.
3. PAD CELLS ACTS LIKE AS PORTS AT THE CHIP LEVEL.
4. CHIP OUTSIDE PINS ARE CONNECTED TO THE INNER CHIP PADS.
5. PADS TYPES:(i)POWER PADS, (ii)DATA PADS .
6. FOR THE POWER SUPPLY TO THE ALL PADS CREATING A PAD POWER RING
.
7. VDD,VSS PADS ARE CONNECTED TO THE CORE VDD,VSS POWER RINGS.
8. FOR FILLING THE GAPS BETWEEN THE PADS FILLED BY PAD FILLER CELLS.
9. THESE PAD FILLER CELLS ARE FOR WELL CONTINUITY.

PHYSICAL ONLY CELLS ARE:

 1. PAD CELLS.
2. END CAP CELLS.
3. TAP CELLS.
4. DECAP CELLS.

FLOORPLAN(TIMING)
FLOOR PLAN [TIMING]:
IN FLOOR PLAN TIMING IS ALSO IMPORTANT.

BEFORE GOING TO TIMING , PERFORM GLOBAL ROUTING AND ANALYZE

CONGESTION.

1. BY PERFORMING THE GLOBAL ROUTING EXTRACT APPROPRIATE R,C

VALUES.
2. IF IN THE DESIGN CONGESTION PRESENT, GO TO THE CONGESTION STEP
AND MODIFY THE P - NET OPTIONS FULL TO PARTIAL.
3. PERFORM GLOBAL ROUTING AND ANALYZE CONGESTION.
4. IF IN THE DESIGN CONGESTION PRESENT MODIFY THE P-NET OPTIONS
PARTIAL TO COMPLETE.
5. EXTRACT R,C VALUES , ANALYZE THE TIMING.

EXTRACT PARASITIC NET R,C VALUES AND GENERATE A TIMING REPORT.

OPTIMIZE TIMING [DEFAULT]-->IF THE TIMING IS NOT ACCEPTED REPEAT

GLOBAL ROUTING, ANALYZE CONGESTION , TIMING IF NOT ACCEPTED.

PERFORM OPTIMIZE TIMING[HIGH EFFORT]---->OPTIMIZE HIGH EFFORT.

IF THE TIMING IS NOT ACCEPTED , MODIFY THE FLOOR PLAN

/RESYNTHESIZE.

AFTER ACCEPTING THE CONGESTION, TIMING THEN WRITE OUT THE .def
file

SAVE THE DESIGN .AND THESE .def FILE IS GIVEN AS INPUT TO THE
PLACEMENT.
FLOORPLAN (CONGESTION)
CONGESTION: REQUIRED NO.OF ROUTING RESOURCES ARE GREATER THAN
THE NO.OF AVAILABLE ROUTING RESOURCES

1. FOR THE CONGESTION ANALYSIS WE HAVE TO DO FIRST PERFORM

GLOBAL ROUTING.
2. BY USING GLOBAL ROUTING CALCULATING CONGESTION.
3. ANALYZE THE CONGESTION [IF WE HAVE CONGESTION MEANS ROUTING
PROBLEM(MAY CAUSES SHORTS)].
4. IF THE CONGESTION IS PRESENT THEN MODIFY THE PLACEMENT
STRATEGY PARAMETERS LIKE BLOCKAGES,OFFSET,KEEP OUT
MARGINS,SLIVER SIZE AND MACRO, STD CELL CONSTRAINTS.
5. PERFORM CONGESTION DRIVEN VIRTUAL FLAT PLACEMENT.CONGESTION
DRIVEN MEANS MOVING STD CELLS FAR AWAY.
6. REANALYZE THE CONGESTION. IF CONGESTION IS NOT SATISFIED.
7. PERFORM HIGH EFFORT CONGESTION DRIVEN VIRTUAL FLAT PLACEMENT.
8. REANALYZE THE CONGESTION.
9. IF CONGESTION IS NOT SATISFIED.
10. MODIFY THE FLOOR PLAN.
11. IF CONGESTION IS SATISFIED.
12. FIX MACRO PLACEMENT.

CONGESTION CAUSES :

1. MISSING PLACEMENT BLOCKAGES

2. IMPROPER MACRO PLACEMENT AND MACRO CHANNEL
3. HIGH CELL DENSITY(HIGH LOCAL UTILIZATION)
4. VERY ROBUST POWER NETWORK
5. EXCESS POWER STACK VIAS
6. PIN DENSITY OF CELLS, MACROS
7. DUE TO PORTS

MORE FIXES :

1. HIGH CELL DENSITY PROBLEM---->BY USING COORDINATES WE REDUCE

UTILIZATION
2. PARTIAL PLACEMENT BLOCKAGES
3. MAX UTILIZATION %
4. INCREASING SPACING BETWEEN MACROS
5. FLIP MACRO(DO NOT FLIP 90 DEGREES)
6. MODIFY KEEP OUT CONSTRAINTS
 7. GIVING HARD KEEP CHANNEL WIDTH

POWER PLANNING
IN POWER PLANNING

IR DROP : VOLTAGE TRANSFER IN METAL A DROP OCCURS DUE TO

RESISTANCE OF METAL.THIS IS KNOWN AS IR DROP.

IR DROPS ARE TWO TYPES (i)STATIC IR DROP,(ii)DYNAMIC IR DROP.

STATIC IR DROP: INDEPENDENT OF THE CELL SWITCHING THE DROP IS

CALCULATED WITH THE HELP OF WIRE RESISTANCE.

IMPROVE STATIC IR DROP: (i)WIDTH OF WIRE INCREASE, OR (ii) INCREASE

THE NO.OF WIRES

DYNAMIC IR DROP: IR DROP IS CALCULATED WITH THE HELP OF THE

SWITCHING OF THE CELLS.

IMPROVE DYNAMIC IR DROP:(i)PLACING DCAP CELLS IN BETWEEN

THEM,(iii)INCREASE THE NO OF STRAPS.

ELECTROMIGRATION: WHEN HIGH CURRENT DENSITY CONTINUOUSLY

PASSING THROUGH A METAL DUE TO THE HIGH CURRENT, THE ATOMS ARE
MOVING WITH KINETIC ENERGY AND THEY TRANSFER THE ENERGY TO ANOTHER
ATOMS DUE THESE DAMAGE THE METAL.

IMPROVE:INCREASE METAL WIDTH.

 1. FIRST SAVE THE DESIGN, BEFORE GOING TO POWER PLAN.
2. DEFINE LOGICAL P/G CONNECTIONS.
3. APPLY POWER NETWORK CONSTRAINTS.
4. POWER NETWORK CONSTRAINTS ARE
5. (i)NO.OF POWER STRAPS,(ii)POWER STRAPS WIDTH,(iii)NO.OF POWER
PADS, (iii)POWER RING WIDTH.
6. SYNTHESIZE THE POWER NETWORK,ANALYZE POWER NET WORK .
7. ANALYZE POWER NETWORK :(i) P/G NETPAIR (ii) POWER BUDGET OF
SYNTHESIZED NETS(iii)PNS CALCULATES THE REQUIRED NO.OF STRAPS
BASED ON PROVIDED CONSTRAINTS. (iv) IR DROP. (v) ELECTROMIGRATION.
8. ANALYZE IR DROP.
9. IF IR DROP IS MORE THEN MODIFY POWER NETWORK CONSTRAINTS ,AND
RESYNTHESIZE POWER NETWORK.
10. IF IR DROP IS NOT SATISFIED ADD P/G PADS.
11. COMMIT THE POWER NETWORK, HERE STRAPS AND RINGS ARE ROUTED
,SO WE CAN'T MODIFY THE DESIGN.
12. CONNECT THE MACRO P/G PINS AND PAD P/G PINS TO THE CORE RINGS.
13. CREATE POWER RAILS.ALONG THE STD CELL ROWS.
14. AND RE ANALYZE IR DROP.IF STRAPS ARE NOT SUFFICIENT THEN ADD.
15. APPLY P-NET OPTIONS . WHEN A POWER STRAPS IN METAL 7,POWER
STRAPS ARE CONNECTED TO THE POWER RAILS THROUGH VIA'S. SO IF
ANY PLACED INN THAT AREA THEN SHORTS OCCURRED .FOR AVOIDING
THESE PROBLEM WE ARE ADDING P-NET OPTIONS.
16. AFTER THIS INCREMENTAL PLACEMENT:IT MEANS EFFECTIVELY CELLS
MOVING

POWER PLANNING IS ALSO CALLED AS THE PRE ROUTES.

BECAUSE IN THE CHIP FIRST POWER NETS ROUTED FIRST.

POWER CALCULATIONS:
----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF
CHIP=(TOTAL CORE POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM
ALLOWABLE CURRENT FOR A I/O PAD)} .

----->CORE RING WIDTH:

CORE CURRENT(mA)=(CORE POWER)/(CORE VOLTAGE )

CORE P/G RING WIDTH =(TOTAL CORE CURRENT)/{(N0.OF.SIDES)*(MAXIMUM

CURRENT DENSITY OF THE METAL LAYER USED FOR PG RING)}

------->MAXIMUM CURRENT DENSITY Rj mA.

-------->SHEET RESISTANCE :Rs OHMS/SQUARE.

-------->TOTAL CURRENT =TOTAL POWER CONSUMPTION OF CHIP(P)/VOLTAGE(V).

-------->NO.OF POWER PADS(Npads)=Itotal/Ip

------->Itotal =TOTAL CURRENT

------->Ip OBTAINED FROM IO LIBRARY SPECIFICATION.

-------->NO.OF POWER PINS = Itotal/Ip

-------->MAXIMUM CURRENT SPECIFICATION OF EACH METAL LAYER FROM

LIBRARY(Rj).

---------->TOTAL METAL WIDTH REQUIRED ON LAYER1=LAYER2=

Wtotalstrap = Itotal/(2*Rj)

----------->ASSUMING SPACINGS BETWEEN STRAPS=Lspace

L<(Vmax)/(Rj*Rs)

Vmax = MAX ALLOWABLE IR DROP

Rj=MAX CURRENT DENSITY

Rs=SHEET RESISTANCE

---------->TOTAL CORE AREA= Wcore*Hcore

H=HEIGHT

W=WIDTH

----------->NUMBER OF VERTICAL STRAPS=Nv=Wcore/L

----------->NUMBER OF HORIZONTAL STRAPS=NH=Hcore/(2*L)

------------> MIN STRAP WIDTH REQUIRED=Wring/(Nv*Nh)

IR DROP:

------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA

-------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop

=IstrapAvg*Rs*(W/2)*(1/Wstrap)
--------->NUMBER OF STRAPS BETWEEN TWO POWER PADS

Nstrappinspace = Dpadspacing/Lspace.

---------->MIN RING WIDTH = Wring = Ip/Rj microm

POWER

-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER

=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]

=LEAKAGE POWER+[{SHORTCKT+INT POWER}]+EXT SWITCHING

POWER]

=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]

Isc=SHORT CIRCUIT POWER

C=LOAD CAP

S=SWITCHING ACTIVITY FACTOR.

PLACEMENT
IN PLACEMENT STEPS ARE
1. PLACEMENT CHECKS,
2. AHFNS
3. DFT SETUP.
4. POWER SETUP.
5. PLACEMENT OPTIMIZATION.

PLACEMENT :
AFTER GOING TO PLACEMENT WE HAVE TO CHECKS ,FIX

1. FIX MACRO PLACEMENT.(AGAIN)

2. VERIFY THE P-NET, IGNORED ROUTING LAYERS.
3. VERIFY KEEPOUT VARIABLE SETTINGS.
4. SPECIFY NON DEFAULT ROUTING RULES.
5. CHECK PLACEMENT READINESS.

-->FIX MACRO PLACEMENT AGAIN, BECAUSE AFTER INSERTING THE DESIGN IF

MACROS ARE MOVED THE CHECK.

-->P-NET, IGNORED ROUTING LAYERS ALSO.

-->MAINTAIN KEEPOUT VARIABLE SETTINGS FURTHER STEPS ALSO

-->NON DEFAULT RULES ARE SPECIAL RULES. LIKE DOUBLE SPACING, DOUBLE
WIDTHING. THESE ARE APPLIED FOR CLOCK WIRES. BECAUSE THOSE HIGH
ACTIVITY NETS.

-->BUT HERE WE ARE ONLY SPECIFYING NON DEFAULT ROUTING RULES[NDR'S].

--->SPECIFYING NDR'S BECAUSE AVOIDING CONGESTION AND TIMING PROBLEMS

AT THE STAGE OF CLOCK TREE SYNTHESIS

-->CHECK PLACEMENT READINESS IN WE ARE CHECK

1. FLOOR PLAN ,
2. NETLIST,
3. NARROW PLACEMENT REGIONS,
4. R,C FOR ROUTING LAYERS,
5. DESIGN CONSTRAINTS.

AHFNS (AUTOMATIC HIGH FANOUT NET SYNTHESIS):

 ● HFNS FOR RESET AND SCAN ENABLE AND ETC....
● HFNS ARE SYNTHESIZED IN FRONT END ALSO BUT AT THAT MOMENT NO
PLACEMENT INFO STAND CELLS IS AVAILABLE.
● HENCE BACKEND TOOL COLLAPSE SYNTHESIZED HNFS.
● IT RESYNTHESIS HFNS BASED ON PLACEMENT INFO AND APPROPRIATELY
"INSERT BUFFERS".
● TARGET OF THIS SYNTHESIS IS TO MET DELAY REQUIREMENTS i.e. SETUP
AND HOLD.

PLACEMENT OPTIMIZATION
PLACEMENT OPTIMIZATION:

PLACEMENT OPTIMIZATION WITH WE HAVE OPTIONS

(i)CONGESTION,

(ii)AREA RECOVERY ,

(iii)POWER,

(iv)DFT,

(v)TIMING.

BY USING THE CONGESTION OPTION WE CAN REDUCE THE CONGESTION.

BY USING THE POWER OPTION WE CAN REDUCE THE STATIC POWER

DISSIPATION,DYNAMIC POWER DISSIPATION.

BY USING THE AREA RECOVERY OPTION WE CAN REDUCE THE CELLS , POWER,
TIMING.
BY USING THE DFT OPTION WE CAN REDUCE THE ROUTING RESOURECES BY
REORDER THE SCAN CHAINS.

AND IF TIMING IS CRITICAL LOGICAL TIMING DRIVEN PLACEMENT.

AND CONGESTION IS CRITICAL CONGESTION DRIVEN PLACEMNT.

PLACEMENT (POWER SET UP)

POWER SETUP:

WE HAVE TWO TYPE OF THE POWER DISSIPATIONS:

1. STATIC POWER DISSIPATION

2. DYNAMIC POWER DISSIPATION

STATIC POWER DISSIPATION:

STATIC POWER DISSIPATION IS, IF THE CELLS ARE PRESENT AT THE "OFF" STATE
THEN DUE TO THE LEAKAGE OF CELLS STATIC POWER DISSIPATION OCCURRS.

THE LEAKAGE IS DUE TO THE JUNCTION LEAKAGE, TUNNELING , SUB

THRESHOLD LEAKAGE.

FOR REDUCING THE STATIC POWER DISSIPATION REPLACING THE LVT CELLS
WITH HVT CELLS.

HVT CELLS ARE SLOWER,AND LOW LEAKAGE ,HIGH Vt .

LVT CELLS ARE FASTER ,AND HIGH LEAKAGE,LOW Vt.

REPLACING THE LVT CELLS WITH HVT CELLS.

LVT CELLS ARE USED AT CRITICAL PATHS.

IN THE MOST OF THE ARCHITECTURES WE WILL USE THE POWER GATING FOR
REDUCING THE STATIC POWER DISSIPATION.

DYNAMIC POWER DISSIPATION:

DYNAMIC POWER DISSIPATION IS DUE TO THE SHORT CIRCUIT , INTERNAL
LOAD,HIGH SWITCHING.

FOR REDUCING THE DYNAMIC POWER DISSIPATION WE HAVE LOT OF

TECHNIQUES THOSE ARE :

REDUCING THE HIGH TOGGLE RATE NET NET LENGTHS. THESE TOGGLE RATE IS
GETTING FROM SWITCHING FILE(.SAIF ) THIS IS GETTING FROM SIMULATION
PEOPLE.

AND FOR AVOIDING THIS WHICH CELLS HAVING HIGH TOGGLE RATE NET LENTHS
CONNECTED NEARER TO CONNECTED CELLS.

ANOTHER TECHNIQUE IS ADDING THE BUFFER IN BETWEEN THE HIGH NET

LENGTH NETS. FOR REDUCING THE HIGH COUPLING CAPACITANCE.(REDUCE THE
LOAD CAPACITANCE)

ANOTHER TECHNIQUE IS CONNECT HIGH COUPLING CAPACITANCE NET TO THE

LOW CAPACITANCE PIN OF THE CELL.(SWAPPING THE PIN).

ANOTHER TECHNIQUE IS CLONING , IT IS CREATING THE SAME CELL AND

CONNECT THE SOME OF THE OUTPUT NET TO THESE.(SHARING THE LOAD)

AND ANOTHER TECHNIQUE IS CELL SIZING.

ANOTHER TECHNIQUE IS GATE LEVEL LOGIC OPTIMIZATION.

MOSTLY IN DESIGN WE WILL USE THE CLOCK GATING TO REDUCING THE

DYNAMIC POWER DISSIPATION

PLACEMENT (DFT SETUP)

DFT SETUP:

SCAN CHAINS: SCAN CHAINS ARE NOTHING BUT A GROUP OF REGISTERS

CONNECTED SERIALLY.

THESE ARE CONNECTED ARE ALPHA NUMERIC MANNER.

THERE ARE TWO TYPE OF MODES PRESENT:(i)FUNCTION MODE,(ii)TEST MODE.

THESE MODE SELECTED BY USING MUX DEVICES.

TEST MODE IS DONE AT AT DFT TIME.

DFT(DESIGN FOR TESTABILITY) IS ONE OF THE STEP IN ASIC FLOW.

HERE SCAN INPUT SI , SCAN OUT IS SO.

WE HAVE A PROBLEM WITH PREEXISTING SCAN CHAINS ,

THE ISSUE IS PRE EXISTING SCAN CHAINS ARE CONNECTED FAR AWAY ,
BECAUSE THEY ARE CONNECTED BASED ON THE FUNCTIONALITY BASED,

SO FOR CONNECTING THESE WE HAVE TO USE MORE ROUTING ROUTING

RESOURCES.

IT CAUSED FOR CONGESTION.

INSERT THE SCAN CHAINS FILE. IF PROBLEM WITH PREEXISTING SCAN CHAINS
THEN REORDER THE NAMES OF THE SCAN REGISTER NAMES.

IT ALSO REDUCES THE HOLD TIME.

SCAN CHAIN INFORMATION PRESENT IN .scandef FILE

IF THE GIVEN NETLIST IS .ddc FORMAT THEN THERE IS NO NEED OF LOADING

.scandef

IF THE GIVEN NETLIST IS .v FORMAT THEN WE HAVE TO LOAD THE .scandef FILE
CTS (CLOCK TREE SYNTHESIS)
CLOCK TREE SYNTHESIS :

----->CTS IS THE CONNECT THE CLOCKS TO THE ALL CLOCK PIN OF SEQUENTIAL
CIRCUITS.

------->ALL CLOCK PINS ARE DRIVEN BY A SINGLE CLOCK SOURCE.

------->CTS TARGETS : (i)skew ,

(ii)insertion delay

-------->CTS GOALS :(i)max transition,

(ii)max capacitance,

(iii)max fanout,

(iv)max buffer levels.

------->A BUFFER TREES IS BUILT TO BALANCE THE LOADS AND MINIMIZE THE
SKEW.

-------->A CLOCK TREE WITH BUFFER LEVELS BETWEEN THE CLOCK SOURCE AND
CLOCK SINKS(END POINTS).

-------->CTS STARTING POINT IS CLOCK SOURCE (SDC DEFINED CREATE_CLOCK)

-------->CTS ENDPOINTS ARE CLOCK PINS OF SEQUENTIAL CELLS.

-------->CLOCK PINS ARE ALSO CALLED AS THE CLOCK SINKS.

-------->WHEN THE CLOCK ROOT IS PRIMARY PORT OF BLOCK.

-------->AT CHIP LEVEL PRIMARY PORTS ARE PADS.

-------->CLOCK PINS ARE DIFFERENT TYPES ,THOSE ARE (i) STOP PINS,

(ii)FLOAT PINS,

(iii)EXCLUDE PINS.

(iv)NON STOP PINS

-------->STOP PINS:CTS OPTIMIZES FOR CLOCK TREE TARGETS,CLOCK TREE

GOALS.

-------->FLOAT PIN:LIKE AS STOP PINS,BUT DELAYS ON CLOCK PIN,MACRO

INTERNAL DELAY.

--------->EXCLUDE PIN:CTS IGNORES TARGETS,FIX CLOCK TREE DRC'S.

--------->NON-STOP PINS: NONSTOP PINS ARE PINS THROUGH WHICH CLOCK TREE
TRACING THE CONTINUOUS AGAINST THE DEFAULT BEHAVIOUR .

CLOCKS WHICH ARE TRAVERSED THROUGH DIVIDER CLOCK SEQUENTIAL

ELEMENTS CLOCK PINS ARE CONSIDERED AS NON-STOP PINS.
CTS (APPLYING NDRS ON CLOCK
NETS)
NDR'S:

NDR' S ARE NOTHING BUT NON DEFAULT ROUTING .

THESE ARE APPLIED ON THE CLOCK NETS .

CLOCK NETS ARE LESS SENSITIVE TO CROSSTALK AND ELECTROMIGRATION.

CLOCK NETS ARE HIGH SWITCHING ACTIVITY NETS.

NDR RULES ARE (i) DOUBLE WIDTH,

(ii) DOUBLE SPACING.

(iii) SHIELDING

BY APPLYING DOUBLE WIDTH WE CAN AVOID THE ELECTROMIGRATION EFFECT.

BY APPLYING DOUBLE SPACING WE CAN AVOID CROSS TALK EFFECT.

BY DEFAULT, NON DEFAULT ROUTING RULE APPLIES ON ALL LEVELS CLOCK

TREE. BUT USING NDR RULES AT THE CLOCK SINK PINPOINTS IS BETTER TO
AVOID.

HELPS TO AVOID CONGESTION AT LOWER METAL LAYERS

IMPROVES PIN ACCESSIBILITY OF STD CELLS

----------->ALWAYS ROUTE CLOCK ON METAL 3 AND ABOVE

----------->AVOID NDR ON CLOCK SINKS

----------->AVOID NDR ON METAL 1.

---- -MAY HAVE TROUBLE ACCESSING METAL 1 PINS ON BUFFERS AND

GATES

-----CONSIDER DOUBLE WIDTH TO REDUCE RESISTANCE.

CTS OPTIMIZATION
OPTIMIZATIONS TECHNIQUES:

BUFFERING ----------------->IT WILL IMPROVE SETUP TIME

GATE SIZING---------------->BY DECREASING GATE SIZE DELAY MAY

DECREASE(UPSIZE)

DELAY INSERTION------->IT WILL IMPROVE HOLD TIME

BUFFER RELOCATION--->REDUCE SKEW & INSERTION DELAY

FIX MAX TRANSITION---->ADD BUFFERS

FIX MAX CAPACITANCE--->DECREASE NET LENGTH, CLONING.

OPTIMIZATION PROCESS:

● REDUCE DISTURBANCES TO OTHER CELLS AS MUCH AS POSSIBLE.

● PERFORM LOGICAL AND PLACEMENT OPTIMIZATIONS TO ALL FIX
POSSIBLE TIMING
● FIX MAX TRANS/CAP VIOLATIONS AND SKEW, BASED ON PROPAGATED
CLOCK ARRIVALS

ROUTING

ROUTING:

---->CREATE PHYSICAL CONNECTIONS TO ALL DATA SIGNAL PINS,CLOCK PINS

THROUGH METAL INTERCONNECTIONS.

---->PATHS MUST MET TIMINGS.

IN THE ROUTING MAINLY THREE STAGES ARE PRESENT:

(i)GLOBAL ROUTING

(ii)TRACK ASSIGNMENT

(iii)DETAIL ROUTING

EXTRA ONE

(iv)SEARCH AND REPAIR

ROUTING (GLOBAL ROUTING)

GLOBAL ROUTING:

--->FIRST THE DESIGN IS DIVIDED INTO SMALL BOXES EVERY BOX IS CALLED
GLOBAL ROUTING CELLS (GCELLS OR BUCKETS)

----->EVERY GCELL HAVING THE A NUMBER OF HORIZONTAL ROUTING

RESOURCES AND VERTICAL ROUTING RESOURCES.

----->GLOBAL ROUTING ASSIGNS NETS(LOGICAL CONNECTIVITY NOT METAL

CONNECTIVITY) TO SPECIFIC METAL LAYERS AND GLOBAL ROUTING CELLS.

------>BY USING GLOBAL ROUTING WE CAN ANALYZE CONGESTION.

------->CONGESTION =(REQUIRED ROUTING RESOURCES > AVAILABLE ROUTING

RESOURCES)

------->IF ANY GCELL HAVE CONGESTION THEN DETOURING(AVOID THE GCELL

ROUTING THROUGH ANOTHER GCELL).
ROUTING (TRACK ASSIGNMENT)

TRACK ASSIGNMENTS :
---->ASSIGNS EACH NET TO THE SPECIFIC TRACKS.

---->NETS ARE LAY DOWN THE METAL TRACES.

----->TRACES=METAL CONNECTIVITY..

ROUTING (DETAIL ROUTING)

DETAIL ROUTING:
---->DETAIL ROUTE DONES ACTUAL ROUTING.

----->MEANS ACTUAL ROUTING METAL CONNECTIONS.

----->CHECK ALSO PHYSICAL DRC'S.

----->DETAIL ROUTING DOES NOT WORK ON THE ENTIRE CHIP AT THE SAME TIME
LIKE TRACK ASSIGNMENT.

------>INSTEAD IT WORKS BE REROUTING WITHIN THE CONFINES OF A SMALL

AREA CALLED AN "SBOX".

SBOX : DIVIDE THE BLOCK INTO MINI BOXES THESE ARE USED FOR THE DETAIL
ROUTE.

ROUTING (SEARCH AND REPAIR)

SEARCH AND REPAIR :

---->SEARCH AND REPAIR FIXES REMAINING DRC VIOLATIONS THROUGH MULTIPLE

LOOPS USING PROGRESSIVELY LARGE SBOX.
ROUTING (SEARCH AND REPAIR)

SEARCH AND REPAIR :

---->SEARCH AND REPAIR FIXES REMAINING DRC VIOLATIONS THROUGH MULTIPLE

LOOPS USING PROGRESSIVELY LARGE SBOX.

ECO (ENGINEERING CHANGE ORDER)

ECO:

ECO'S ARE TWO TYPE :1)TIMING ECO'S(TO IMPROVE TIMING)

2)FUNCTIONAL ECO'S(TO ADD FUNCTIONALITY)

TIMING ECO FUNCTIONAL ECO

| |

----------------------------- ---------------------------

| | | |

FREEZE NON-FREEZE FREEZE NON-FREEZE

--------->IT IS THE LATE CHANGE IN THE FLOW.

---------->AFTER ROUTING IF WE WANT ANY CHANGES OR ADDING NEW CELLS ,

THESE ALL ARE DONE AT THE ECO STAGE.

HERE TWO TYPE OF ECO'S PRESENT :

(i)FREEZE SILICON ECO

(ii)NON FREEZE SILICON ECO

--------->IN FREEZE SILICON ECO WE HAVE NO CHANCE OF ADDING CELL, HERE

SPARE CELLS ARE USED FOR THESE.

DIFFERENT TYPE OF CELLS

DIFFERENT TYPE OF CELLS:

● STDCELLS:
■ Nothing But Base cells(Gates,flops).

● TAP CELLS:
■ Avoids Latch up Problem(Placing these cells with a particular
distance).
■ Cells are physical-only cells that have power and ground pins
and dont have signal pins.
■ Tap cells are well-tied cells that bias the silicon infrastructure of
n-wells or p-wells.
■ They are traditionally used so that Vdd or Gnd are connected to
substrate or n-well respectively.
■ This is to Help TIE Vdd and Gnd which results in lesser drift and
prevention from latchup.
■ Required by some technology libraries to limit resistance
between Power or Ground connections to well of the substrate.

● TIE CELLS :
■ It is used for preventing Damage of cells; Tie High cell(Gate One
input is connected to Vdd, another input is connected to signal
 net);Tie low cells Gate one input is connected to Vss, another
input is connected to signal .
■ Tie - high and Tie - low cells are used to connect the gate of the
transistor to either Power and Ground.
■ In lower technology nodes, if the gate is connected to Power or
Ground. The transistor might be turned "ON/OFF" due to Power
or Ground Bounce.
■ These cells are part of the std cell library.
■ The cells which require Vdd(Typically constant signals tied to 1)
conncet to tie high cells.
■ The cells which require Vss/Vdd (Typically constant signals tied
to 0) connect to tie low cells.

● END CAP CELLS:

■ To Know the end of the row,and At the edges endcap cells are
placed to avoid the cells damages at the end of the row to avoid
wrong laser wavelength for correct manufacturing.
■ You can add Endcap cells at both Ends of a cell row.
■ Endcap cells surrounding the core area features which serve as
second poly to cells
■ placed at the edge of row.
■ The library cells do not have cell connectivity as they are only
connected to Power and Ground rail,
■ Thus ensure that gaps do not occure between "WELL" and
"IMPLANT LAYER" and to prevent the DRC violations by
satisfying "WELL TIE - OFF" requirements for core rows we use
End cap cells.
■ Usually adding the "Well Extension" for DRC correct designs.
■ End caps are a "POLY EXTENSION" to avoid drain source SHORT

● DECAP CELLS:
■ Charge Sharing;To avoid the Dynamic IR drop ,charge stores in
the cells and release the charge to Nets.
■ Decoupling capacitor cells , or Decap cells, are cells that have a
capacitor placed.
■ Between the Power rail and Ground rail to Over come Dynamic
voltage drop.
■ Dynamic IR Drop happens at the active edge of the clock at
which a High currents is drawn from the Power Grid for a small
Duration.
■ If the Power is far from a flop the chances are there that flop can
go into Metastable State.
■ To overcome decaps are added , when current requirements is
High this Decaps discharges and provide boost to the power
grid.
● FILLER CELLS:
■ Filler cells are used to connect the gaps between the cells after
placement.
■ Filler cells are ussed to establish thecontinuity of the N-Wells and
the IMPLANT LAYERS on the standard cells rows, some of the
cells also don't have the Bulk Connection (Substrate connection)
Because of their small size (thin cells).
■ In those cases, the abutment of cells through inserting filler cells
can connect those substrates of small cells to the Power/Ground
nets.
■ i.e. those tin cells can use the Bulk connection of the other
cells(this is one of the reason why you get stand alone LVS check
failed on some cells)

● ICG CELLS:
■ Clock gating cells ,to avoid Dynamic power Dissipation.
■ Register banks disabled during some clock cycles.
■ During idle modes, the clocks can be gated-offs to save Dynamic
power dissipation on flipflops.
■ Proper circuit is essential to achive a gated clock state to prevent
false glithes on the clock paths

● POWER GATING CELLS:

■ In Power gating to avoid static power Dissipation.
○ Power Gating Cells:
■ Power switches
■ Level Shifters
■ Retention registers
■ Isolation cells
■ Power controler

● PAD CELLS:
■ To Interface with outside Devices;Input to of Power,Clock,Pins
are connected to pad cells and outside also.

● CORNER CELLS:
■ Corner Pads are used for Well Continity.
■ To lift the chip.

● MACRO CELLS:
■ Memories.
■ The memory cells are called Macros.
 ■ To store information using sequntial elements takes up lot of
area.
■ A single flipflop could take up 15 to 20 transistors to store one bit
store the data efficiently and also do not occupy much space on
the chip comparatively by using macros.

● SPARE CELLS:
■ Used at the ECO.
■ Spare cells are standard cells in a design that are not used by
the netlist.
■ Placing the spare cells in your design provides a margin for
correcting logical error that might be detected later in the design
flow, or for adjusting the speed of your design.
■ Spare cells are used by the fix ECO command during ECO
process.

● PAD FILLER CELLS:

■ Used for Well Continity, Placed in between Pads.

● JTAG CELLS:
■ These are used to check the IO connectivity.

FIXING DRC'S
DRC'S FIXING

DRC'S ARE DIFFERENT TYPES :

1. LOGICAL DRC'S.
2. PHYSICAL DRC'S.

LOGICAL DRC'S:

1. MAX TRANSITION
2. MAX CAPACITANCE
3. MAX FANOUT
MAX TRANSITION:

FIXING TECHNIQUES:

● ADD A BUFFER IN MIDDLE OF THE LONG LENGTH WIRE.

● REDUCE THE WIRE LENGTH.
● ADDING A CHAIN OF BUFFERS.

MAX CAPACITANCE:

FIXING TECHNIQUES:

● DECREASE WIRE LENGTH AT OUTPUT SIDE.

MAX FANOUT:

FIXING TECHNIQUES:

● CLONNING=ADDING A SAME CELL LOAD WILL BE DIVIDED.

● SHARING THE LOAD

PHYSICAL DRC'S:
1. WIRE TO WIRE SPACING(MIN SPACING)
2. MIN WIDTH OF WIRES
3. VIA TO VIA SPACINGS
4. NOTCH AVOIDING

FIXING TECHNIQUES:

● SEARCH AND REPAIR

FIXING CROSSTALK
CROSS TALK:

THE VOLTAGE TRANSFER FROM HIGHLY SWITCHING NET(AGGRESSOR NET) TO

ANOTHER NET (LOW SWITCHING (OR) HIGH SWITCHING (OR) VICTIM NET (OR)
CONSTANT NET ) THROUGH COUPLING CAPACITANCE THESE MAY CAUSE CROSS
TALK .
REDUCING TECHNIQUES:

● VICTIM NET WIDTH INCREASING THEN RESISTANCE DECREASE IT IS USED

AT ROUTING ALSO.
● SPACING BETWEEN AGGRESSOR NET AND VICTIM NET INCREASE.
● BUFFERING ON CONSTANT NETS (OR) VICTIM NETS.
● PLACING AN GROUND NETS ON BETWEEN THE AGGRESSOR NET AND
VICTIM NET THEN VOLTAGE DISCHARGE ON GROUND NET THEN NO SIGNAL
INTEGRITY PROBLEM.THIS IS CALLED SHIELDING .
● MAINTAIN STABLE SUPPLY.
● FAST SLEW RATE.
● JOGING(INCRAESE HALF TRACK BY HALF ITCH).
● LAYER JUMPING(JUMP ONE LAYER ABOVE LAYER AND COMES TO SAME
LAYER)
● INCREASE DRIVE STRENTH OF CELL
● CELL SIZING(UP SIZING)
● DEEP N-WELL.
● GUARD RING.

CALCULATIONS:
POWER CALCULATIONS:

----->NUMBER OF THE CORE POWER PAD REQUIRED FOR EACH SIDE OF

CHIP=(TOTAL CORE POWER)/{(NUMBER OF SIDE)*(CORE VOLTAGE)*MAXIMUM
ALLOWABLE CURRENT FOR A I/O PAD)} .

----->CORE RING WIDTH:

CORE CURRENT(mA)=(CORE POWER)/(CORE VOLTAGE )

CORE P/G RING WIDTH =(TOTAL CORE CURRENT)/{(N0.OF.SIDES)*(MAXIMUM

CURRENT DENSITY OF THE METAL LAYER USED FOR PG RING)}

------->MAXIMUM CURRENT DENSITY Rj mA.

-------->SHEET RESISTANCE :Rs OHMS/SQUARE.

-------->TOTAL CURRENT =TOTAL POWER CONSUMPTION OF CHIP(P)/VOLTAGE(V).

-------->NO.OF POWER PADS(Npads)=Itotal/Ip

------->Itotal =TOTAL CURRENT

------->Ip OBTAINED FROM IO LIBRARY SPACIFICATION.

-------->NO.OF POWER PINS = Itotal/Ip

-------->MAXIMUM CURRENT SPACIFICATION OF EACH METAL LAYER FROM

LIBRARY(Rj).

---------->TOTAL METAL WIDTH REQUIRED ON LAYER1=LAYER2=

Wtotalstrap = Itotal/(2*Rj)

----------->ASSUMING SPACINGS BETWEEN STRAPS=Lspace

L<(Vmax)/(Rj*Rs)

Vmax = MAX ALLOWABLE IR DROP

Rj=MAX CURRENT DENSITY

Rs=SHEET RESISTANCE
---------->TOTAL CORE AREA=Wcore*Hcore

H=HEIGHT

W=WIDTH

----------->NUMBER OF VERTICAL STRAPS=Nv=Wcore/L

----------->NUMBER OF HORIZONTAL STRAPS=NH=Hcore/(2*L)

------------> MIN STRAP WIDTH REQUIRED=Wring/(Nv*Nh)

IR DROP:

------>AVG CURRENT THROUGH EACH STRAP=IstrapAvg=(Itotal)/(2*Nstraps)mA

-------->APPROPRIATE IR DROP AT THE CENTER OF THE STRAP=Vdrop or IRdrop

=IstrapAvg*Rs*(W/2)*(1/Wstrap)

--------->NUMBER OF STRAPS BETWEEN TWO POWER PADS

Nstrappinspace = Dpadspacing/Lspace.

---------->MIN RING WIDTH = Wring = Ip/Rj microm

POWER

-------->TOTAL POWER=STATIC POWER+DYNAMIC POWER

=LEAKAGE POWER+[INTERNAL POWER+EXT SWITCHING POWER]

 =LEAKAGE POWER+[{SHORT CIRCUIT POWER + POWER+INT
POWER}]+EXT SWITCHING POWER]

=LEAKAGE POWER+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]

Isc=SHORT CIRCUIT POWER

C=LOAD CAP

S=SWITCHING ACTIVITY FACTOR.

-----CORE RING WIDTH:

CORE CURRENT=(CORE POWER)/(CORE VOLTAGE).

CORE P/G RING WIDTH=(TOTAL CURRENT)/(NO OF SIDES *MAXIMUM CURRENT

DENSITY OF THE METAL LAYER USED FOR P/G PAD RING)

VERIFICATION'S
PHYSICAL VERIFICATION:
IN PHYSICAL VERIFICATION IT CHECKS:

1. LVS(LAYOUT VERSUS SCHEMATIC)

2. DRC(DESIGN RULE CONSTRAINTS CHECK)
3. ERC(ELECTRICAL RULE CHECK)

LAYOUT VERSUS SCHEMATIC(LVS):

INPUTS ARE (.LVS.V) AND (.GDSII) FILES AND RULE DECK FILES.
COMPARISION TWO ELECTRICAL CIRCUITS EQUIVALENT WITH RESPECT TO THEIR
"CONNECTIVITY" AND "TOTAL TRANSISTOR COUNT".

COMPARISION BETWEEN (.GDSII) FILE AND EXTRCTED NETLIST (.LVS.V) FILE.

FINALLY BOTH ARE CONVERTED INTO A SPICE LEVEL .

LVS CHECKS ARE:

EXTRACT ERRORS :

● SHORTS
● OPENS
● FLOATING NETS.

COMPARE ERRORS:

● PIN ERRORS
● PARAMETRIC ERRORS
● DEVICE MISMATCH
● NET MISMATCH
● MALFORMED DEVICES
● PORTS MISMATCH

DESIGN RULE CONSTARINTS CHECK(DRC):

INPUT IS .GDSII FILE AND RULE DECK FILE.

CHECKS:

● ACTIVE TO ACTIVE SPACINGS.

● WELL TO WELL SPACINGS.
● MINIMUM CHANNEL LENGTH OF THE TRANSISTOR.
● MINIMMUM METAL WIDTH.
● METAL TO METAL SPACINGS.
 ● ESD(ELECTRO STATIC DISCHARGE).
● I/O RULES.
● METAL FILL DENSITY.

ELECTRICAL RULE CHECK(ERC):

INPUT IS (.GDSII) FILE .

INVOLVES CHECKING A DESIGN FOR ALL ELECTRICAL CONNECTIONS.

CHECKS ARE:

● WELL AND SUBSTRATE AREAS FOR PROPER CONTACTS AND SPCINGS

THERE BY ENSURING CORRECT POWER CONTACTS AND GROUND
CONNECTIONS.
● TO LOCATE FLOATING DEVICES AND FLOATING WELLS.
● TO LOCATE DEVICE WICH ARE SHORTED.
● TO LOCATE DEVICES WITH MISSING CONNECTIONS.
● GATE CONNECTRD DIRECTLY TO SUPPLIES.
● FLOATING INPUTS.

FORMAL VERIFICATIONS:

IN FORMAL VERIFICATION CHECKS ARE LEC(LOGICAL EQUIVALENCE CHECK).

CHECKING BETWEEN FINALLY EXTRCCTED NETLIST(.V) AND SYNTHESIZED

NETLIST(.V).

INPUTS ARE EXTRCCTED NETLIST(.V) AND SYNTHESIZED NETLIST(.V).

HERE CHECKING FOR FUNCTIONALITY CORRECTNESS.

SCENARIO'S
SCENARIO
SCENARIO = MODE + CORNER.

MODE: MODE IS DEFINED AS A SET OF CLOCKS , SUPPLY VOLTAGES ,TIMING

CONSTRAINTS AND LIBRARIES.

MODES TYPE:

1. FUNCTIONAL MODE.
2. TEST MODE.

IT CONTAINS SDC CONSTRAINTS.

IN DESIGN DIFFERENT FUNCTIONALITY MODES CONTAINS DIFFERENT SDC'S.
IN DESIGN DIFFERENT FUNCTIONALITY MODES ARE PRESENT.

CONSTRAINTS IN TEST MODE WHILE THE CHIP IS A DEVICES UNDER TEST:

● TESTER CLOCK PERIOD AND CLOCK SOURCES.

● MODEL TESTER SKEW ON THE INPUT PORTS.
● DIFFERENT TIMING EXCEPTIONS.
● DIFFERENT SETUP/HOLD ON THE OUTPUT PORTS.
● THE SCAN CHAIN IS EXCERSIED IN TEST MODE.(NOT IN FUNCTIONAL
MODE).

CORNERS:

CORNERS CONTAINS PVT'S.

_____________ BEST CASE CORNER

|
PVT -------------

|
______________WORST CASE CORNER.

FOR SETUP :

Arrival Path-------- |
|--------------------->Max Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

FOR HOLD :

Arrival Path-------- |
|--------------------->Min Dealys
Data path------------|

Reqired Path------------------------------->Min Delays

BEST CASE : --------->FASTEST<-------->MIN DELAYS<------->Early<-----------> FOR HOLD

● MIN DELAYS IN ARRIVAL PATH,DATA PATH .

● MAX DELAYS IN CLOCK PATH.

PVT: PROCESS---------------------->FAST
VOLTAGE--------------------->HIGH
TEMPERATURE------------>LOW

WORST CASE: --------->SLOWEST<-------->MAX DELAYS<------------> FOR SETUP

● MAX DELAYS IN ARRIVAL PATH, DATA PATH.

● MIN DELAYS IN CLOCK PATH.

PVT: PROCESS-------------------->SLOW
VOLTAGE-------------------->LOW
TEMPERATURE----------->HIGH

FINAL VERIFICATION GDS FILE EXPORT

FINAL VERIFICATION:
1. PARASITICS EXTRACTION:IT EXTRACT R,C VALUES FOR GETTING ORIGINAL
DELAYS. TOOL:STAR RC XT LICENCE
2. TIMING VERIFICATION:IT IS FIND BY USING PRIME TIME TOOL.
3. LVS ,ERC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES
TOOLS.
4. DRC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.

AFTER VERIFICATION:
1. AFTER THIS WE RELEASE THE GDS FILE
 2. IN THIS WE HAVE ALL POLYGONS INFORMATION IS PRESENT.

AFTER GDS

AFTER THIS WE ARE FINALLY BASE TAPE OUT(BTO).

AFTER BASE TAPE OUT WE WILL DO METAL TAPE OUT(MTO).