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Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator

Conference Paper · September 2009

DOI: 10.1109/DSD.2009.228 · Source: IEEE Xplore

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Architecture and DSP Implementation of a DVB-S2
Baseband Demodulator
P. Savvopoulos, N. Papandreou† and Th. Antonakopoulos
Department of Electrical and Computer Engineering
University of Patras, Rio-Patras, 26500, Greece
Email: [email protected], [email protected], [email protected]

Abstract—This paper presents the design and implementation processor is realized by the development of efficient fixed-
of a baseband demodulator for DVB-S2 satellite receivers. In point implementations of the various demodulation algorithms
order to meet the requirements of different complex and multi- that exploit the parallel-instruction execution capabilities of the
domain signal processing stages of the DVB-S2 baseband signal-
flow, the presented architecture is based on efficient fixed-point target CPU. Efficient time-scheduling of the various software
implementation of the various demodulation algorithms and on tasks enables the dynamic intercommunication of the different
the use of a dynamic time-sharing scheduler for the various signal processing stages that are executed sequentially or in
DSP software tasks. The prototyping of the demodulator and its parallel, thus enabling real-time execution.
verification in the design of a complete digital DVB-S2 satellite The rest of this paper is organized as follows. Section II
receiver using a versatile testbed is also presented.
presents the functional requirements of the DVB-S2 demodu-
I. I NTRODUCTION lator and describes the circuits at the various baseband signal
DVB-S2 comprises the newest European standard for broad- processing stages. Section III describes the architecture of
band satellite communications that exploits new achievements the demodulator, discusses the implementation details of the
in the fields of modulation and coding [1], [2]. DVB-S2 various algorithms in DSP software threads and presents their
meets the high performance requirements of todays satellite time-scheduling according to the different operational modes.
broadcasting and interactive communications, in terms of Finally, Section IV describes the prototyping and verification
capacity and power efficiency, while keeping the complexity of the presented demodulator using a versatile testbed that
of the terminal receiver at acceptable levels. Both functional utilizes powerful commercial equipment along with custom
characteristics are based on the versatility of the DVB-S2 devices.
physical layer with frame-by-frame adaptability according to II. DVB-S2 D EMODULATOR C IRCUITS
the channel conditions [3].
In order to support high data-rate applications, like multi- The block diagram of a DVB-S2 terminal is presented in
media applications and point-to-point backbone connectivity, Fig. 1. It consists of the following main components: the
the DVB-S2 standard supports high-order M-ary modulation outdoor unit (ODU), the analog-front end (AFE) and the
formats, such as 16APSK and 32APSK, which provide high digital receiver. The ODU consists of a parabolic dish antenna
spectral efficiency and robustness under non-linear distor- and the Low Noise Block (LNB) that converts the received
tion introduced by the high-power amplifier (HPA) onboard RF signal into the respective L-Band (950-2150 MHz). The
the satellite [4]. In addition, since powerful channel coding signal is further down-converted to the IF-Band (70 MHz)
(LDPC/BCH) is adopted [1], the receiver is able to recover by a programmable analog tuner that includes output power
the transmitted data under low signal-to-noise ratio (SNR) control and fixed bandpass filtering. The incoming IF signal
conditions. Therefore, the application of efficient synchroniza- is digitized by a high-speed analog-to-digital converter (ADC)
tion techniques are imperative in order to achieve the high and then a second digital down-converter (DDC) provides the
performance of the DVB-S2 standard. baseband complex I/Q signal to the digital signal processing
In this paper, we present the architecture and implementa- receiver. Adjustment of the incoming IF signal to the dynamic
tion of a digital baseband demodulator for DVB-S2 satellite range of the used ADC is achieved by an automatic gain
receivers. The demodulator’s architecture is based on a pow- controller (AGC) that is driven by a power measurement circuit
erful DSP processor with on-chip memory and external high- implemented in the DDC.
speed data ports, thus providing a stand-alone solution. The The digital DVB-S2 receiver consists of the baseband de-
demodulator implements the full signal-processing chain at the modulator, the forward error correction (FEC) decoder, the
physical layer including: symbol timing recovery, frame syn- MPEG or IP data stream framer and the network interface. The
chronization, carrier frequency and phase recovery, automatic demodulator implements the full baseband signal-processing
gain control and constellation decoding. The integration of chain including: symbol timing recovery, frame synchroniza-
the different multi-domain signal processing stages in a single tion, carrier frequency and phase error recovery, automatic
gain control and M-ary constellation decoding. In particular,
† N. Papandreou is currently with IBM Zurich Research Laboratory QPSK, 8PSK, 16APSK and 32APSK modulation formats are
 External Equipment Analog Front End Digital Signal Processing
RF L-band IF (70MHz)

BB Telco/
IF FEC MPEG/IP
LNB Tuner ADC Signal De- Network
DDC LDPC/BCH Framer
modulator Output

Baseband DVB-S2 Signal Demodulator

PL
Framer

Symbol Matched Fine

PL Constellation
Timing Filter/ Phase
Descrambler Recovery Demapper
Recovery Downsample

Fine Carrier Est. Coarse

DEMUX

DEMUX

DEMUX
Complex Baseband Signal (I/Q)
Digital
Phase
Control Signal Coarse Carrier Est. AGC
Est.
Binary Data Frame

Fig. 1. DVB-S2 receiver block diagram and detailed baseband demodulator signal processing stages.

DIFFERENTIAL PLSC SOF

supported. FEC decoding is carried out by the concatenation of
an LDPC inner decoder and a BCH outer decoder [1]. A block r (k ) 90
u (k ) 89 88 87 86 27 26 25 24 1

D D D D D D D D D D
de-interleaver is also preceded when high-order modulation
formats, such as 8PSK, 16APSK and 32APSK, are used. DVB- conj
T57 T56 T26 T25 T24 T1

S2 supports two major transport modes: the MPEG transport

stream and the DVB-S2 generic stream. + +

This work is focused on the design and implementation of S2(k)

+ +
S1(k)

+ -
the digital demodulator. Fig. 1 also shows the various signal
processing stages of the demodulator. Detailed description of ⋅ ⋅

the demodulator circuits follows. max

to peak detector
p(k )
A. Symbol Timing Recovery
Fig. 2. Differential PL header detection.
The first stage of the demodulator is the symbol timing
recovery (STR). The functionality of this module is to track the
symbol rate fluctuations introduced during signal transmission.
STR is implemented as a second order feedback loop utilizing feedback loop under non-linearities, AWG noise and residual
a Farrow structured cubic interpolator along with the non-data- carrier frequency offset is studied in [6].
aided (NDA) timing error detector (TED) proposed by Gardner
[5], which provides the loop with the required error signal. B. Frame Synchronization
Gardner TED is capable of operating under random symbols After the STR has reached steady state, the next function
and unknown carrier frequency offset error without precise to be performed is frame synchronization. This is done by
carrier synchronization. searching the physical layer (PL) header using an appropriate
At the output of the STR interpolator, the synchronized correlator that operates on a symbol-by-symbol basis. Using
samples stream is matched filtered and finally downsampled differential detection, accurate frame synchronization is possi-
leading to a rate of one sample per symbol that feeds the rest of ble even in the presence of strong carrier frequency errors [7].
the signal processing chain. Fig. 3 shows the closed-loop STR Fig. 2 shows the shift-register structure used for the detection
using the NDA Gardner TED. The performance of the STR of the DVB-S2 frame boundaries. Each frame starts with the
 Fs=1/Ts FMF=M/T FSTR=1/T

rf(mTs) y(kT/M+εΤ/Μ) z(kT/M+εΤ/Μ) z(iT+εΤ)

I’ Farrow I
From Matched
1/Ts Struct. 1/Ti=M/Τ M/Τ 1/Τ To
DDC Q’ Filter Q
Interpolator Frame/
Carrier
Synch
μ(1/Ts) Gardner
M/Τ
TED

T-NCO
(Period: T/M)

e(mnM)
1/Τs 1/Τ Loop
Filter

Fig. 3. Closed-Loop STR using the NDA Gardner TED.

FS/2 4R’S 2R’S RS

Programmable Freq.
From
DDC Subunit
(·)* 1 2 + j1 2 Following
Fixed Freq. Pilot Synchronizatrion
DDC Subunit 1. Symbol Timing Recovery Subunit
Sample Symbols
2. Matched Filtering
Rate
3. Frame Synchronization
Conversion z(k) y(k)
4. PL Descrambler

exp(-jθo[n])
z-D
Delay &
Multiply
cos/
Loop Filter FED
sin
(·)*
z-1 + ΚInt
εο[n]
x
Accumulator

NCO 1/(1-z-1) + ΚProp Im(·)

FS: ADC Sampling Frequency

R’S, RS: Nominal, Final Symbol Rate

Fig. 4. Coarse carrier frequency recovery.

PL header that consists of two parts, the Start of Frame (SOF) frame in order to drive the various pilot-aided carrier and phase
and the Physical Layer Signalling code (PLSC). SOF is a synchronization circuits.
known 26-symbol pattern, while PLSC is a 64-bit linear binary
code [1]. The shift register in Fig 2 is partitioned into two C. Carrier Frequency Recovery
sections. The first is associated with the SOF, the second with Carrier frequency recovery (CFR) is invoked directly after
the PLSC. The output of the correlator drives a peak detector the frame synchronization unit has detected the start of the
and has its maximum value when the whole PL header appears transmitted frames and thus the locations of the respective
in the shift register. pilot fields. CFR is performed in two sequential steps, which
A finite-state machine (FSM) controls the frame synchro- both use the known pilot symbols that are regularly repeated
nization unit during acquisition and normal operation. After in the form of fields during the payload transmission of the
frame synchronization has locked, the data symbols (I/Q) of DVB-S2 frames.
each frame are descrambled using a special Gold sequence The first step of carrier synchronization consists of a coarse
in the complex domain [1]. The scrambling process at the carrier recovery mechanism, which compensates large fre-
transmitter provides symbol randomization and is used for quency offset errors up to several MHz and is implemented as
energy dispersal. In our implementation, the descrambling a second order feedback loop based on a delay-and-multiply
sequence is precalculated and stored locally in the DSP (DM) frequency error detector [8]–[10]. The compensation of
memory. Based on the correct framing alignment, it is possible this loop is applied through the numerical control oscillator
to demultiplex (DEMUX) the pilot symbols from the incoming (NCO) embedded inside the DDC logic. Fig. 4 shows the
 To
Decoder
To Phase
Frame Recovery From
Sync AGC
q(k)
Mixer (·)Q

zn yμ ν̂ Accumulate Accumulator/
DEMUX Over L Look-Up Table e-jφˆ ejβ
pilot fields (SIN-COS) e-j2πˆνkT sign(Re{·})
From -jsign(Im{·})
Descrambler c*μ

Complex Conjugate
Accumulator/ eφ(k)
of the Pilot Symbols Look-Up Table Loop Filter Im{·}
(SIN-COS)

Fig. 5. Fine carrier frequency recovery. Fig. 7. Fine phase recovery.

Frame
Synch Frame
Sync sk
Mixer
ML
From Fine HDR 1
Phase
Carrier θnew
Estimator zk
DEMUX

-
Recovery To Fine
Control Phase θint Look-Up Table + Phase
Unit Interpolation (SIN-COS) + γ AGC
θold DEMUX Magnitude Recovery
ML 1- z
PLT
Phase From
Estimator Carrier Phase cp*k
To Recovery
AGC
Complex Conjugate
Delay
of the Pilot Symbols
Data

Fig. 6. Coarse phase recovery. Fig. 8. Digital automatic gain control (DAGC).

coarse CFR mechanism, where Fs is the sampling frequency, E. Digital Automatic Gain Control
Rs is the nominal symbol frequency and Rs is the recovered Digital automatic gain control (DAGC) takes place after
symbol frequency. After the convergence of the coarse carrier the first level of phase recovery and is based on a data-
recovery loop, fine carrier recovery is initiated where the aided (pilot-assisted) vector tracker mechanism (DA-VT) [13],
frequency offset error is in the order of a few hundreds of kHz. which utilizes the known pilot symbols in order to determine
Fine frequency recovery deploys a feed-forward estimation al- the amplitude multiplication factor. Therefore, the DAGC is
gorithm, derived from an alteration of the L&R technique [11], activated during the transmission of the pilot fields and it
and an integrator look-up table for the respective frequency is frozen during data symbol transmissions, where proper
offset removal. Fig. 5 depicts the fine frequency recovery amplitude adjustments are applied. Fig. 8 shows the DAGC
scheme, which is also based on a closed loop structure. unit.

D. Phase Recovery F. Constellation Decoder

Phase recovery needs to cope with residual frequency offset After the various synchronization parameters have been
resulting from both carrier recovery procedures. In case of compensated, the complex I/Q symbols of the incoming frame
low order modulation transmissions (QPSK or 8PSK), a pilot- are demapped into the data bit sequence based on the used
assisted maximum-likelihood (ML) feed-forward estimator is modulation efficiency. The DVB-S2 standard supports the
used for computing the average phase of each pilot field [8]. following modulation formats: QPSK, 8PSK, 16APSK and
Phase compensation is based on the interpolation between the 32APSK. The output bit sequence is grouped into coded data
estimations of two consecutive pilot fields. When high-order frames (blocks) that feed the FEC decoding unit.
modulations of 16APSK or 32APSK are used, an additional Fig. 9 describes the format of the physical layer frame
phase synchronizer is needed, which consists of a closed-loop (PLFRAME) [1]. The FEC encoded data, i.e. the LDPC
based on the NDA phase error detector of Q-th power (Q=3 codeword, form the FECFRAME, the length of which is 64800
for 16APSK and Q=4 for 32APSK) [12]. This NDA feedback or 16200 bit depending on the type of the DVB-S2 frame,
loop is located after the digital amplitude control unit, which namely normal or short frame respectively. Based on the
is described in the next subsection, and is initiated as soon as modulation efficiency, the FECFRAME is divided into S slots
the ML feed-forward coarse estimator has reached its steady of complex symbols, which form the XFECFRAME. The size
state. Figures 6 and 7 show the coarse and fine phase recovery of each slot is 90 symbols. The number of slots is given by
units respectively. S = ηLDPC /(90 · ηMOD ), where ηLDPC is the size of the LDPC
 TABLE I
PARAMETERS OF THE normal AND short PLFRAME

normal frame: ηLDPC = 64800 bits short frame: ηLDPC = 16200 bits
ηMOD S αPIL K η (%) S αPIL K η (%)
QPSK: 2 360 22 33282 97.35 90 5 8370 96.77
8PSK: 3 240 14 22194 97.32 60 3 5598 96.46
16APSK: 4 180 11 16686 97.09 45 2 4212 96.15
32APSK: 5 144 8 13338 97.17 36 2 3402 95.24

Sx90 symbols Sundance - SMT395

SDRAM TIMERS,
XFECFRAME
256MB, GPIO, LED
Data Link
133MHz
90 symbols DDC
Implementation
Control Link

slot 1 slot 2 slot 16 slot 17 slot 90

FPGA DSP
VirtexII-Pro TMS320C6416T
XC2VP30 EMIFA
1GHz
Data Link 64-bit 133MHz
90 symbols 36 symbols
FEC
Implementation

HEADER slot 1 slot 2 slot 16 PILOTS slot 17 slot 90 Control Link

FLASH
JTAG
8MB, 133MHz

PLFRAME

Fig. 9. Format of the DVB-S2 PLFRAME. Fig. 10. Architecture of the demodulator’s TIM development module.

codeword in bits and ηMOD is the modulation efficiency in

down-converter (DDC) unit, which feeds the input to the
bits-per-symbol.
demodulator, and with the forward error correction (FEC)
In order to form the PLFRAME, a header is inserted in the unit, which receives the output bit stream. The interconnection
beginning of each frame. If pilots are used, then a 36 symbols links are implemented in the FPGA. The development of the
pilot field is inserted every 16 slots of data symbols. Given demodulator’s subunits is based on a multi-thread DSP imple-
that a PLFRAME cannot terminate to a pilot field, the total mentation, where the various signal processing algorithms are
number of pilot fields is αPIL = (S − 1)/16. The total length organized and executed into different threads.
of the PLFRAME in symbols is
 A. Mapping of Demodulator Subunits into Threads
90 × (S + 1) without pilots
K= (1)
90 × (S + 1) + 36 × αPIL with pilots Fig. 11 shows the structure of the demodulator’s thread-
based implementation. The various signal processing units
while the efficiency of the frame format is η = (90 × S)/K. are divided into two threads. The first thread is fed with
Table I displays the different parameters of the normal and the complex I/Q samples derived from the DDC unit, which
short DVB-S2 frame for all constellation formats. is located at a different TIM, and implements part of the
demodulator’s signal processing chain. The second thread
III. S OFTWARE A RCHITECTURE OF D EMODULATOR
completes the demodulation process and drives the output
A LGORITHMS
bitstream to another TIM that implements the FEC operations
The demodulator presented in this work comprises the basic of the DVB-S2 receiver. The two threads are controlled by
component of a software-defined radio (SDR) implementation an appropriate interrupt handler associated with a DSP timer
of a DVB-S2 satellite receiver developed on a powerful and whose frequency is proportional to the sampling rate of the
reprogrammable hardware platform that utilizes four Texas input signal.
Instrument Modules (TIMs) [14]. The demodulator is imple- As shown in Fig. 11, the DDC input samples are transferred
mented in a single TIM that combines a C6416T DSP running to the demodulator’s TIM via a dedicated interface logic. The
at 1GHz along with a Virtex-II Pro (XC2VP30) FPGA [15]. interrupt handler holds a logical FIFO that stores the incoming
As shown in Fig. 10, the demodulator’s TIM is interconnected samples. Using a frequency of twice the nominal symbol rate,
via dedicated high-speed data and control links with the digital in order to account for the STR mechanism (the Gardner
 DSP-Timer DSP-Thread #1 DSP-Thread #2
INT Handler
Frame
Synch
FPGA Buffer FPGA
Symbol Matched A Fine
Dedicated Complex Input PL Symbol Dedicated
Samples Timing Filter/ Phase
Buffer Descr. Demapper
Recovery Downsample Buffer Recovery
Interface Interface
B
Logic Fine Logic
Carrier

DEMUX
DEMUX

DEMUX
Est. Phase Digital
Thread Coarse Est. AGC
Initiation Carrier
Est.
DDC NCO Frequency Control

DSP-Timer

Sample Based Processing PL Frame Based Processing

Fig. 11. Software thread architecture of the DVB-S2 demodulator.

detector needs 2 samples/symbol), the interrupt handler reads handler and resumed after the completion of the first thread.
a block of N samples and then invokes the first thread by
signalling a specific semaphore. B. Demodulator Operational Modes and Threads Execution
The first thread consists of the synchronization mechanisms The presented SDR demodulator has three modes of oper-
that recover the actual symbol rate (STR), identify the start ation. The first mode is called initial acquisition and is the
of a each new frame (PL framer) and compensate the carrier initial mode after power-up. In this mode, the demodulator
frequency offset errors (coarse and a fine CFR). These pro- attempts to recover the symbol rate, as well as to determine
cedures are executed on a block of N samples that has been the start of the PLFRAME. Therefore, during this mode only
transferred from the logical FIFO to a dedicated input buffer, the STR and PL framer stages are executed in the first thread,
which is directly accessible by the various threads. The output while the second thread remains inactive. The operations
of the first thread is enabled as long as the underlying synchro- during this mode are triggered by the timer-based interrupt
nization stages have converged. A two output buffer strategy handler, which signals the availability of a new block of N
is used in order to preserve real-time operation. These buffers samples.
are named A and B in Fig. 11. The size of each buffer equals After the STR and PL framer subunits converge, the op-
to the size of a PLFRAME. When a complete PLFRAME has erational mode of the demodulator is switched to the second
been written into buffer A, the second thread is initiated via mode, which is called frequency acquisition. During this mode,
a dedicated semaphore for processing the stored samples. At the descrambling and carrier frequency recovery stages are
the same time, the first thread stores the compensated samples also executed in the first thread, while the second thread
of the next PLFRAME into buffer B. The interrupt handler remains inactive. In addition, the PL framer functions during
provides efficient synchronization between the two threads in this mode are reduced. The differential PL header detector is
order to preserve real-time functionality. enabled only in a window of M symbols before and after the
The second thread, whose activation is frame-based, im- expected reception of the next frame header. This results in
plements carrier phase recovery, automatic gain control and significant savings on CPU resources, which can be devoted to
demapping. Carrier phase is recovered using two separate other functions. During this mode, the descrambler is enabled
steps: a coarse step that is adequate for single ring constella- in order to generate the unscrambled symbol sequence. The
tions (QPSK and 8PSK) and a fine step, which is necessary for descrambler operates on a complete PLFRAME excluding the
two and three ring constellations (16APSK and 32APSK). The frame header. The coarse frequency recovery mechanism is
automatic gain control mechanism is embedded between the also enabled and drives the frequency control input of the
two steps of the phase recovery, while the demapper comprises DDC’s NCO. The NCO is only updated whenever a pilot field
the last processing stage of the demodulator. The output of the is present. When the coarse recovery subunit converges, its
second thread is the decoded bitstream that feeds the FEC unit processing is paused and the fine compensation algorithm is
of the DVB-S2 receiver. enabled. The latter is also pilot-based and is executed during
In order to support the different modes of the DVB-S2 the pilot fields. The operations during this mode are triggered
signal (see Table I), it is important that the first thread is by the timer-based interrupt handler, as soon as a new block
able to complete the processing of each block of N samples of N input samples is available. The flowchart for the initial
between two successive interrupt signals, even when most acquisition and frequency acquisition modes is shown in Fig.
of its processing stages are active. This requirement imposes 12-(a).
that the first thread is called immediately after the interrupt, When the fine frequency recovery subunit converges, the
while the second thread is paused periodically by the interrupt demodulator’s mode changes to normal operation. During this
 New
Timer Interrupt
Interrupt
Timer Handler
Mode: Normal Operation
Interrupt
Thread #2
Handler 1. STR
(a) (b)
2. Framer
3. Fine Freq. Recovery
Thread #1
New
4. Descrambler
Interrupt

Thread #1 Thread #2 No
Is the processing of current
Thread #2
buffer DONE?
Thread #2
Yes

New
Interrupt
Wait for the Thread #2 No Wait for the
next Interrupt Is the other buffer
next Interrupt
FULL?

Yes
New
Interrupt
Thread #2

Fig. 12. Execution of threads according to the demodulator’s mode of operation: (a) initial acquisition and frequency acquisition, (b) normal operation.

TABLE II
mode, we consider that all synchronization circuits of the D URATION OF normal PLFRAME WITH P ILOT F IELDS FOR 1MBAUD
first thread have converged and most of the errors have been S YMBOL R ATE
compensated. Therefore, the first thread stores the recovered
frames at the output buffers A or B and enables the second ηMOD Total PLFRAME Data Slot Pilot Field
thread in order to process the data. During this mode the STR, (msec) (μsec) (μsec)
the PL framer, the carrier frequency recovery and the output
buffer writing subunits of the first thread are enabled along QPSK: 2 33.282 90 36
with all circuits of the second thread. The flowchart of the 8PSK: 3 22.194 90 36
normal operation mode is depicted in Fig. 12-(b).
16APSK: 4 16.686 90 36
A critical restriction that affects the performance of the
presented multi-thread DSP implementation is related with the 32APSK: 5 13.338 90 36
total processing time of all threads that should not exceed the
total duration of the transmission of a complete PLFRAME.
The mapping of the demodulator’s subunits as well as the
dynamic scheduling of the various DSP circuits according to
the operational modes described in this Section ensure that the prototyping platform and a host computing environment for
processing of all subsequent frames is performed in real-time. visualization of measurements, diagnostics and signal statistics
Table II gives the duration of the normal DVB-S2 frame, as using a custom MATLAB-based application.
well as the duration of one data slot (90 symbols) and one The DVB-S2 signal generator consists of a NEWTEC
pilot field (36 symbols) for 1MBaud symbol rate and for all NTC2277 IF modulator at 70 MHz and an IP host traffic
constellation formats. generator. System parameters such as baud rate, modulation
and coding modes, roll-off factor and transmit power are user
IV. P ROTOTYPING T ESTBED selectable. DVB-S2 signal generation can also be performed
Fig. 13 shows the prototyping testbed, used for the devel- by Vector Signal Generators (VSG). The programmable fre-
opment, testing and demonstration of the DVB-S2 demod- quency conversion unit (FCU) supports multiple signal paths,
ulator. It consists of a versatile laboratory setup based on with independent L-band to IF and IF to L-band conversion
commercially available equipment and custom devices that modules, thus allowing the addition of various signal impair-
enable the measurement and analysis of the DVB-S2 receiver ments at different signal processing stages. The FCU along
functionality and performance under different signal condi- with the VSG provides various signal distortion options, in-
tions and operating modes. In particular, the setup consists of cluding white and colored Gaussian noise and RF interference.
a set of DVB-S2 compliant signal generators, programmable Additionally, the FCU can also be interfaced with an outdoor
up and down frequency conversion units, a noise injection unit with a LNB that provides L-band signal under realistic
and multi-channel fading conditions emulator, the hardware conditions.
 Geostationary Satellite

DownLink
Ku-Band

DVB-S2
Newtec NTC/2277 Terminal
DVB-S2 Compliant IF-Band Modulator ODU

LNB Agilent MXA N9020A

Vector Signal Analyzer
L-Band
L-Band IF

R&S SMU 200A

Vector Signal Generator Newtec NTC/2142 L-Band
IF IF/L – L/IF Frequency Converter
IF Combiner/ IF
Hardware Prototyping
Selector Platform

L-Band

IF

Tx Data Stream Rx Data Stream

Computing
Device

ETHERNET

Fig. 13. The DVB-S2 receiver testbed.

V. C ONCLUSIONS [5] F. M. Gardner, “A BPSK/QPSK timing-error detector for sampled

receivers,” IEEE Trans. Commun., vol. 34, no. 5, pp. 423–429, May
In this work we presented the design and implementation of 1986.
a digital baseband demodulator for DVB-S2 satellite receivers. [6] P. Savvopoulos and T. Antonakopoulos, “Comparative performance
The architecture of the digital demodulator is based on a multi- analysis of symbol timing recovery for DVB-S2 receivers,” In Proc.
13th Ka and Broadband Communications Conference, Turin, Italy, Sep.
thread DSP implementation. Integration of the complex multi- 2007.
domain signal processing stages of the DVB-S2 signal demo- [7] F.-W. Sun, Y. Jiang, and L.-N. Lee, “Frame synchronization and pilot
dulation in a single processor is realized by efficient fixed- structure for second generation DVB via satellites,” International Jour-
nal of Satellite Communications and Networking 2004, vol. 22(3), pp.
point implementations of the various demodulation algorithms 319–339, 2004.
along with dynamic time-scheduling of the different software [8] U. Mengali and A. N. D’Andrea, Synchronization Techniques for Digital
tasks according to the operational modes of the receiver. Receivers. New York: Plenum, 1997.
[9] J. W. Park, H. J. Yun, M. H. Sunwoo, P. Kim and D. Chang, “Efficient
ACKNOWLEDGMENT coarse frequency synchronizer using serial correlator for DVB-S2,” In
Proc. IEEE International Symposium on Circuits and Systems - ISCAS
This work was supported by the European Regional Devel- 2008, pp. 1520 – 1523, Seattle, WA, May 2008.
opment Fund (ERDF) and the Greek Ministry of Development [10] J. W. Park, M. H. Sunwoo, P. Kim, and D. Chang, “An efficient
data-aided initial frequency synchronizer for DVB-S2,” In Proc. IEEE
- General Secretariat for Research and Technology (GSRT) in Workshop on Signal Processing Systems - SiPS 2007, pp. 645 – 650,
the framework of project ‘AKMON’. Shangai, China, Oct. 2007.
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