Block I

Apollo Guidance Computer (AGC)

How to build one in your basement

Part 4: Memory (MEM) Module

John Pultorak
December, 2004
 Abstract
This report describes my successful project to build a working reproduction of the 1964
prototype for the Block I Apollo Guidance Computer. The AGC is the flight computer for the
Ap ollo m oon lan din gs, and is the wo rld’s first in tegra ted c ircuit com pu ter.

I built it in my ba sem ent. It took me 4 yea rs.

If you like, you can build one too. It will take you less time, and yours will be better than
mine.

I docum ented m y project in 9 separate .pdf files:

Part 1 O v ervie w : Introdu ces the p roject.

Part 2 CTL Module: Design and construction of the control module.

Part 3 PROC M odule: Design and construction of the processing (CPU) modu le.

Part 4 MEM Module: Design and construction of the mem ory module.

Part 5 IO Module: Design and construction of the display/keyboard (DSKY) m odule.

Part 6 Assem bler: A cross-a ssem bler for AG C softw are dev elopm ent.

Part 7 C+ + S imu lator: A low-level simulator that runs assemb led AGC code.

Part 8 Flight Software: My translation of portions of the COLOSSUS 249 flight

software.

Part 9 Test & Che ckou t: A suite of test programs in AG C assembly langu age.
 Overview
The Memory Module (MEM) has 5 subsystems: MMI, ADR, EMM/FMM, MBF, and PAR

MM I (Mem ory Module external

Interface)
The M MI in terfaces oth er m em ory
module subsystems (ADR, EMM/FMM,
MB F, and PAR ; describ ed be low) to
external AGC modules. 40-pin IDE
connectors interface to the PROC and
CTL m odules. Inputs from those
modules are buffered to 1 LSTTL load.
A 1 -pin con nector int erfaces to th e IO
mod ule.

EMM /FMM (Eraseable/Fixed

Mem ory)
The EMM/FMM is the AGC m emory.
AGC mem ory is 16-bit word s,
organized into 1024 word banks. The
lowe st ban k (ba nk 0 ) is erasab le
mem ory (EMM), originally implem ented
as core, but implemented here as RAM.
All banks above bank 0 are fixed
mem ory (originally implemented as
rope core, but implemented here as
EPROM). The Block I AGC initially had
12K word s of fixed m em ory. This
implementation has 15K.

The MSB (bit 16) in memory is an odd

parity b it. The low er 15 b its hold
instructions or data.

MB F (M em ory Bu ffer Reg ister)

The MBF has the 16-bit mem ory buffer
register which holds 16-bit data words m oving to and from mem ory. This is also called the G
regis ter.

The AG C tra nsfers da ta to a nd from m em ory th roug h th e G re giste r during the "m em ory
cycle." The memory cycle takes 12 timing pulses (11.72 microseconds). During AGC
operation, data w ords cycle continuo usly from m em ory to the G register and the n back
again to memory.

There are four locations in eraseable memory, at addresses 20-23 (octal), dubbed "editing
location s" beca use w hate ver wa s stored th ere wo uld em erge sh ifted or rotated by on e bit
position. This shifting is performed in the MBF.

PAR (Parity Ge nerate and T est)

The PA R g ene rates and tests th e m em ory p arity bit. Th e low er 15 bits o f each m em ory w ord
hold AG C instru ctions o r data. Ea ch w ord is prote cted b y a 16 th "od d pa rity" bit. This bit is
set to 1 or 0 by a parity generator circuit so a count of the 1's in each memory word always
prod uce s an odd nu m ber. A parity ch ecking circuit tests the p arity bit d urin g ea ch m em ory
cycle; if the bit doesn't match the expected value, the memory word is assumed to be
corrupted and a PARITY ALARM panel light illum inates on the IO module.

ADR (M emo ry Address)

The ADR constructs the AGC m emory address. The address is formed from the S register
which holds the lower 12-bits that directly address the lowest 4K of memory, and the BANK
register, w hich selects hig her m em ory ba nks w hen add ressing is in the fixe d-sw itchab le
mod e.
The AGC transfers data to and from memory through the G register in a process called the
"m em ory cycle." Th e m em ory cycle ta kes 12 timin g pu lses (11 .72 m icrosecon ds). Th e cycle
beg ins at tim ing p ulse 1 (TP1 ) wh en th e AG C load s the m em ory ad dress to b e fetched into
the S register in ADR. Memory hardware retrieves the data word from memory at the
address specified by the S register. Words from erasable memory are deposited into the G
register by timing pulse 6 (TP6); words from fixed memory are deposited by timing pulse 7.
The retrieved
m em ory w ord is
then available in the
G register for AGC
access during timing
pulses 7 through 10.
After timing p ulse
10, data in the G
register is written
back to memory.

The m em ory address

is formed from the
12-bit S register and
the 4-bit BANK
register. M em ory in
the lowest 4 1K
ban ks is directly
addressed by the S
register. The higher
1K ban ks (5 -12 ) are
address through the
bank register as
described in the ADR
subsystem section of
this do cum ent.

The h igh- order bit in

mem ory (bit 15) is an
odd parity bit. If the
me mo ry word is a
data word, the 14 th bit
is the sig n, an d bits
13 through 1 hold the
magnitude. The
num ber
rep resen tation is 1's
com plem ent.

The first half of the

mem ory cycle copies
data from m em ory to
the G register, The
sign bit in m em ory
(bit 1 4) is copied to bits 1 5 an d 14 of th e G re giste r. Bits 1 3 th roug h 1 in m em ory a re
copied to bits 13 th rough 1 in G. This is performed in the MB F and EMM /FMM subsystem s.
The p arity bit (b it 16 in me m ory) is read by the PAR subs ystem and tested a gain st parity
gen erate d on the m em ory w ord copied in to G. If the pa rity bits fail to m atch , a pa rity alarm
is generated.

The 14 th bit in the G register (and the central registers in the AGC) is called the Uncorrected
Sign (U S). This extra sign bit is used as an overflow in dication in m ulti-word op erations.
Normally, the Sign and Un corrected sign should agree. When overflow or underflow
conditions occur, both signs will disagree, and are reconciled by software in an operation at
the end of a lon g string of mu lti-word com putations.

At the end of the memory cycle, the G register is copied back to memory. The sign bit in G
(bit 15 ) is written to the sig n bit (b it 14) in me m ory. Bits 13 throug h 1 in G are w ritten to
bits 13 through 1 in memory. A new odd parity bit is computed in the PAR subsystem and
written to the 16 th bit in mem ory.
T hese d ia gra m s
show the timing
of the m em ory
cycle. The top
chart is a little
m ore
conceptual; the
bottom cha rt
show s the clock
cycles and
control pulses
directly
associa ted w ith
reading
erasea ble
m em ory
(SBEW G) or
fixed m em ory
(SBFWG) to the
G register (the
‘WG ’ part
m ean s ‘write to
G ’) . T he WE
pulse w rites G
back to memory.

CLK1 steps the

sequencer in the
CTL module that
enables the
control signals.
The signals have
tim e to settle
between CLK1
and CLK 2. Da ta
tran sfer occ urs
on CLK2.
This is a functional
diagram of the ADR,
EMM/FMM, and MBF
subsystems in the
MEM modu le.

The diagram is m ine,

but th e style is
borrowed from
original AGC
documentation:
con trol sig nals are
represented by
diamonds. The
arrows show the
direction of data
flow. When a control
signal is asserted,
data is allow ed to
flow through the
diamond.
For example, when
WE is asserted, the
contents of the G
register are written
into era seab le
me mo ry (bank 0 ).

Note the different

formats for data and
instruc tion w ord in
mem ory, shown at
the bottom of the
d ia gra m .
This is a functional
diagram of the
PAR subs ystem in
the MEM m odule.
The diagram was
developed during
the early stages of
my AGC
arch itectu re
analysis in 2001.
 MEM Internal Subsystem Interconnections
This diagram show s internal interconnections for subsystems in the MEM m odule.
 MEM Module External Interfaces
The M EM m odule interfaces to the PR OC an d CTL m odules throu gh 40 -pin IDE ribbon cables.
J102-CTL: CTL-to-MEM I/F
J102 is a 40-pin IDE cable that connects the MEM modu le to the CTL m odule.

INPU TS (to CTL ):

PIN signal fu ll n am e state definition

1 WE WRITE EMEM (97) 0=W rite E-MEM from G
2 S BW G WRITE G (95) 0= W rite G from m em ory
3 GENRST GENERAL RESET (86) 0=G eneral Reset
4 W23 WRITE ADDR 23 (85) 0=Write into SL
5 W22 WRITE ADDR 22 (84) 0=W rite into CYL
6 W21 WRITE ADDR 21 (83) 0=Write into SR
7 W20 WRITE ADDR 20 (82) 0=W rite into CYR
8 WGn WRITE G NORMAL (81) 0=W rite G (norm al gates)
9 WBK WRITE BNK (80) 0=W rite BNK reg
10 RBK READ BNK (70) 0=R ead BNK reg
11 WS WRITE S (46) 0=W rite S
12 WP2 WRITE P2 (44) 0=W rite P2
13 WPx WRITE P NO RESET (43) 0= W rite P (do n ot reset)
14 WP WRITE P (42) 0=W rite P
15 WGx WRITE G NO RESET (37) 0= W rite G (do not reset)
16 TP TEST PARITY (30) 0= Test pa rity
17 RP2 READ PARITY 2 (14) 0=Read parity 2
18 RG READ G (12) 0=Read G
19 GP GEN PARITY (5) 0= Gen erate Pa rity
20 CLG CLR G (2) 0= Clear G
21 CLK2 CLOCK2 1.02 4 M Hz A GC clock ph ase 2 (n orm ally
low)
22 CLK1 CLOCK1 1.02 4 M Hz A GC clock ph ase 2 (n orm ally
low)
23 NPURST POWER U P RESET 0=reset, 1=normal operation.
24 SW CLK DEBOUNCE CLOCK low freq clk for switch debounce (not
used)
25 FCLK CLOCK MODE 1= free-runn ing clk mo de; 0= sing le clk
mode

OUT PUTS (from CTL):

PIN signal fu ll n am e state definition

31 EQU_16 ADDRESS = 016 (1) 0=CADR in register S = 016
32 EQU_17 ADDRESS = 017 (2) 0=CADR in register S= 017
33 GTR_17 ADDRESS > 017 (3) 0=CADR in register S > 017
34 EQU_25 ADDRESS = 025 (4) 0=CADR in register S = 025
35 GTR_27 ADDRESS > 027 (5) 0=CADR in register S > 027
36 GTR_1777 ADDRESS > 01777 (6) 0=CADR in register S > 01777
37 AD_1 ADDRESS (1) where AD_4 is MSB, AD_1 is LSB
38 AD_2 ADDRESS (2)
39 AD_3 ADDRESS (3)
40 AD_4 ADDRESS (4)
J105-MEM: MEM -to-PROC I/F
J102 is a 40-pin IDE cable that connects the MEM modu le to the PROC modu le.

INPU TS (to M EM):

PIN signal fu ll n am e state definition

1 WB_01 WRITE BUS 01 (lsb)
2 WB_02 WRITE BUS 02
3 WB_03 WRITE BUS 03
4 WB_04 WRITE BUS 04
5 WB_05 WRITE BUS 05
6 WB_06 WRITE BUS 06
7 WB_07 WRITE BUS 07
8 WB_08 WRITE BUS 08
9 WB_09 WRITE BUS 09
10 WB_10 WRITE BUS 10
11 WB_11 WRITE BUS 11
12 WB_12 WRITE BUS 12
13 WB_13 WRITE BUS 13
14 WB_14 WRITE BUS 14
15 WB_15 WRITE BUS 15 US (overflow ) bit
16 WB_16 WRITE BUS 16 SG (sign ) bit

OUT PUTS (from ME M):

PIN signal fu ll n am e state definition

40 RB_01 READ BUS 01 (lsb)
39 RB_02 READ BUS 02
38 RB_03 READ BUS 03
37 RB_04 READ BUS 04
36 RB_05 READ BUS 05
35 RB_06 READ BUS 06
34 RB_07 READ BUS 07
33 RB_08 READ BUS 08
32 RB_09 READ BUS 09
31 RB_10 READ BUS 10
30 RB_11 READ BUS 11
29 RB_12 READ BUS 12
28 RB_13 READ BUS 13
27 RB_14 READ BUS 14
26 RB_15 READ BUS 15 US (overflow ) bit
25 RB_16 READ BUS 16 SG (sign ) bit

22 BUSY7 READ BUS BUSY 0=BNK register output to read bus

21 BUSY5 READ BUS BUSY 0=G register output to read bus
MEM CONTROL PANEL SWITCHES

AGC/MANUAL Permits memory to be examined and loaded when the switch is in the
MANUAL position and the AGC is halted.

EXAM Loads the address counter with the contents of the switch register. To
work, the following switches m ust also be set: AG C/M ANU AL -->
MANUAL

NEXT Steps the address to the next location. To work, the following switches
must also be set: AGC/MANUAL --> MANUAL

READ/WR ITE Displays m em ory contents in the R EAD position; displays sw itch
register contents in the WRITE position.

LOAD Load memory with data manually entered into the switch register. To
work, the following switches must also be set prior to LOAD: CLOCK
CON TRO L (on CTL m odule) --> STEP; A GC/M ANU AL --> M ANU AL;
READ/WR ITE --> WRITE

CLEAR PARITY Clears a parity alarm indication by resetting the parity alarm (PALM)
register. The parity alarm indicator is on the IO modu le.
MEM CONTROL SWITCH CONNECTIONS

PIN signal state definition

1 READ/WR ITE GND= read
2 AGC/MANUAL GND= manual
3 EXAM GND=examine
4 NEXT GND= examine next
5 CLEAR PARITY GND= clear
6 LOAD LOAD switch conta ct
7 LOAD LOAD switch conta ct

PIN signal fu ll n am e state definition

1 D1 DATA1 LSB on switch bus 101
2 D2 DATA2
3 D3 DATA3
4 D4 DATA4
5 D5 DATA5
6 D6 DATA6
7 D7 DATA7
8 D8 DATA8
9 D9 DATA9
10 D10 DATA10
11 D11 DATA11
12 D12 DATA12
13 D13 DATA13
14 D14 DATA14
15 D15 DATA15
16 D16 DATA16 LSB on switch bus 101
17 GND GND
MEM INDICATORS

These indicator lamps show the

current state of all registers and
som e add itiona l, imp ortant lo gic
signals produced by the MEM
m odu le. AG C n um bers are
represen ted in o ctal, so all
register lamps are in groups of
three. At the time the photo was
taken the AGC was running
the COLOSSUS 249 flight
softw are lo ad, executin g V erb
16 , Nou n 36: a m onitor verb
wh ich disp lays th e AG C real tim e
clock.
 ADR (Memory Address)
The AGC has a 14-bit address range. Memory address is selected by the 12-bit S register
and th e 4-b it BA NK regis ter.
S: the 12-bit mem ory address register, which holds the lower portion of
the m em ory address.
BANK: the 4-bit mem ory bank register, which selects the mem ory bank when
addressing is in the fixed-switchable mode.

Each A GC instru ction has a 12 -bit a dd ress fiel d. Th e low er bits (1-1 0) a dd ress m em ory
inside each bank. Bits 11 and 12 select the bank:
00: selects the erasable memory bank; the BANK register is ignored.
01: selects th e low est ban k (ba nk 1 ) of fixed m em ory; the BAN K reg ister is
ignored.
10: selects th e nex t ban k (ba nk 2 ) of fixed m em ory; the BAN K reg ister is
ignored.
11: selects the BANK register, which is used to address any bank above 2.
If the BA NK register con tains 0 , 1, or 2, the B AN K reg ister is
overridden and bank 3 is selected.

Banks 1 and 2 are called "fixed-fixed" mem ory, because they are always available,
regardless of the contents of the BANK register. Banks 3 and above are called
"fixed -sw itchable" becau se th e sele cted ban k is determ ined by the B AN K reg ister.

Type:
E Eraseab le M em ory
FF Fixe d-F ixed Me m ory
FS Fixe d-S wit cha ble M em ory

S R egis ter:
14-b it BANK bits 12-b it
address bank type Reg. 12,11 address
00000 - 01777 0 (E) ignored 00 0000 - 1777
02000 - 03777 1 (FF) ignored 01 2000 - 3777
04000 - 05777 2 (FF) ignored 10 4000 - 5777
06000 - 07777 3 (FS) 0000 - 0011 11 6000 - 7777
10000 - 11777 4 (FS) 0100 11 6000 - 7777
12000 - 13777 5 (FS) 0101 11 6000 - 7777
14000 - 15777 6 (FS) 0110 11 6000 - 7777
16000 - 17777 7 (FS) 0111 11 6000 - 7777
20000 - 21777 8 (FS) 1000 11 6000 - 7777
22000 - 23777 9 (FS) 1001 11 6000 - 7777
24000 - 25777 10 (FS) 1010 11 6000 - 7777
26000 - 27777 11 (FS) 1011 11 6000 - 7777
30000 - 31777 12 (FS) 1100 11 6000 - 7777

BANK register (B) + S register (S) Decode s to address:

B4 B3 B2 B1 S12 S11 A14 A13 A12 A11
X X X X 0 0 0 0 0 0
X X X X 0 1 0 0 0 1
X X X X 1 0 0 0 1 0

0 0 0 0 1 1 0 0 1 1
0 0 0 1 1 1 0 0 1 1
0 0 1 0 1 1 0 0 1 1
0 0 1 1 1 1 0 0 1 1

0 1 0 0 1 1 0 1 0 0
0 1 0 1 1 1 0 1 0 1
0 1 1 0 1 1 0 1 1 0
0 1 1 1 1 1 0 1 1 1

1 0 0 0 1 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
1 0 1 0 1 1 1 0 1 0
1 0 1 1 1 1 1 0 1 1

1 1 0 0 1 1 1 1 0 0
1 1 0 1 1 1 1 1 0 1
1 1 1 0 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1

X= don ’t care

This is an early conceptual diagram of

ADR architecture. The WRITE bus loads
the B NK register or S reg ister. Outp uts
from both registers feed into the bank
decoder to gen erate the bank address.
The A DR gen erates som e logic
signals to test the add ress.
Thes e are inte rnally u sed in
ME M a nd a lso m ade a vailab le
to the external modules. The
GTR signals test whether the
generated address is greater
than 1 777, 27 , or 17 (all octal).

The EQU logic tests whether the

gen erated add ress is equ al to a sp ecific
value: 14, 16, 17, or 25.
The bank select logic chooses
betw een the S regis ter or a
combination of the S register
and the ba nk reg ister to
generate addre ss b its 1 4-11 . It
uses S register bits 11 and 12
to make the decision. The
selection signa l enab les tri-
state buffer A or B to produce
the correct bank ad dress.
ADR INPUTS:

I/F signal fu ll n am e state definition

CLK:
CLK1 CLOCK 1 1=read bus setup; inhibit read bus output
CLK2 CLOCK 2 data transfer occurs on falling edge
CPM:
GENRST GENERAL RESET 0= reset A DR regis ters

RBK READ BANK 0=output BNK register to read bus

WBK WRITE BANK 0=w rite into BNK register
from write bus

WS WRITE S 0=w rite into S register

from write bus
WBUS:
WB_01 WRITE BUS 01
...
WB_14 WRITE BUS 14

ADR OUTPUTS:

I/F signal fu ll n am e state definition

MEM:
AD_11 ADDRESS BUS 11 ban k select bits
...
AD_14 ADDRESS BUS 14

AD_1 ADDRESS BUS 1 low order add ress

...
AD_10 ADDRESS BUS 10

various:
EQU_16 ADDRESS = 016 0=CADR in reg S = 016
EQU_17 ADDRESS = 017 0=CADR in reg S = 017
GTR_17 ADDRESS > 017 0=CADR in reg S > 017
EQU_25 ADDRESS = 025 0=CADR in reg S = 025
GTR_27 ADDRESS > 027 0=CADR in reg S > 027
GTR_1777 ADDRESS > 01777 0=CADR in reg S > 01777

RBUS:
RB_01 READ BUS 01
...
RB_16 READ BUS 16

BUSY READ BUS BUSY 0=output to read bus

 EMM/FMM (Eraseable/Fixed Memory)
MEM INPUTS:

I/F signal fu ll n am e state definition

CLK:
CLK2 CLOCK 2 data transfer occurs on CLK2

CPM:
WE WR ITE ERASEABLE 0= write m em ory bu s to
erase able m em ory
S BW G WRITE G (MEM) 0=read eraseable or fixed
memory onto memory bus

ADR: GTR_1777 ADDRESS > 01777 0=CADR in reg S > 01777

AD_01 ADDRESS BUS 01

...
AD_10 ADDRESS BUS 10

AD_11 ADDRESS BUS 11 bank select portion of

address bus
...
AD_14 ADDRESS BUS 14 bank select portion of
address bus

BIDIRECTIONAL (IN/OUT):

I/F signal fu ll n am e state definition

EMM/FMM:
MEM_01 MEMORY_BUS 01 Mem ory word form ats:
... inst: 15-13 :op code; 12 -1:add ress
MEM_15 MEMORY_BUS 15 data: 15:S G; 1 4-1 d ata
MEM_16 MEMORY_BUS 16 parity (odd) bit for memory bus
 MBF (Memory Buffer Register)
The AGC has a 16-
bit G register for
transferring data to
and from m emory.
WRITE bus data can
be w ritten direc tly
into the G regis ter,
or can be bit-shifted
before w riting. D ata
from the G register
can be copied to the
READ bus, or to the
me mo ry bus.

The following
section shows how
bits are sh ifted in
bus-to-register-to-
m em ory tra nsfers.
The row of 16
comm a-separated
entries rep resent b it
locations at the
destin ation ; the leftm ost entry is the M SB , and th e rightm ost is the LS B. Th e desig natio n in
each location identifies source bit location. This will become clearer shortly.

In memory, the 16 th bit is the odd parity bit, and the 15th bit is th e sig n. In th e G re giste r,
the bits are flipped: the 16 th bit is the sign, and the 15 th bit is the parity. The WE pulse,
which writes from the G register to memory, causes the sign bit (SG; bit 16 in G) to be
written to bit 15 in m em ory. Parity is written to mem ory from the pa rity generator (PAR ),
not from the p arity bit in G. (T he G parity bit holds th e pa rity rea d from m em ory.)

WE:
BX, SG, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1

Data is written from m em ory to G b y the S BW G con trol pulse . The sig n in m em ory (SG ; bit
15) is written to bit 16 in G. The parity bit (bit 16 in memory) is written to bit 15 in G by the
P AR su bsy stem .

SBWG:
SG, BX, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1

Data is written into G from the WRITE bus using WG (no shift), or one of the following
control pulses that prod uce the followin g shifts:

W20:
B1, BX, SG, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2
W21:
SG, BX, SG, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2

W22:
B14, BX, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, SG

W23:
SG, BX, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, SG

Data is read from G to the READ bus as follows. The parity bit (bit 15 in G) is not transferred
to the read bu s; instead, the sign b it is copied onto bits 15 an d 16 of the R EAD bus.

RG:
SG, SG, B14, B13,
B12, B11, B10, B9, B8,
B7, B6, B5, B4, B3, B2, B1

Some of the design that

went into the
combinational logic that
sets bit 16 in the G
register from the READ
bus is shown here. The
MB _B1 6 ou tput co ntrols
the 16th bit for the W20
and W 21 control pu lses.
The MB_C16 output controls the
16 th bit for the W22 and W23
control pulses.
MBF INPUTS:

I/F signal fu ll n am e state definition

CLK:
CLK1 CLOCK 1 1=read bus setup; inhibit read bus output
CLK2 CLOCK 2 data transfer occurs on falling edge

CPM:
RG READ G 0=output G register to read/write bus
WE WR ITE ERASEABLE 0=output G register to memory bus
GTR_17 ADDRESS > 017 0=CADR in register S > 017

S BW G WRITE G (MEM) 0=write G from memory bus

WGN WRITE G 0= write G from rea d/w rite
bus (no sh ift)
WGX WRITE G 0= write G from rea d/w rite
bus (no sh ift)
W20 WRITE G (SHIFT) 0=w rite G
W21 WRITE G (SHIFT) 0=w rite G
W22 WRITE G (SHIFT) 0=w rite G
W23 WRITE G (SHIFT) 0=w rite G

GENRST GENERAL RESET 0=G eneral Reset

WBUS:
WB_01 WRITE BUS 01
...
WB_14 WRITE BUS 14
WB_15 WRITE BUS 15 US (overflow ) bit for write
bus
WB_16 WRITE BUS 16 SG (sign) bit for write bus

MBF OUTPUTS:

I/F signal fu ll n am e state definition

RBUS:
RB_01 READ BUS 01
...
RB_14 READ BUS 14
RB_15 READ BUS 15 US (overflow) bit for read/write bus
RB_16 READ BUS 16 SG (sign) bit for read/write bus

BUSY READ BUS BUSY 0=output enabled to read bus

BIDIRECTIONAL (IN/OUT):

I/F signal fu ll n am e state definition

EMM/FMM:
MEM_01 MEMORY_BUS 01 Mem ory word form ats:
... inst: 15-13 :op code; 12 -1:add ress
MEM_15 MEMORY_BUS 15 data: 15:S G; 1 4-1 d ata
MEM_16 MEMORY_BUS 16 parity (odd) bit for memory bus
 PAR (Parity Generation and Test)

The PAR subsystem checks

the m em ory pa rity bit
durin g each me m ory cycle
and gen erates an alarm if
the parity bit in m em ory
does not match the
expected odd parity. The
PAR subsystem also
generates parity from the
contents of G and writes
this parity back to memory.
This block diagram of the PAR
subsystem emerges from the
previous diagram.

This is the combinational

logic u sed to g enera te
the input to the G15
register. Th is is the 1- bit
register that holds bit 15
(the parity bit) for the G
register. The remainder
of the G register (bits 1-
14 and bit 16) is in the
M BF su bsy stem .

The m interms are written

ou t on top . De Morg an ’s
Theo rem and a little
bubble-pushing changes
the OR gate into a NAND.
PAR INPUTS:

I/F signal fu ll n am e state definition

CLK:
CLK2 CLOCK 2 data transfer occurs on
falling edge

CPM:
RG READ G15 0=w rite G15 into P
RP2 READ P2 0=write P2 into G15

WP WRITE P 0=write P (same as WPX)

WPX WRITE P 0=write P (same as WP)
WP2 WRITE P2 0=write P2 from 1-15
generator

S BW G WRITE G15 (MEM) 0= writ e G1 5 from m em ory

parity b it

GP WRITE G15 0=write G15 from 1-15

generator (same as WGX)
WGX WRITE G15 0=write G15 from 1-15
generator (same as GP)
CLG CLEAR G15 0=clear G15

TP TEST PARITY 0=test parity from P-15

ADR:
GTR_27 ADDRESS > 027 0=CADR in Register S evaluates to > 027

WBUS:
WB_01 WRITE BUS 01
...
WB_14 WRITE BUS 14
WB_15 WRITE BUS 15 US (overflow) bit for write bus
WB_16 WRITE BUS 16 SG (sign) bit for write bus

MON:
CLRPLM CLEAR PA RITY ALM 0= clea r parity ala rm

PAR OUTPUTS:

I/F signal fu ll n am e state definition

MON
PARALM PARITY ALARM 1= parity alarm
BIDIRECTIONAL (IN/OUT):

I/F signal fu ll n am e state definition

EMM/FMM:
MEM_16 MEMORY_BUS 16 parity (odd) bit for memory bus
 Fabrication
The M EM mo dule is (3) 13 "x5" circu it board s, and 1 con trol pan el.

Module Rack

The m odule framework is designed

to resemble a relay rack, but
scaled to fit the c ircuit boa rd
dimensions. It is constructed out
of 1"x2" pine and spray-painted
semi-gloss gray.

Circuit boards are mounted to the

rack by 2 phillips screws at either
end . Nylon s pacers (1 /4") are
used as standoffs to hold the
board edges above the rack. The
boards are mounted so the chips
are in the b ack and the p ins a re
wirin g are visib le from the front.

Power is distributed by 2 heavy

aluminu m bu s bars mounted
vertically, one per side, on the
back of the module. Machine
screws are mounted through the bus bars at evenly-spaced intervals to provide connection
points for the boards.

Solid copper wire (24 gauge) connects the boards to the bus bars. Ring terminals are used
on the bus bar side of the connection. On the circuit board size, the wires are soldered
directly to the supply rails.

Materials were purchased from Home Depot, ACE Hardware, and Radio Shack.

Circuit Boards

The circuit boards are 13 "x5" general p urpose prototypin g boards,

epo xy g lass with dou ble- side plated th roug h pads on 0.1" centers
(JAM ECO 2147 7CL).

ICs are mounted in level 3 machine tooled wire-wrap sockets: 8, 14,

16, 20, 24, and 28 pin (JAMEC O). Each socket has the pin-out labeled
wit h a w ire-w rap sock et ID m arke r, wh ich slips o nto the socke t befo re
wra pping (JAM ECO). T he p art num ber is writt en o nto the ID m arke r.

Sockets are arranged in 4 horizontal rows on each board, with about

10 sockets per row.

Pow er is di stribu ted o n th e ba ck-side o f each boa rd by bare 24-ga ug e solid copp er w ire
supply rails soldered at equal intervals to Klipwrap terminals: 3-prong terminals with a
squ are tail for w ire-wra ppin g (JA ME CO 341 63C L). A + 5V ra il runs a bove each row of soc kets
and a ground rail runs below. Each rail connects directly to the aluminum module power bus
usin g a rin g tail con nec tor.

On the p in sid e of th e bo ard, all con nec tion s are m ade w ith 3 0 A W G K yna r wire -w rap wire
(JAMECO ). Red wire is used for direct connections to the +5V supp ly rail. Black wire is used
for direct connections to ground. White wire is used for everything else.

Power connections from the supply rails to each ICs are double-wrapped. Bypassing
capacitors (.1 uf disc ) are soldered across the supply rails at the Klipwrap terminals; about
1 capacitor for every 2 IC packag es.

All connections were stripped and hand-wrapped using a Radio Shack hand-wrap tool. As
each connection was made, the corresponding line on the schematic was marked with a
colored h igh ligh ter.

DIP resistor networks (JAMECO) plugged into 20-pin wire-wrap sockets were used as current
limiting resistors for the panel ind icators.
MEM Printed Circuit Board (PCB) A

The A b oard contain s the zero-insertion force (ZIF) sockets for the fixed mem ory EPRO Ms,
and the 2 4 0-pin IDE con necto rs that in terface to the other m odu les. The e raseab le
me mo ries (U101 , U102 ) are also clearly visible next to the EPRO Ms. The M em ory Address
(AD R) an d Erase able/ Fixed Mem ory (EM M/F MM ) sub system s are prim arily loca ted on this
board.
MEM Printed Circuit Board (PCB) B

The B board contains the display indicators, their current-limiting resistor networks, and the
open collector drivers. The display panel is a sheet of white styrene plastic. A push pin was
used to make holes through the plastic and the LEDs were inserted in rows. The panel was

hand -lette red w ith a n in delible m arke r.

MEM Printed Circuit Board (PCB) C

The C b oard prim arily contains the M em ory Buffer (MBF) a nd Parity Ge neration an d Test
(PAR ) subsystem s.
 Parts (ICs)
74LS00 (11) U50,U25,U26,U27,U40,U32,U33,U34,U43,U44,U53
74LS02 (3) U52,U31,U55
74LS04 (12) U39,U28,U51,U56,U48,U46,U45,U41,U30,U35,U36,U54
74LS06 (21) U2 0,U 19 ,U1 8,U 15 ,U1 6,U 17 ,U1 4,U 13 ,U1 2,U 10 ,U1 1,U 9,U 6,U 7,U 8,U 5,U
4,U21,U22,U23,U24
74LS10 (3) U49,U37,U42
74LS20 (2) U47,U29
74LS27 (2) U2,U38
74LS74 (1) U1
74LS86 (1) U3
74LS154 (1) U72
74LS193 (4) U63,U64,U65,U66
74LS244 (31) U57,U58,U59,U60,U61,U62,U67,U68,U69,U70,U71,U73,U83,U84,U85,
U86,U87,U88,U89,U90,U91,U92,U93,U94,U95,U96,U97,U98,U103,U10
4,U105
74LS273 (10) U74,U75,U76,U79,U80,U81,U82,U106,U107,U108
74S280 (2) U77,U78
27C128 (2) U99,U100
2016 (2) U101,U102

Power Budget
qty mA (ea) m A (tot)
74LS00 11 2.4 26 .4
74LS02 3 2.4 7.2
74LS04 12 3.6 43 .2
74LS06 21 3.6 75 .6
74LS10 3 1.8 5.4
74LS20 2 1.2 2.4
74LS27 2 3.4 6.8
74LS74 1 4.0 4.0
74LS86 1 6.1 6.1
74LS154 1 6.2 6.2
74LS193 4 19 .0 76 .0
74LS244 31 32 .0 99 2.0
74LS273 10 17 .0 17 0.0
74LS280 2 16 .0 32 .0
27C128 2 25 .0 50 .0
2016 2 25 .0 50 .0
LED 124 20 .0 24 80 .0
-------
4.0 Amps total
1.6 Am ps (excludin g LEDs)