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Proc Emb - Ch1

The document outlines a course on embedded processors using the ARM Cortex-M4 architecture, covering topics such as the ARM architecture, assembly and C programming, peripherals, and implementing a DSP application. The course objectives are to understand the ARM-M4 core and programming, master development tools, and practice embedded software coding. The syllabus lists 14 sessions that include lectures, labs, and a practical exam on various ARM and embedded system concepts.

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Jihene Zgolli
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0% found this document useful (0 votes)
55 views

Proc Emb - Ch1

The document outlines a course on embedded processors using the ARM Cortex-M4 architecture, covering topics such as the ARM architecture, assembly and C programming, peripherals, and implementing a DSP application. The course objectives are to understand the ARM-M4 core and programming, master development tools, and practice embedded software coding. The syllabus lists 14 sessions that include lectures, labs, and a practical exam on various ARM and embedded system concepts.

Uploaded by

Jihene Zgolli
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Telecommunication Engineers – 2nd Year

Embedded Processors
ARM Cortex-M4 Architecture & Embedded Programming Practice

Adel Ghazel
[email protected]

1 September 2017
Course Objectives
▪ Target knowledge
▪ Hardware architecture and technologies for widely used processors
▪ Machine level programming concept and practice
▪ Embedded real-time software application coding and porting on target MCU board

▪ Target skills
▪ Understand ARM Cortex-M4 MCU core & peripherals architecture
▪ Master an Integrated Development Environment (IDE) for ARM processors programming
▪ Practice ARM Assembler programming
▪ Practice Embedded C software coding and porting to ARM MCU target
▪ Master the configuration and the programming of ARM Cortex-M4 peripherals
▪ Build and test the implementation of a DSP application software on ARM MCU target

2
Course Syllabus

▪ Embedded Processors Basic Concepts


▪ ARM Cortex-M4 Architecture
▪ ARM Assembler & Programming Practice
▪ Embedded C & Programming Practice
▪ ARM Cortex-M4 I/Os & Implementation Practice
▪ Embedded Application Porting on ARM Cortex-M4 Eval Board
▪ ARM Cortex-M4 Interruptions & Timers and Implementation Practice
▪ ARM Cortex-M4 ADC & DAC
▪ DSP Application Implementation Practice

3
Course Activities Organisation
Session Designation Activity
S01 Embedded Processors Basic Concepts Lecture
S02 ARM Cortex-M4 Architecture Lecture
S03 ARM Assembler Syntax & Coding Examples Lecture
S04 Initiation to the ARM IDE – Simulation Mode Lab
S05 Assembler Programming Lab Lab
S06 Embedded C Programming Techniques Lecture
S07 Embedded C Programming Lab Lab
S08 ARM Cortex-M4 I/Os Lecture
S09 Embedded Software Application Coding and Porting to Eval Board Lab
S10 ARM Cortex-M4 Interruptions & Times Lecture
S11 ARM Cortex-M4 Interruptions & Timers Lab Lab
S12 ARM Cortex-M4 ADC & DAC Lecture
S13 DSP Application Implementation Lab Lab
S14 Practical Exam Lab Exam
4
Chapter 1
Embedded Processors Basic Concepts

5 September 2017
Chapter Syllabus

▪ Introduction to Embedded Systems


▪ Microprocessor Units
▪ Classes of Architectures
▪ Embedded Processors Applications

6
INTRODUCTION
TO EMBEDDED SYSTEMS

7
Embedded System Definition
▪ No formal definition of an embedded system

▪ It is generally accepted to be a type of computer designed to solve a specific problem or task.

▪ This is in contrast to a general-purpose computer such as a PC or workstation.

▪ Embedded systems typically use a microprocessor combined with other hardware and software to solve a
specific computing problem

8
Embedded System Components
▪ Microprocessors Hardware range from simple (by today’s standards) 8-bit microcontrollers to the fastest
and most sophisticated 64-bit microprocessors.
▪ Embedded system Software ranges from a small executive to a large Real-Time Operating System (RTOS)
with a Graphical User Interface (GUI).
▪ Typically, the embedded system software must respond to events in a deterministic way and should be
guaranteed not to crash.

9
Computer Design Concept

Processing Memory Test

Power

communications Integration

Security
Human & Machines

10
Embedded Design Lifecycle

11
Embedded Processor Choice

Real-time
Constraints Legacy
Code Power
Budget

Cost of
Goods
Performance

Tool
Time to Support
Market

12
MICROPROCESSOR UNITS

13
Processor Basic Architecture
Address Bus

Data Bus

Control & Command Bus


CPU

Input/Output
Memory
Interfaces

▪ CPU : Central Processor Unit


▪ Intelligent Unit with program controlled operation
▪ Memory
▪ Information storage unit (Data & Program)
▪ Inputs / Outputs interfaces
▪ Allowing bidirectional communication with peripheral units

14
Buses Definition
Address Bus

CPU Data Bus


▪ Address Bus
◦ Unidirectional CPU
Control & Command Bus

◦ Address transfer media

▪ Data Bus Memory Input/Output


Interfaces
◦ Bidirectional
◦ Data transfer between CPU, memory and I/O interfaces

▪ Control & Command Bus


◦ Read, Write, … commands generated by CPU
◦ To CPU : READY, Interruptions,...

15
CPU Organisation
▪ Logic circuit with program-based operation and composed of 3 functional parts

Registers Information supports: instruction codes, data, address

ALU Arithmetic & Logic Unit supporting arithmetic (+, -,…)


and logical operations (AND, OR, XOR, rotation,…..)

Quartz
Control Instructions decoding
Unit
Time supervision of processing operations

16
ALU Description

Arithmetic Operations
addition
Operation
selection subtraction
Accumulator
Increment
Result Decrement
ALU …
Logical Operations
Temporary Complement
Register
AND
State
Register OR
XOR
Rotation

17
CPU Registers
▪ Accumulator: used during ALU operations, it contains one of operands before execution and the
obtained result after ALU operation

▪ MDR : Memory Data register

▪ MAR : Memory address register

▪ State Register (SR): indicates ALU operation status, Z, CY, P, S,….

▪ Instruction Register (IR) : contains operation code of the instruction being executed

▪ Program counter (PC) : contains address of next instruction to be executed

18
CPU Control Unit
▪ Function: Supervision of CPU operations

▪ Instruction execution steps:


▪ Extraction of operation code from memory and transfer to the Instruction Decoder

▪ Decoding and decomposition of the instruction into elementary operations (µ-instructions)

▪ Sequential execution of elementary operations according to a certain timing

▪ Moving to next instruction

19
Memory Definition
▪ Used for data and programs storage and can be of two types
▪ Accessible only for reading: ROM

▪ Accessible for both reading and writing: RAM

Internal Organization Memory chipset 512 kbit Flash

k bits Word
0 0 1 1 0 1 0 1 ▪ Static : information maintained indefinitely if
0
circuit powered

n Address lines
1
2n locations

A0 RD WR
2 ▪ Dynamic : information lost during time
Addresses

. An-1 ▪ Volatile : information disappear when power


. supply is off
Chip Select CS D0 Dk-1
. ▪ Non-volatile : information conserved after
2n -2 power supply off
k Data lines
2n -1

20
Memory Access Mode

Reading Access
CPU places selected CPU activates Read
address on Address command
Bus
Time
Memory location Memory case content
selected deposed on Data Bus

Writing Access
CPU places selected CPU places Data on CPU activates Write
address on Address Bus Data Bus command
Time

Memory location Written Data in selected


selected Memory location

21
Input / Output Interface
▪ Function: used to establish communication with peripheral units: keyboard, screen, printer, host processor,...
▪ Addressing & Access: similar to memory procedures

Input Input Ethernet Interface


Data Bus
Port

CPU
Output Address Bus
Output
Port
Commands
Control CAN Interface

22
CLASSES OF ARCHITECTURES

23
Embedded Processors Nomenclature
▪ Microprocessors
▪ Architecture: mono-chip CPU, need for external additional circuits
◦ RISC: Reduced Instruction Set Computer
◦ CISC: Complex Instruction Set Computer
▪ Applications: Data processing
▪ Examples: Pentium-Series, PowerPC, MIPS,…

▪ Microcontrollers
▪ Architecture: CPU, RAM, ROM, serial/parallel interfaces, timer, interruption circuits
▪ Applications: process control & management
▪ Characteristics: relaxed processing time constraints, compact instructions set
▪ Examples: 8051, 68HC11, PIC, AdµC7022,…

▪ Digital Signal Processors (DSP)


▪ Architecture: Optimized CPU for real time & repetitive mathematical processing, RAM, ROM,
serial/parallel interfaces, timer, interruption circuits
▪ Examples: ADSP-BF53x, ADSP-TS201, TMS320Cxx, …
24
Classes of Processors Architectures

25
Von Neumann Architecture
Interfaces
General Purpose
Processor
Inputs
One memory shared
for Data & instructions
CPU
(Core) Double use of Data &
Address Buses
Outputs

1. Instruction fetch
2. Data_1 fetch
3. Data_2 fetch
Address Bus

Data Bus Memory


Program & Data
Multiple machine cycles !

John von Neumann (1903 – 1957) is a Hungarian-American


mathematician and physicist
26
Harvard Architecture

Interfaces

▪ Separated PM and DM memories


DMA
PMA
▪ Independent buses for each memory
Inputs

Program ▪ In single machine cycle : (Instr. Fetch &


CPU
Memory
(Core)
Data fetch)
PMD
Outputs ▪ Memory Mapped IO

▪ Core : optimized data flow, MAC


(Multiply-ACcumulates), enhanced
Data (improved, advanced, or sophisticated )
Memory
addressing modes

DMD

27
CISC Processor Mode
▪ CISC (Complex Instruction Set Computer) is the traditional computer architecture using microcode to
execute very comprehensive instructions.

▪ Instructions may be variable in length and use all addressing modes, requiring complex circuitry to decode
them.

▪ CISC are direct representations of high level functions of high level programming languages

▪ In CISC mode one instruction would do all of the work in a single instruction. Example: load up the two
numbers to be added, add them, and then store the result back directly to memory.

▪ CISC concept improves density of information to overcome previous µP technology constraints: lack of
large memories and slow access time, CPU with few registers

▪ General goal at that time was to provide every possible addressing mode for every instruction
(orthogonality principle).

28
RISC Processor Mode
▪ RISC (Reduced Instruction Set Computer) is a computer architecture that reduces chip complexity by
using simpler instructions.

▪ RISC compilers have to generate software routines to perform complex instructions that were previously
done in hardware by CISC computers.

▪ In RISC, the microcode layer and associated overhead is eliminated.

▪ RISC keeps instruction size constant, bans the indirect addressing mode and retains only those instructions
that can be overlapped and made to execute in one machine cycle or less.

▪ The RISC chip is faster than its CISC counterpart and is designed and built more economically

29
RISC vs CISC

▪ RISC machine executes instructions faster because it does not have to go through a microcode conversion
layer.

▪ RISC compiler generates more instructions than CISC compiler for the same processing.

30
Pipeline Technique

IF ID EX MEM WB

5 Instructions per Machine Cycle

31
Advanced Pipeline Architectures

Super-pipeline architecture Super-scaler architecture

VLIW architecture
32
Program Flow Configurations

33
EMBEDDED PROCESSORS
APPLICATIONS

34
Embedded Processors Applications
▪ Consumer electronics

▪ Smart Home equipment's, Cameras, Smart TV, Smart phones, Media-players,


Interactive & Virtual Reality Games,…

▪ Automotive

▪ ABS, GPS and Navigation, Engine Control, ADAS, On Board Entertainment,…

▪ Avionic, space, marine, industrial processes

▪ Air borne and Marine systems, Industrial management systems

▪ Computers & communications

▪ Terminals, Transfer nods, Transmission equipment's, Computer peripherals

35
Classes of Computing Systems
▪ Generic computers
▪ Functions: Data Processing with interactive user interface
▪ Applications: PC, Set-top box, video games, PDA, …

▪ Control systems
▪ Functions: Real time system and process control
▪ Applications: car engines, industrial processes, navigation equipments, …

▪ Signal processing systems


▪ Functions: Fast and repetitive processing on high bit rate data
▪ Applications:Video and audio compression and processing, radar, sonar, …

▪ Communication and networks


▪ Functions: Transmission and multi-user access management
▪ Applications: switches, routers, terminals, base stations, …

36
Smart Phone µP-based Design Example

37

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