SiC780, SiC780A

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Integrated DrMOS Power Stage
DESCRIPTION FEATURES
The SiC780 is an integrated power stage solution • Thermally enhanced PowerPAK MLP6x6-40L
optimized for synchronous buck applications offering high package
current, high efficiency and high power density. Packaged in • Industry benchmark MOSFET with integrated
Vishay's proprietary 6 mm x 6 mm MLP package, SiC780 Schottky diode
enables voltage regulator designs to deliver in excess of
• Delivers in excess of 50 A continuous current
50 A per phase current with 93 % peak efficiency.
• 93 % peak efficiency
The internal Power MOSFETs utilize Vishay’s
state-of-the-art TrenchFET Gen III technology that delivers • High frequency operation up to 1 MHz
industry benchmark performance by significantly reducing • Power MOSFETs optimized for 12 V input stage
switching and conduction losses. • 3.3 V (SiC780ACD)/5 V (SiC780CD) PWM logic with
The SiC780 incorporates an advanced MOSFET gate driver Tri-state and hold-off
IC that features high current driving capability, adaptive • SMOD logic for light load efficiency boost
dead-time control, and integrated bootstrap Schottky
diode, and a thermal warning (THDN) that alerts the system • Low PWM propagation delay (< 20 ns)
of excessive junction temperature. The driver is also • Thermal monitor flag
compatible with a wide range of PWM controllers and • Enable feature
supports Tri-state PWM, 3.3 V (SiC780ACD)/5 V (SiC780CD)
• VCIN UVLO
PWM logic, and skip mode (SMOD) to improve light load
efficiency. • Compliant with Intel DrMOS 4.0 specification
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

APPLICATIONS
• Synchronous buck converters
• Multi-phase VRDs for CPU, GPU and memory
• DC/DC POL modules

TYPICAL APPLICATION DIAGRAM

Fig. 1 - SiC780 Typical Application Diagram

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PIN CONFIGURATION - Bottom View

Fig. 2 - SiC780 Pin Configuration

PIN DESCRIPTION
PIN NUMBER SYMBOL DESCRIPTION
1 SMOD# LS FET turn-off logic. Active low
2 VCIN Supply voltage for internal logic circuitry
3 VDRV Supply voltage for internal gate driver
4 BOOT High side driver bootstrap voltage
5, 37, P1 CGND Analog ground for the driver IC
6 GH High side gate signal
7 PHASE Return path of HS gate driver
8 to 14, P2 VIN Power stage input voltage. Drain of high side MOSFET
15, 29 to 35, P3 VSWH Phase node of the power stage
16 to 28 PGND Power ground
36 GL Low side gate signal
38 THDN Thermal shutdown open drain output
39 DSBL# Disable pin. Active low
40 PWM PWM input logic

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ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE
SiC780CD-T1-GE3 PowerPAK MLP66-40L SiC780
SiC780ACD-T1-GE3 PowerPAK MLP66-40L SiC780A
SiC780DB Reference Board

ABSOLUTE MAXIMUM RATINGS (1)

ELECTRICAL PARAMETER SYMBOL LIMITS UNIT

Input Voltage VIN -0.3 to +22
Control Input Voltage VCIN -0.3 to +7
Drive Input Voltage VDRV -0.3 to +7
Switch Node (DC) VSW -0.3 to +22
V
Switch Node (AC) (2) VSW -7 to +27
Boot Voltage (DC Voltage) VBS -0.3 to +29
Boot to Switching Node (DC Voltage) VBS_SW -0.3 to +7
All Logic Inputs and Outputs (PWM, DSBL, SMOD and THDN) -0.3 to VCIN + 0.3
Max. Operating Junction Temperature TJ 150
Ambient Temperature TA -40 to +125 °C
Storage Temperature -65 to +150
Notes
(1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(2) The specification values indicated “AC” is V
SW to PGND -7 V to +27 V (< 50 ns), max..

RECOMMENDED OPERATING CONDITIONS

PARAMETER MIN. TYP. MAX. UNIT
Input Voltage (VIN) 4.5 - 18
Drive Input Voltage (VDRV) 4.5 5 5.5
Control Input Voltage (VCIN) 4.5 5 5.5 V
Switching Node (LX, DC Voltage) - - 19
BOOT-SW 4 4.5 5.5

THERMAL RESISTANCE RATINGS

PARAMETER MIN. TYP. MAX. UNIT
Thermal Resistance from Junction to Case (to P3 PAD (VSHW) - 2.5 -
°C/W
Thermal Resistance from Junction to PCB - 5 -

S14-1497-Rev. D, 04-Aug-14 3 Document Number: 63788

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ELECTRICAL SPECIFICATIONS
TEST CONDITIONS UNLESS SPECIFIED
VDSBL# = VSMOD = 5 V,
PARAMETER SYMBOL MIN. (3) TYP. (1) MAX. (3) UNIT
VIN = 12 V, VDRV = VCIN = 5 V,
TA = 25 °C
Power Supplies
VDSBL# = 0 V, no switching - 100 -
VCIN Control Logic Input Current IVCIN VDSBL# = 5 V, no switching - 300 - μA
VDSBL# = 5 V, fs = 300 kHz, D = 0.1 - 300 -
fs = 300 kHz, D = 0.1 - 16 25
Drive Input Current (Dynamic) mA
fs = 1 MHz, D = 0.1 - 60 -
IVDRV
VDSBL# = 0 V, no switching - 30 -
Drive Input Current (No Switching) μA
VDSBL# = 5 V, no switching - 60 -
Bootstrap Supply
Bootstrap Switch Forward Voltage VF VCIN = 5 V, forward bias current 2 mA - - 0.4 V
PWM Control Input (SiC780CD)
Rising Threshold Vth_pwm_r 3.4 3.7 4.2
Falling Threshold Vth_pwm_f 0.7 0.9 1.2
Tri-state Voltage Vtri PWM pin floating - 2.3 - V
Tri-state Rising Threshold Vth_tri_r 0.9 - 1.5
Tri-state Falling Threshold Vth_tri_f 3 3.4 3.7
Tri-state Rising Threshold Hysteresis Vhys_tri_r - 225 -
mV
Tri-state Falling Threshold Hysteresis Vhys_tri_f - 325 -
VPWM = 5 V - - 500
PWM Input Current IPWM μA
VPWM = 0 V - - -500
PWM Control Input (SiC780ACD)
Rising Threshold Vth_pwm_r 2.1 2.4 2.8
Falling Threshold Vth_pwm_f 0.7 0.9 1.2
Tri-state Voltage Vtri PWM pin floating - 1.8 - V
Tri-state Rising Threshold Vth_tri_r 0.9 - 1.5
Tri-state Falling Threshold Vth_tri_f 1.9 2.2 2.6
Tri-state Rising Threshold Hysteresis Vhys_tri_r - 225 -
mV
Tri-state Falling Threshold Hysteresis Vhys_tri_f - 275 -
VPWM = 3.3 V - - 300
PWM Input Current IPWM μA
VPWM = 0 V - - -300

S14-1497-Rev. D, 04-Aug-14 4 Document Number: 63788

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ELECTRICAL SPECIFICATIONS
TEST CONDITIONS UNLESS SPECIFIED
VDSBL# = VSMOD = 5 V,
PARAMETER SYMBOL MIN. (3) TYP. (1) MAX. (3) UNIT
VIN = 12 V, VDRV = VCIN = 5 V,
TA = 25 °C
Timing Specifications
Tri-State to GH/GL Rising Propagation
TPD_R_Tri - 20 -
Delay
Tri-state Hold-Off Time TTSHO - 150 -
GH - Turn Off Propagation Delay TPD_OFF_GH - 20 -
GH - Turn ON Propagation Delay No load, see fig. 4.
TPD_ON_GH - 10 -
(Dead Time Rising)
GL - Turn Off Propagation Delay TPD_OFF_GL - 20 - ns

GL - Turn On Propagation Delay

TPD_ON_GL - 10 -
(Dead Time Falling)
DSBL# Hi to GH/GL Rising Propagation
TPD_R_DSBL - 22 -
Delay
DSBL# Lo to GH/GL Falling
TPD_F_DSBL - 10 -
Propagation Delay
DSBL#, SMOD INPUT
Enable 2 - -
DSBL# Logic Input Voltage VDSBL
Disenable - - 0.8
V
High State 2 - -
SMOD Logic Input Voltage VSMOD
Low State - - 0.8
ProtectionL
Rising, On Threshold - 3.7 4.3
Under Voltage Lockout VUVLO V
Falling, Off Threshold 2.7 3.2 -
Under Voltage Lockout Hysteresis - 550 - mV
THDn Flag Set - 160 -
Note (2)
THDn Flag Clear - 135 - °C
THDn Flag Hysteresis - 25 -
THDn Output Low - 0.02 - V
Notes
(1) Typical limits are established by characterization and are not production tested.
(2) Guaranteed by design.
(3) Min. and max. parameters are not 100 % production tested.

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DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-State Function
The PWM input receives the PWM control signal from THDN signal. The SiC780 does not stop operation when the
the VR controller IC. The PWM input is designed to be flag is set. The decision to shutdown must be made by an
compatible with standard controllers using two state logic external thermal control function.
(H and L) and advanced controllers that incorporate Tri-state
Voltage Input (VIN)
logic (H, L and Tri-state) on the PWM output. For two state
logic, the PWM input operates as follows. When PWM is This is the power input to the drain of the high-side
driven above Vth _pwm_r the low side is turned OFF and the power MOSFET. This pin is connected to the high power
high side is turned ON. When PWM input is driven below intermediate BUS rail.
Vth_pwm_f the high side turns off and the low side turns on. Switch Node (VSWH and PHASE)
For Tri-state logic, the PWM input operates as above for The switch node VSWH is the circuit PWM regulated output.
driving the MOSFETs. However, there is an third state that This is the output applied to the filter circuit to deliver the
is entered into as the PWM output of Tri-state compatible regulated high output for the buck converter. The PHASE
controller enters its high impedance state during shut-down. pin is internally connected to the switch node VSWH. This pin
The high impedance state of the controller's PWM output is to be used exclusively as the return pin for the BOOT
allows the SiC780A to pull the PWM input into the Tri-state capacitor. A 20.2 kΩ resistor is connected between GH and
region (see the Tri-State Voltage Threshold Diagram below). PHASE to provide a discharge path for the HS MOSFET in
If the PWM input stays in this region for the Tri-state the event that VCIN goes to zero while VIN is still applied.
Hold-Off Period, tTSHO, both high side and low side
MOSFETs are turned off. This function allows the VR phase Ground Connections (CGND and PGND)
to be disabled without negative output voltage swing PGND (power ground) should be externally connected
caused by inductor ringing and saves a Schottky diode to CGND (control signal ground). The layout of the Printed
clamp. The PWM and Tri-state regions are separated Circuit Board should be such that the inductance separating
by hysteresis to prevent false triggering. The SiC780ACD the CGND and PGND should be a minimum. Transient
incorporates PWM voltage thresholds that are compatible differences due to inductance effects between these two
with 3.3 V logic, and SiC780CD is 5 V logic. pins should not exceed 0.5 V.
Disable (DSBL#) Control and Drive Supply Voltage Input (VDRV,VCIN)
In the low state, the DSBL# pin shuts down the driver IC and VCIN is the bias supply for the gate drive control IC. VDRV is
disables both high-side and low-side MOSFET. In this the bias supply for the gate drivers. It is recommended to
state, the standby current is minimized. If DSBL# is left separate these pins through a resistor. This creates a low
unconnected an internal pull-down resistor will pull the pin pass filtering effect to avoid coupling of high frequency gate
down to CGND and shut down the IC. drive noise into the IC.
Diode Emulation Mode (SMOD) Skip Bootstrap Circuit (BOOT)
When SMOD pin is low the diode emulation mode is enabled The internal bootstrap switch and an external bootstrap
and GL is turned off. This is a non-synchronous conversion capacitor form a charge pump that supplies voltage to the
mode that improves light load efficiency by reducing BOOT pin. An integrated bootstrap diode is incorporated so
switching losses. Conducted losses that occur in that only an external capacitor is necessary to complete the
synchronous buck regulators when inductor current is bootstrap circuit. Connect a boot strap capacitor with one
negative can also be reduced. Circuitry in the external leg tied to BOOT pin and the other tied to PHASE pin.
controller IC detects when inductor current crosses zero Shoot-Through Protection and Adaptive Dead Time
and drive SMOD Lo turning the low side MOSFET off. See (AST)
SMOD Operation diagram for additional details. This
function can be also be used for a pre-biased output The SiC780A has an internal adaptive logic to avoid
voltage. If SMOD is left unconnected, an internal pull up shoot through and optimize dead time. The shoot through
resistor will pull the pin up to VCIN (Logic High) to disable the protection ensures that both high-side and low-side
SMOD function. MOSFET are not turned on the same time. The adaptive
dead time control operates as follows. The HS and LS gate
Thermal Shutdown Warning (THDN) voltages are monitored to prevent the one turning on until
The THDN pin is an open drain signal that flags the presence the other's gate voltage is sufficiently low (1 V), that and built
of excessive junction temperature. Connect a maximum of in delays ensure the one power MOS is completely off,
20 kΩ to pull this pin up to VCIN. An internal temperature before the other can be turned on. This feature helps to
sensor detects the junction temperature. The temperature adjust dead time as gate transitions change with respect to
threshold is 160 °C. When this junction temperature is output current and temperature.
exceeded the THDN flag is set. When the junction
temperature drops below 135 °C the device will clear the

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Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive when the UVLO falling edge triggers the shutdown of
holding high-side and low-side MOSFET gate low until the the device. As an added precaution, a 20.2 kΩ resistor is
input voltage rail has reached a point at which the logic connected between GH and PHASE to provide a discharge
circuitry can be safely activated. The SiC780A also path for the HS MOSFET.
incorporates logic to clamp the gate drive signals to zero

FUNCTIONAL BLOCK DIAGRAM

Fig. 3 - SiC780 Functional Block Diagram

DEVICE TRUTH TABLE

DSBL# SMOD PWM GH GL
Open X X L L
L X X L L
H L L L L
H L H H L
H H H H L
H H L L H
H L Tri-state L L
H H Tri-state L L

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PWM TIMING DIAGRAM

Fig. 4 - Definition of PWM Logic and Tri-State

SMOD OPERATION DIAGRAM

PWM 0V

GH

IL
0A

GL

SMOD#

Fig. 5 - CCM Operation with SMOD# = HIGH

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SMOD OPERATION DIAGRAM

PWM 0V

GH

IL
0A

GL

10nS

SMOD#

Fig. 6 - DCM Operation with SMOD# = Active Toggle

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ELECTRICAL CHARACTERISTICS

VDRV/VCIN :2V/div VDRV/VCIN :2V/div

Vo:0.5V/div Vo:0.5V/div
VIN :5V/div VIN :5V/div

PWM:5V/div
PWM:5V/div

t:2ms/div
t:50ms/div

Startup with VIN Ramping Up Power Off with VIN Ramping Down
VIN = 12 V, VOUT = 1.2 V, FSW = 500 kHz, IOUT = 0 A VIN = 12 V, VOUT = 1.2 V, FSW = 500 kHz, IOUT = 1.2 A

Vo:0.5V/div
DSBL#:2V/div DSBL#:2V/div
VSWH:5V/div

Vo:0.5V/div

t:20us/div VSWH:5V/div

t:200us/div

Enable with VIN = 12 V, Disable with VIN = 12 V,

VOUT = 1.2 V, FSW = 500 kHz, IOUT = 1.2 A VOUT = 1.2 V, FSW = 500 kHz, IOUT = 1.2 A

VDRV/VCIN :5V/div VDRV/VCIN :5V/div

VIN :5V/div VIN :5V/div

Vo:0.5V/div

Vo:0.5V/div

PWM:5V/div
PWM:5V/div

t:20us/div t:100us/div

PWM Start with VIN = 12 V, PWM Turn-Off with VIN = 12 V,

VOUT = 1.2 V, FSW = 500 kHz, IOUT = 1.2 A VOUT = 1.2 V, FSW = 500 kHz, IOUT = 1.2 A

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ELECTRICAL CHARACTERISTICS

PWM:2V/div PWM:2V/div

GH:5V/div GH:5V/div

VSWH:5V/div VSWH:5V/div

GL:2V/div GL:2V/div

t:10ns/div
t:10ns/div

Switching Waveform at PWM Rising Edge Switching Waveform at PWM Falling Edge
VIN = 12 V, VOUT = 1.2 V, FSW = 500 kHz, IOUT = 0 A VIN = 12 V, VOUT = 1.2 V, FSW = 500 kHz, IOUT = 0 A

PWM:2V/div
PWM:2V/div

GH:5V/div

GH:5V/div

VSWH:5V/div

VSWH:5V/div

GL:2V/div GL:2V/div

t:10ns/div t:10ns/div

Switching Waveform at PWM Rising Edge Switching Waveform at PWM Falling Edge
VIN = 12 V, VOUT = 1.2 V, FSW = 500 kHz, IOUT = 30 A VIN = 12 V, VOUT = 1.2 V, FSW = 500 kHz, IOUT = 30 A

Typical Efficiency Typical Power Loss

VIN = 12 V, VOUT = 1.2 V, VDRV = VCIN; NO AIR FLOW, VIN = 12 V, VOUT = 1.2 V, VDRV = VCIN; NO AIR FLOW,
O/P Inductance = 0.33 μH O/P Inductance = 0.33 μH

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PACKAGE DIMENSIONS
K1
2x K2
5 6 A 0.08 C
D 0.10 C A
Pin 1 dot A A1 Pin #1 dent
0.41 D2-1
by marking A2
31 40
2x
30 1
0.10 C B

E2-2
MLP66-40

0.10 M C A B

(Nd-1)X e
(6 mm x 6 mm)

E2-1

ref.
E

E2-3
4
B 21 10

20 D2-3 D2-2 11
C
(Nd-1)X e
ref.

Top View Side View Bottom View

MILLIMETERS INCHES
DIM
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.029 0.031
A1 0 - 0.05 0 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.078 0.098 0.011
D 6.00 BSC 0.236 BSC
e 0.50 BSC 0.019 BSC
E 6.00 BSC 0.236 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 40 40
Nd (3) 10 10
Ne (3) 10 10
D2-1 1.45 1.50 1.55 0.057 0.059 0.061
D2-2 1.45 1.50 1.55 0.057 0.059 0.061
D2-3 2.35 2.40 2.45 0.095 0.094 0.096
E2-1 4.35 4.40 4.45 0.171 0.173 0.175
E2-2 1.95 2.00 2.05 0.076 0.078 0.080
E2-3 1.95 2.00 2.05 0.076 0.078 0.080
K1 0.73 BSC 0.028 BSC
K2 0.21 BSC 0.008 BSC
Notes
(1) Use millimeters as the primary measurement.
(2) Dimensioning and tolerances conform to ASME Y14.5M-1994.
(3) N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction.
(4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
(5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
(6) Exact shape and size of this feature is optional.
(7) Package warpage max. 0.08 mm.
(8) Applied only for terminals.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63788.

S14-1497-Rev. D, 04-Aug-14 12 Document Number: 63788

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PowerPAK® MLP66-40 Case Outline

2x K1
5 6 A 0.08 C
D 0.10 C A K2
Pin 1 dot A A1
0.41 D2-1
by marking A2
31 40
2x
30 1
0.10 C B

E2-2
MLP66-40

0.10 M C A B

(Nd-1)X e
(6 mm x 6 mm)

E2-1

ref.
E

E2-3
4
B 21 10

20 D2-3 D2-2 11
C
(Nd-1)X e
ref.

Top View Side View Bottom View

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.078 0.098 0.011
D 6.00 BSC 0.236 BSC
e 0.50 BSC 0.019 BSC
E 6.00 BSC 0.236 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 40 40
Nd (3) 10 10
Ne (3) 10 10
D2-1 1.45 1.50 1.55 0.057 0.059 0.061
D2-2 1.45 1.50 1.55 0.057 0.059 0.061
D2-3 2.35 2.40 2.45 0.095 0.094 0.096
E2-1 4.35 4.40 4.45 0.171 0.173 0.175
E2-2 1.95 2.00 2.05 0.076 0.078 0.080
E2-3 1.95 2.00 2.05 0.076 0.078 0.080
K1 0.73 BSC 0.028 BSC
K2 0.21 BSC 0.008 BSC
ECN: T14-0826-Rev. B, 12-Jan-15
DWG: 5986
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals

Revision: 12-Jan-15 1 Document Number: 64846

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Revision: 08-Feb-17 1 Document Number: 91000

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