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Tracing Coverage

1. Basic tracing involves adding constraints from the scan insertion script to the ATPG to address violations. Tracing or T3 errors may occur due to missing libraries. 2. The next stage involves setting the system mode to analysis to convert F violations to T3, T5, or K violations and then analyzing signal traces using a schematic viewer. 3. Coverage analysis involves black box analysis to identify missing modules, creating a no-fault list, setting sequential depth and pattern type parameters, and generating patterns to evaluate final coverage using reports. Advanced techniques involve test point insertion to address UC/UO coverage losses.

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Srinath M S
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786 views

Tracing Coverage

1. Basic tracing involves adding constraints from the scan insertion script to the ATPG to address violations. Tracing or T3 errors may occur due to missing libraries. 2. The next stage involves setting the system mode to analysis to convert F violations to T3, T5, or K violations and then analyzing signal traces using a schematic viewer. 3. Coverage analysis involves black box analysis to identify missing modules, creating a no-fault list, setting sequential depth and pattern type parameters, and generating patterns to evaluate final coverage using reports. Advanced techniques involve test point insertion to address UC/UO coverage losses.

Uploaded by

Srinath M S
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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/** Tracing**/

Basic:
Constraints as per the scan insertion script to be added to the atpg .
Tracing or T3 may come even due to balck box and missing libs

Next stage:

set_system mode analysis stage

If error are F Violations ->

set_edt_finder off
set_system_mode analysis

all F violations turns or get converted to T3/T5 or K violations.


then open vi click on the flop having issue check signals trace and analyse

add_primary_input top/kaushika/adc/o -pseudo clock_cutpoint_en


add_input_constraint clock_cutpoint_en -c1

/**COVERAGE ANALYSIS STEPS**/


BASIC:
1.BLACK BOX ANALYSIS : THIS GIVES HINT OF MISSING MODULES OR LIBARARIE WHICH WILL
IMPACT COVERAGE
2.NOFAULT LIST BASED ON SCAN FALSE ELEMENTS AS PER SCAN INSERTION AREA AND SCRIPTS:
(*occ*, *edt*, *mbist*,*tap*,*tdr*,*jtag*, analog modules ex adc ,*adc*)
if the coverage class of coverage loss AU.SEQ or AU.AAB abort limit, sequential
depth.
3.
set_sequential_depth 4
set_pattern_type -seq 5
set_abort_limit 100 50
create_patterns -auto
4. Final Coverage Methods

report_statistics -detailed_analysis (check all the fault classes where cov is


low ) au 10% (au.tc 5% au.seq 4%)
report_fault -class au.tc > au_tc_file
report_fault -class au.seq > au_seq_file
report_fault -class au > au_file
report_faults -class uc > uc_file
analyze_fault (path which is picked from au_tc_file or any filw for coverage loss)
-stuck_at 0/1
analyze_fault (path which is picked from au_tc_file or any filw for coverage loss)
-rise

to load some instance in schematic /visulaizer and see

add_display_instance path (flat)


or
add_display_instance path -dis hier (hierarchial)

advanced :
suppose cove UC/UO test point insertion -> combinational logics when UO UO coverage
loss at atpg

STeps:
see if cov loss at atpg due to UC or UO ( here write out the UC and UO fault list
paths )
during atpg analyse uc up and find out the main hierrachies where doing TPI on
these i=hierarchies maxim cov come
if so REdo scan insertion with test point insertion on these paths ?

new netlist with TPI then check coverage final coverage if loss due to UC UO'

AU.PC Pin constraint coverage loss of 5%.


we should remove the constraint from atpg dofile.
this constraine define as force 1 or 0 as per constraint in shift, load unload as
this value is constraint only dyuring shift or load unload and free for tool to
toggle during caoture we wull get coverage on this pin.
named capure procedures NCPs capture name given by user and define these values
pulse , force yav cycle

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