ACSP · Analog Circuits And Signal Processing

Yan Lu
Wing-Hung Ki

CMOS Integrated
Circuit Design for
Wireless Power
Transfer
Analog Circuits and Signal Processing

Series editors
Mohammed Ismail, Dublin, USA
Mohamad Sawan, Montreal, Canada
More information about this series at http://www.springer.com/series/7381
Yan Lu • Wing-Hung Ki

CMOS Integrated Circuit

Design for Wireless Power
Transfer
Yan Lu Wing-Hung Ki
University of Macau The Hong Kong University of Science and
Macao, China Technology
Hong Kong, China

ISSN 1872-082X ISSN 2197-1854 (electronic)

Analog Circuits and Signal Processing
ISBN 978-981-10-2614-0 ISBN 978-981-10-2615-7 (eBook)
DOI 10.1007/978-981-10-2615-7

Library of Congress Control Number: 2017945086

© Springer Nature Singapore Pte Ltd. 2018

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of
the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
or information storage and retrieval, electronic adaptation, computer software, or by similar or
dissimilar methodology now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt
from the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
authors or the editors give a warranty, express or implied, with respect to the material contained
herein or for any errors or omissions that may have been made. The publisher remains neutral with
regard to jurisdictional claims in published maps and institutional affiliations.

Printed on acid-free paper

This Springer imprint is published by Springer Nature

The registered company is Springer Nature Singapore Pte Ltd.
The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721,
Singapore
Preface

CMOS integrated circuit design for wireless power transfer intends to report the
state-of-the-art analog and power management IC design techniques for various
wireless power transfer (WPT) systems. To propose elaborate power management
solutions, the circuit designers are required to have in-depth understanding on the
characteristics of each type of converters and regulators in the power chain. This
book addresses the design issues of WPT at both the system level and the circuit
level and serves as a handbook with design hints for research students and engineers
in analog integrated circuit design, integrated power electronics, and wireless
power transfer system design.
Our research has been focusing on fully integrated power management inte-
grated circuits design that aims at miniaturizing the devices by proposing novel
circuit topologies and system architectures. Since the passive components (induc-
tors and capacitors) occupy most of the chip and board area, reducing their values
and numbers and reusing them are the keys to minimizing the volume of the
portable/wearable/implantable devices. Reducing the supply noise also provides
more design margin for the functional loading circuits, and increasing the power
conversion efficiency can maximize the available energy and prolong the device
operation time on a single charge of the battery.
Besides discussing the power management solutions for biomedical implantable
systems, we also touch upon the topics of wireless charging for portable and
wearable devices, wireless powering for storage devices, and RF energy harvesting
for internet-of-things (IoT). New regulation methods and state-of-the-art converter
architectures at both the system level and the circuit level are briefed. Our work
focuses on the CMOS integrated circuit design of wireless power transfer systems

v
vi Preface

and active circuits that effectively convert the power between the AC and DC
domains. Voltage regulation at both the system level and the circuit level would
also be addressed. We hope our work could help electronic engineers and students
in designing high-quality power supplies for the wirelessly powered devices.

Macao, China Yan Lu

Hong Kong, China Wing-Hung Ki
April 2017
Contents

1 Introduction of Wireless Power Transfer . . . . . . . . . . . . . . . . . . . . . 1

1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Operation Principles, Regulations, and Standards . . . . . . . . . . . . . 2
1.2.1 Near-Field and Far-Field Operation . . . . . . . . . . . . . . . . . 3
1.2.2 Ultrasound Wireless Power Transfer . . . . . . . . . . . . . . . . . 5
1.2.3 Inductive and Resonant WPT . . . . . . . . . . . . . . . . . . . . . . 6
1.2.4 Wireless Charging Standards . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Design Perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Comparison of Wired and Wireless Power . . . . . . . . . . . . 7
1.3.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Organization of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Wireless Power Transfer Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Output Voltage Regulation Schemes . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Primary Side Non-linear Power Control . . . . . . . . . . . . . . 16
2.2.2 Reconfigurable Rectifier for Adaptive Output . . . . . . . . . . 19
2.2.3 Resonant Regulating Rectifier . . . . . . . . . . . . . . . . . . . . . 21
2.2.4 Reconfigurable Resonant Regulating Rectifiers . . . . . . . . . 23
2.2.5 Pre-rectifier Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.6 Multi-Level Single-Inductor Multiple Output
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Analysis of Coupled-Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 Coupled-Coils and Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.1 Ideal Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.2 Ideal Coupled-Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

vii
viii Contents

3.2.3 T-Model of Coupled-Coils . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2.4 Transformer Model of Coupled-Coils . . . . . . . . . . . . . . . . 36
3.2.5 Reflected Impedance Model of Coupled-Coils . . . . . . . . . . 37
3.2.6 Link Voltage Gain and Link Efficiency . . . . . . . . . . . . . . . 38
3.2.7 Computing A and η of the Ideal Coupled-Coils . . . . . . . . . 39
3.2.8 Design-Oriented Analysis of Coupled-Coils
with Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Resonant Coupled-Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1 Series-Series Resonant Coupled-Coils . . . . . . . . . . . . . . . 44
3.3.2 Series-Parallel Resonant Coupled-Coils . . . . . . . . . . . . . . 47
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4 Circuit Design of CMOS Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 Diodes and Diode-Connected Transistors . . . . . . . . . . . . . . . . . . . 55
4.3 Comparator-Based Active Rectifiers . . . . . . . . . . . . . . . . . . . . . . 59
4.3.1 Delay Compensation Schemes . . . . . . . . . . . . . . . . . . . . . 61
4.3.2 Delay Time Analysis of Active Diodes . . . . . . . . . . . . . . . 67
4.3.3 Biasing Circuits of Active Rectifiers . . . . . . . . . . . . . . . . . 70
4.3.4 Full-Wave Rectifier Design Examples . . . . . . . . . . . . . . . 72
4.3.5 Reconfigurable Rectifier Design Example . . . . . . . . . . . . . 83
4.4 DLL-Based Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.5 Rectifiers for RF Energy Harvesting . . . . . . . . . . . . . . . . . . . . . . 89
4.6 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5 Linear Regulators for WPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2 PMOS and NMOS LDO Regulators . . . . . . . . . . . . . . . . . . . . . . 99
5.3 Control Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.3.1 Dominant Pole Considerations . . . . . . . . . . . . . . . . . . . . . 101
5.3.2 Replica Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.3 Flipped Voltage Follower . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.4 Impedance Attenuation Buffer . . . . . . . . . . . . . . . . . . . . . 105
5.3.5 Digitally Controlled LDO Regulator . . . . . . . . . . . . . . . . . 105
5.4 Design Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.4.1 Design of Tri-Loop LDO Regulator . . . . . . . . . . . . . . . . . 106
5.4.2 LDO Regulator with Enhanced Super Source
Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.5 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6 DC-DC Converters for WPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.2 DC-DC Converter Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . 128
Contents ix

6.3 Control Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6.3.1 Loop Design for Inductor-Based Converters . . . . . . . . . . . 130
6.3.2 Loop Design for SC DC-DC Converters . . . . . . . . . . . . . . 132
6.4 Architectures of DC-DC Conversion . . . . . . . . . . . . . . . . . . . . . . 136
6.4.1 Multiple-Output Converters . . . . . . . . . . . . . . . . . . . . . . . 136
6.4.2 Layout Strategy for Efficient Power Delivery . . . . . . . . . . 136
6.4.3 Cascade Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . 138
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7 Power Amplifiers for WPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.1.1 Integration Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.1.2 Losses in Switching PAs . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.1.3 Zero Voltage (Current) Switching . . . . . . . . . . . . . . . . . . 147
7.2 Class-D PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.2.1 Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.2.2 ZVS Class-D PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.3 Class-E PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.4 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
8 Conclusions and Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
8.1 Concluding Remarks of the Book . . . . . . . . . . . . . . . . . . . . . . . . 159
8.2 Suggested Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Chapter 1
Introduction of Wireless Power Transfer

Abstract Wireless power transfer (WPT) for a broad range of applications is

projected to have an exponential growth, with an enormous number of new devices
and products to be enabled by this powerful technology. In this chapter, the
background and motivations of WPT are introduced first. Then high-level consid-
erations on WPT such as operation frequencies, WPT regulations and WPT stan-
dards are reviewed and summarized. In addition, design perspectives on the WPT
circuits and systems are also examined. Finally, we present the organization of this
book and provide some reading guidelines.

Keywords Wireless power transfer • Inductive coupling • Wireless charging •

Near field • Far field • Ultrasound • Optimum coupling distance

1.1 Motivations

Wireless power transfer (WPT) has a wide range of applications including

(arranged from low to high power levels) radio frequency identification (RFID),
internet-of-things (IoT), implantable medical devices (IMDs), real-time wireless
power for non-contact memory devices and wafer-level testing, and also wireless
chargers for portable/wearable devices and electric vehicles (EVs). It is evident that
the utilization of WPT technologies is on the verge of exponential growth.
Design considerations for WPT at different power levels are quite different, and
are discussed as follows. In the extreme low-power cases, IMDs [1–3] such as the
pacemaker, cochlear implant, retinal prosthesis, neural recording microsystem, etc.
only consumes a power level of milli-Watt or even lower. The form factor of the
IMD power receiver is one of the most important concerns because it has to be as
non-invasive as possible. For IMDs with a single channel or a few channels such as
the pacemaker and the cochlear implant, a power level of micro-Watt would be
sufficient [1]. For retinal prosthesis and neural signal recording, on the other hand,
hundreds or thousands of channels are needed [2, 3], as simulations suggest that, for
example, 600–1000 pixels will be required to provide visual function such as face
recognition and reading [2]. In such a case, the power level would be in the milli-
Watt range, and fully on-chip integration is preferred such that no discrete compo-
nent is needed, and the complete system could occupy just a few cubic millimeters.

© Springer Nature Singapore Pte Ltd. 2018 1

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_1
2 1 Introduction of Wireless Power Transfer

High efficiency is of utmost importance, such that only little power is lost and being
absorbed by the tissue that would cause potential damage.
In the high-power regime such as charging up automotive battery systems for
EVs, discrete high-voltage diodes and transistors are used to handle the power in the
Kilo-Watt range. In between IMD powering and EV charging, wireless charging for
portable/wearable devices is in the range of a few Watts. For consumer electronics,
small size and compact packaging are preferred. The power level of a typical
wireless mobile phone charger is around 5 W, and the rectifier is preferably
integrated on-chip to avoid using discrete Schottky diodes or III-V transistors and
to reduce the cost.
As mentioned above, one potential application of WPT is the contact-less
memory [4–7]. There are a few advantages to equip memory cards with wireless
data and wireless power transfer functions. First, by using WPT to power up the
card, the metal pads in conventional memory cards can be removed, and data
transmission rate can be enhanced, as the electrostatic discharge (ESD) protection
circuits that introduce additional capacitive loads to the I/O can be removed.
Second, for a contact-less memory card, there will be no wear and tear of the
card due to repeated plugging and unplugging. Third, the fully sealed packaging
enables the device to be waterproof, and more importantly, it dramatically extends
the memory lifetime by isolating the chip from moisture and oxygen [4].
Therefore, wireless power transfer is not just about getting rid of wires. It helps
many technologies and applications to become possible. For example, unmanned
battery-powered aircrafts (drones) can be recharged in mid-air to extend their
limited navigation distance; and portable devices can have waterproof packaging
with no electrical connectors.

1.2 Operation Principles, Regulations, and Standards

One major concern on wireless power transfer is the health issue. Radiation can be
classified into ionizing and non-ionizing radiation, depending on the energy of the
radiating particles. Ionizing radiation has energy high enough to ionize atoms and
molecules and break chemical bonds; while non-ionizing radiation only generates
heat. This is an important distinction that differentiates if the radiation is harmful to
living subjects. Ionizing radiations such as Gamma rays (from radioactive decay of
atomic nuclei), X-rays (used in medical imaging and security check) and the higher
energy range of ultraviolet light (exists in the sunlight) constitute the ionizing part
of the electromagnetic spectrum. While visible light, infrared light, microwaves and
radio waves have lower energy and longer wavelength, and are non-ionizing.
Research showed that the adverse effects due to RF exposure are basically related
to the thermal aspects [8].
As summarized in [8], an extensive literature review on RF biological effects
that consists of over a thousand primary peer-reviewed publications reveals
no adverse health effects that are not thermally related. Behavioral studies on
animal subjects indicate that disruption of behavior is usually (not always)
1.2 Operation Principles, Regulations, and Standards 3

Fig. 1.1 Maximum permissible exposure for the general public versus the ISM frequency bands

accompanied by a core body temperature increase of ~1.0
C; and a body temper-

ature increase of 2–2.5
C will cause significant heat-induced abnormalities, which
mostly occur after RF exposures for tens of minutes or one hour. Therefore, basic
restrictions (BRs) on the whole-body-average for frequencies between 100 kHz and
3 GHz is 0.4 W/kg with a traditional safety factor of ten, and the localized exposure
BRs is 4 W/kg averaged over any 10 g of tissue of which the volume is approxi-
mately 10 cm3. The maximum permissible exposure (MPE) versus the ISM (indus-
trial, scientific, medical) frequency bands are shown in Fig. 1.1. Measurement
results show that the human tissue specific absorption rate (SAR) increases as the
frequency increases [9]. Meanwhile, pulsed waveforms with low duty-cycle can be
employed for EM wave transmission to reduce the heat produced, because the
heating capability of electric current is proportional to the square root of the duty-
cycle [8].

1.2.1 Near-Field and Far-Field Operation

Electromagnetic (EM) WPT systems can basically be divided into two categories
according to the transmission modes of near-field and far-field operations. As
shown in Fig. 1.2a, near-field operation assumes that the transmission distance
d is much shorter than the wavelength λ, that is, d << λ. In the near-field case, both
4 1 Introduction of Wireless Power Transfer

Fig. 1.2 Block diagrams of near-field and far-field wireless power transfer systems

the transmitting and receiving devices are coils, and the energy transfer medium is
magnetic flux only. On the other hand, as shown in Fig. 1.2b, for far-field operation,
the wavelength is much shorter than the transmission distance, that is, λ << d, and
the energy transfer devices are antennas that deal with EM waves.
For near-field operation, the optimum transmission distance xOPT is related to the
radius R of the transmitting coil. A rule-of-thumb optimum distance is suggested in
[10] as
pffiffiffi
xOPT  R= 2, ð1:1Þ

As shown in the conceptual diagram of Fig. 1.3, if the transmitting coil is too
large, the field strength becomes very weak, even at a distance of x ¼ 0. On the
other hand, if the coil is too small, the magnetic field strength drops at a fast rate that
is inversely proportional to x3. Therefore, the size of the transmitting coil should be
designed according to the targeted distance.
For far-field operation, it is quite difficult to focus the transmitted energy to a
targeted location. Hence, antenna array technologies may be used for direction
control of the transmitted power and consequently achieve higher receiver and
system efficiencies [11, 12]. Equation (1.2) shows the simplified formula for the
path loss APATH in free space between two isotropic transmitting and receiving
antennas:
 
4πd
APATH ¼ 20log , ð1:2Þ
λ

The path loss is inversely proportional to the wavelength, and therefore it is

proportional to the frequency. To reduce path loss, lower frequency bands are
conventionally used for long distance RF transmission. However, there is another
aspect of consideration. By increasing the transmission frequency by ten times, the
values of both the inductor and the capacitor can be reduced by ten times, because
the resonant frequency FRES is given by
1.2 Operation Principles, Regulations, and Standards 5

Fig. 1.3 Conceptual diagram of the relationship between the coil diameter and the optimum
coupling distance

1
FRES ¼ pffiffiffiffiffiffi ð1:3Þ
2π LC

Hence, high-frequency wireless power transfer could reduce the volume of the
LC resonant tank of near-field operation or the volume of the antenna of far-field
operation. The value of the output filtering capacitor can also be reduced, such that
the entire WPT receiver could be integrated on-chip or on-package. Besides,
smaller inductance with higher Q can be more easily achieved at higher frequencies
within a limited space, which is one of the key factors in improving the overall
efficiency of the wireless power transfer systems. For near-field operation, the
readily available ISM frequency 13.56 MHz is commonly used for implantable
medical devices (IMDs) [13–15]. Although the SAR of tissue increases with
frequency in the range of tens to hundreds of MHz, the human tissue SAR for
13.56 MHz is still quite low compared to the thermal power dissipation in the coils
[16]. Alternatively, when larger wireless power levels are required, frequencies
such as 100–200 kHz and 6.78 MHz are widely adopted for wireless charging [17–
19].

1.2.2 Ultrasound Wireless Power Transfer

Ultrasound with a frequency of 20 kHz or above is also a good candidate for

wireless power transfer. The advantage of acoustic waves is that the propagation
6 1 Introduction of Wireless Power Transfer

loss in water is much lower than that of electromagnetic (EM) waves [20]. More-
over, the relatively low operating frequency compared to the EM waves makes it
easier to achieve higher power conversion efficiency for the power converters used.
For safe wireless power transmission in tissue, ultrasound of high power density is
allowed, for example, an ultrasonic intensity of 100 mW/cm2 would generate little
or no hazard for the duration of at least two hours [21]. Nevertheless, the power
level of ultrasound should still be limited, as it causes much distress to animals that
are sensitive to higher frequencies than humans [22].

1.2.3 Inductive and Resonant WPT

It is easy to be confused with the two marketing terms: inductive power transfer
(IPT) and resonant WPT (R-WPT). Aren’t all the EM WPT systems both inductive
and resonant? (This is similar to the question: isn’t all food organic?) Yes, both IPT
and R-WPT utilize the magnetic field and the resonant circuits. The difference is in
the operating mechanism of the WPT transmitter.
A wireless power transfer system can be considered as tightly or loosely coupled
by the values of the coupling coefficient k and the distance d of the coils. When the
two coils are of similar sizes and are placed very closely together, they are tightly
coupled. A higher k improves the WPT efficiency, and consequently reduces the
losses and heat. In a tightly coupled system, the transmission frequency is designed
to be slightly different from the resonant frequency of the receiver for output power
control, and a high efficiency can still be maintained [23]. For a loosely coupled
system, the transmission frequency is well-tuned at the receiver resonant frequency
to induce sufficient power and to achieve a better efficiency at extended distance,
for example, a few times of the diameter of the transmitter coil. The secondary coil
is designed to have a very high quality factor Q, and efficient power transfer can be
achieved if the transmission frequency is exactly the same as the resonant frequency
of the receiver. However, resonant excitation is sensitive to component variations,
and hence additional resonant tuning circuits may have to be implemented.

1.2.4 Wireless Charging Standards

Wireless charging usually makes use of the frequency bands in the range of
100 kHz to 10 MHz. There are currently two main standards in the market. One
is the Qi (pronounced “Chee”, derived from the Chinese word meaning “life
energy”) standard developed by the Wireless Power Consortium (WPC). The
other one is the AirFuel Alliance which is formed from merging the Alliance for
Wireless Power (A4WP) and the Power Matters Alliance (PMA). Both standards
1.3 Design Perspectives 7

are targeting at 5 W for smartphone charging and 15 W for fast charging and laptop
charging.
At the early phase of the consortium/alliance, WPC only supported inductive
power transfer, and A4WP only supported resonant WPT. However, to cater for a
larger market, the two standards are now supporting both operating modes. There
are three main differences between these two mainstream standards. First, the Qi
devices operate with a frequency range of 87–205 kHz, while the AirFuel devices
operate at an ISM band of 6.78 MHz  15 kHz. Second, Qi employs a multi-coil
transmitter structure or magnet-core auto-alignment for horizontal freedom and
electromagnetic interference (EMI)/electromotive force (EMF) reduction, while
AirFuel only uses a larger transmitter coil for three-dimensional (3D) freedom.
Third, Qi uses load modulation (also known as back-scattering) for data commu-
nication between the WPT receiver and transmitter; while AirFuel uses the
Bluetooth module for data communication and power control.
Besides the above relatively mature near-field standards, there is one more
emerging wireless charging technology that uses the WiFi frequency bands (2.45
or 5.8 GHz) for longer WPT distance (within a range of 10 m) and total spatial
freedom with transmission power of 1 W [24]. This technology is attractive
especially for office-room and in-car applications. To achieve effective power
transmission, a complex and costly phased array of antenna is required to precisely
send power to the device-under-charging with multiple energy beams. This tech-
nology is also included in the uncoupled power transfer family of the AirFuel
Alliance.

1.3 Design Perspectives

1.3.1 Comparison of Wired and Wireless Power

In the circuit designer’s perspective, as shown in Fig. 1.4, wired power is “verti-
cally” provided to the functional circuits from the power supply to ground that is
“orthogonal” to the signal lines. In such a case, the power-management circuit
designers may treat the signal processing circuits as a black box, and the analog and
mixed-signal circuit designers similarly may treat the power supply circuits as a
black box. On the other hand, wireless power is “horizontally” transmitted from the
energy source to the end-users. In other words, it is “in parallel” with the wireless
signal paths. Now, a circuit designer needs to know both power processing and
signal processing in order to design an efficient wireless power transfer system. In
addition, knowledge of coil design and EM wave analysis is definitely helpful. In
fact, in many cases both the wireless power link and the data telemetry link are
designed by the same circuit designer. This imposes design challenges to both the
circuit and the system designers.
8 1 Introduction of Wireless Power Transfer

Fig. 1.4 A conceptual diagram showing systems with wired power and wireless power

1.3.2 System Overview

Figure 1.5 shows a typical integrated wireless power transfer system with a power
link, a data up-link and a data down-link. The transmitter (TX) chip consists of a
DC-DC converter that supplies power to the power amplifier (PA) driving the
primary resonator, a load-current detection block that sends information to the
microprocessor for output power control, and a data TX for sending information
to the receiver (RX) chip. The RX chip consists of a rectifier that converts the AC
power into a DC power reservoir, a DC-DC converter that regulates the output
voltage or current to the load, a microcontroller that commands data communica-
tion, and protection circuits that prevent over-temperature, over-voltage and over-
current conditions. Output power control can be realized by supply modulation of
the PA [25].
As mentioned in Sect. 1.2.1, increasing the transmission frequency could sig-
nificantly reduce the values and thus the volume of passive components. Obviously,
higher frequency operation enables full integration of a WPT system to within a few
cubic millimeters [26–28]. One additional advantage of increasing the WPT fre-
quency is that the data coil/antenna may be removed by transmitting up-link and
down-link data using the same power link in a time-multiplexing fashion.
To sum up, for different WPT applications, the engineers need to consider the
tradeoffs among various parameters such as transmission frequency, process tech-
nology, resonator topology, output regulation method etc. that makes the design
very challenging. In addition, considerations for different power levels are quite
different. Techniques and topologies that can increase the link efficiency and
reduce the device volume are highly desirable. We believe that there are plenty
of research opportunities in this area, and we believe consumers would enjoy a
smart living environment with minimum wires dangling around.

1.4 Organization of the Book

This book focuses on the circuit and system designs of wireless power transfer for
portable and medical devices. The organization of the materials is as follows.
1.4 Organization of the Book 9

Fig. 1.5 Block diagram of a generic inductive power link with up and down data links

Chapter 1 introduces WPT applications, standards, and some high-level

considerations.
Chapter 2 reviews the state-of-the-art WPT systems with the emphasis on
reducing the device volume. In recent years, many system architectures have
been proposed by various research groups with improved efficiency, reduced
number of components and enhanced functionalities.
Chapter 3 analyzes the coil coupling characteristics, and provides design guide-
lines for optimizing the wireless power link.
Chapter 4 gives a detailed review on CMOS rectifiers for both near-field and
far-field operations that enable high-efficiency full-chip integration. Active recti-
fiers with different delay compensation schemes are introduced and compared with
design examples. CMOS rectifier designs for RF energy harvesting are discussed
as well.
Chapter 5 discusses the design guidelines for linear regulators, which are the
most widely adopted voltage regulation method on-chip, due to its simple structure
and area-efficient and noise-reduced characteristics. Fast local control loops can be
easily achieved for linear regulators, without affecting the global loop of wireless
power transfer system. Two fully-integrated design examples are presented to
verify the design suggestions.
Chapter 6 presents the design considerations on switching DC-DC converters
which can be classified as switched-inductor and switched-capacitor converters.
Converter architectures and control-loop designs for both types are introduced.
Chapter 7 compares the two most popular power amplifiers (Class-D and Class-
E) for wireless power transmitters. Essential knowledge of power devices and
power electronics for switching loss reduction is also revisited.
Chapter 8 concludes the topic with suggestions on future directions.
10 1 Introduction of Wireless Power Transfer

References

1. Wise KD, Anderson DJ, Hetke JF, Kipke DR, Najafi K (2004) Wireless implantable
microsystems: high-density electronic interfaces to the nervous system. Proc IEEE
92:76–97. doi:10.1109/JPROC.2003.820544
2. Weiland JD, Liu W, Humayun MS (2005) Retinal prosthesis. Annu Rev Biomed Eng
7:361–401. doi:10.1146/annurev.bioeng.7.060804.100435
3. Gosselin B (2011) Recent advances in neural recording microsystems. Sensors 11:4572–4597.
doi:10.3390/s110504572
4. Lee H-M, Ghovanloo M (2012) An adaptive reconfigurable active voltage doubler/rectifier
for extended-range inductive power transmission. IEEE Trans Circuit Sys II Exp Briefs
59:481–485. doi:10.1109/TCSII.2012.2204840
5. Radecki A, Chung H, Yoshida Y, Miura N, Shidei T, Ishikuro H, Kuroda T (2011) 6W/25mm2
inductive power transfer for non-contact wafer-level testing. In: IEEE international solid-state
circuits conference digest of technical papers (ISSCC), pp 230–232. doi:10.1109/ISSCC.2011.
5746297
6. Chung H, Radecki A, Miura N, Ishikuro H, Kuroda T (2012) A 0.025–0.45 W 60%-efficiency
inductive-coupling power transceiver with 5-bit dual-frequency feedforward control for
non-contact memory cards. IEEE J Solid State Circ 47:2496–2504. doi:10.1109/JSSC.2012.
2206686
7. Lu Y, Huang M, Cheng L, Ki WH, SP U, Martins RP (2017) A dual-output wireless power
transfer system with active rectifier and 3-level operation. IEEE Trans Power Electron
32:927–930. doi:10.1109/TPEL.2016.2601623
8. (2006) IEEE standard for safety levels with respect to human exposure to radio frequency
electromagnetic fields, 3 kHz to 300 GHz. IEEE Std C951–2005 (Revision of IEEE Std
C951–1991) 1–238. doi:10.1109/IEEESTD.2006.99501
9. Gabriel S, Lau RW, Gabriel C (1996) The dielectric properties of biological tissues:
II. Measurements in the frequency range 10 Hz to 20 GHz. Phys Med Biol 41:2251. doi:10.
1088/0031-9155/41/11/002
10. Finkenzeller K (2010) RFID handbook: fundamentals and applications in contactless smart
cards, radio frequency identification and near-field communication, 3rd edn. Wiley, Hoboken
11. Merlin R (2007) Radiationless electromagnetic interference: evanescent-field lenses and
perfect focusing. Science 317:927–929. doi:10.1126/science.1143884
12. Kim S, Ho JS, Poon ASY (2013) Midfield wireless powering of subwavelength autonomous
devices. Phys Rev Lett 110:203905. doi:10.1103/PhysRevLett.110.203905
13. Lu Y, Ki W-H (2014) A 13.56 MHz CMOS active rectifier with switched-offset and compen-
sated biasing for biomedical wireless power transfer systems. IEEE Transac Biomed Circuits
Syst 8:334–344. doi:10.1109/TBCAS.2013.2270177
14. Lee H-M, Ghovanloo M (2012) An adaptive reconfigurable active voltage doubler/rectifier for
extended-range inductive power transmission. IEEE Transac Circuits Sys II Exp Briefs
59:481–485. doi:10.1109/TCSII.2012.2204840
15. Lu Y, Li X, Ki W-H, Tsui C-Y, Yue CP (2013) A 13.56MHz fully integrated 1X/2X active
rectifier with compensated bias current for inductively powered devices. In: IEEE international
solid-state circuits conference digest of technical papers (ISSCC), pp 66–67. doi:10.1109/
ISSCC.2013.6487639
16. Jow UM, Ghovanloo M (2010) Optimization of data coils in a multiband wireless link for
neuroprosthetic implantable devices. IEEE Transac Biomed Circuits Syst 4:301–310. doi:10.
1109/TBCAS.2010.2049491
17. Lidow A, de Rooij M (2014, May) Performance evaluation of enhancement-mode GaN
transistors in Class-D and Class-E wireless power transfer systems. Bodo Mag:56–60
18. Riehl PS, Satyamoorthy A, Akram H et al (2015) Wireless power systems for mobile devices
supporting inductive and resonant operating modes. IEEE Transac Microwave Theory Tech
63:780–790. doi:10.1109/TMTT.2015.2398413
References 11

19. Hwang JT, Lee DS, Lee JH et al (2016) An all-in-one (Qi, PMA and A4WP) 2.5W fully
integrated wireless battery charger IC for wearable applications. In: IEEE international solid-
state circuits conference digest of technical papers (ISSCC), pp 378–380
20. Meng M, Kiani M (2016) Design and optimization of ultrasonic wireless power transmission
links for millimeter-sized biomedical implants. IEEE Transac Biomed Circuits Syst:1–10.
doi:10.1109/TBCAS.2016.2583783
21. Ulrich WD (1974) Ultrasound dosage for nontherapeutic use on human beings – extrapolations
from a literature survey. IEEE Trans Biomed Eng BME-21:48–51. doi:10.1109/TBME.1974.
324362
22. van Schuylenbergh K, Puers R (2009) Inductive powering. Springer, Dordrecht
23. Magnetic resonance and magnetic induction – what is the best choice for my application?
https://www.wirelesspowerconsortium.com/data/downloadables/1/2/4/6/magnetic-resonance-
or-magnetic-induction.pdf. Accessed 19 Oct 2016
24. Branscombe M (2013) Wireless power: could Cota make it long-distance and mainstream?
http://www.qiwireless.com/wireless-power-cota-make-long-distance-mainstream. Accessed
19 Oct 2016
25. Li X, Lu Y, Tsui C-Y, Ki W-H (2014) An adaptive wireless powering and data telemetry
system for optic nerve stimulation. In: 2014 I.E. international symposium on circuits and
systems (ISCAS), pp 1404–1407. doi:10.1109/ISCAS.2014.6865407
26. O’Driscoll S, Poon ASY, Meng TH (2009) A mm-sized implantable power receiver with
adaptive link compensation. In: IEEE international solid-state circuits conference digest of
technical papers (ISSCC), pp 294–295. doi:10.1109/ISSCC.2009.4977424
27. Raju S, Li X, Lu Y et al (2014) Efficient wireless power transmission technology based on
above-CMOS integrated (ACI) high quality inductors. In: IEEE international electron devices
meeting (IEDM), pp 12.4.1–12.4.4. doi:10.1109/IEDM.2014.7047038
28. Zargham M, Gulak PG (2015) Fully integrated in-chip coil in 0.13 CMOS for wireless power
transfer through biological media. IEEE Transac Biomed Circuits Syst 9:259–271. doi:10.
1109/TBCAS.2014.2328318
Chapter 2
Wireless Power Transfer Systems

Abstract This chapter discusses wireless power transfer (WPT) at the system
level, with detailed analyses on state-of-the-art WPT output voltage regulation
topologies. Possible combinations of the WPT building block configurations are
investigated, compared and summarized. Several novel architectures for efficient
WPT were proposed in recent years to reduce the number of passive components as
well as to improve the system efficiency or flexibility, and these schemes are
reviewed and discussed in this chapter.

Keywords Wireless power transfer • Voltage regulation • Inductive power

transfer • DC-DC converter • Power amplifier • Rectifier • Coupled coils

2.1 Introduction

A WPT system contains nearly all kinds of power converters, including a DC-AC
converter (inverter, serving as a non-linear power amplifier), a transformer (tightly
or loosely coupled WPT coils), an AC-DC converter (rectifier), a DC-DC converter
and/or a linear regulator. A generic WPT system including most of the building
block combinations is shown in Fig. 2.1.
The WPT system consists of a power transmitter (TX) and a power receiver
(RX) for transferring power through an inductive power link; a data down-link for
sending commands from the primary side to the secondary side; and a data up-link
for transferring data from the secondary side to the primary side, for output voltage
regulation, for example. The power amplifier (PA) drives the primary series or
parallel L1C1 resonator, and the secondary series or parallel L2C2 resonator receives
the wireless power, and then feeds the AC power to the rectifier. The traditional
rectifier is a passive diode-bridge that drives a large filtering capacitor, producing
an unregulated DC voltage with substantial output voltage ripples. The rectifier is
usually cascaded with a voltage regulator such as a linear series/shunt regulator
and/or a DC-DC converter. The linear regulator can only provide an output voltage
that is lower than the peak voltage of the rectifier, because its output voltage is
controlled by tuning the on-resistance of the power transistor. On the other hand, a
DC-DC converter consists of energy-storing components (inductors and/or capac-
itors) and switches may step-up or step-down its output voltage. One should be

© Springer Nature Singapore Pte Ltd. 2018 13

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_2
14 2 Wireless Power Transfer Systems

Fig. 2.1 Block diagram of a generic inductive wireless power transfer system

aware that the passive components of the DC-DC converter occupy considerable
chip and/or printed circuit board (PCB) area. Moreover, the switching operation of
a DC-DC converter generates large output voltage ripples and ground noises.
Design considerations and tradeoffs of each building block will be introduced in
details in subsequent chapters.
At the receiver side, voltage regulation can be done locally using a linear
regulator or a DC-DC converter as discussed above, or globally by adjusting the
power from the transmitter side. One global voltage regulation scheme is to feed the
digitized rectifier output voltage back to the primary side through load modulation
(backscattering, for example) or out-band RF communication (Bluetooth, for
example). When the digitized rectifier output voltage is read and decoded by the
power control unit (PCU) on the primary side, the PCU will then change the PA
output power accordingly. If a Class-D PA is used, the duty ratio will be adjusted; or
if a Class-E PA is used, the power supply voltage will be adjusted through a DC-DC
switching converter.
The total power conversion efficiency ηTOTAL of a WPT link is the product of the
efficiencies of each stage, as given by

ηTOTAL ¼ ηDC-DC  ηPA  ηLINK  ηRECT  ηREG ð2:1Þ

where ηDC-DC and ηPA are the efficiencies of the DC-DC converter and the PA on
the TX side, ηLINK is the efficiency of the coupling link, and ηRECT and ηREG are the
efficiencies of the rectifier and the regulators on the RX side, respectively. The
global voltage regulation loop consists of a few power processing blocks, and is
slow compared to the RX local voltage regulation loop, but global power control is
essential as it has a major impact on the efficiency of the whole system. It is because
when the received power is more than that demanded by the load the excessive
power will be consumed by the linear regulator or other over-voltage protection
circuits. In such a case, ηREG will be very low. Let each stage achieves a reasonably
2.2 Output Voltage Regulation Schemes 15

good efficiency of 90%, then the total efficiency is only 59%, which cannot be
considered as high. Nevertheless, it would still be beneficial if the efficiency of one
certain stage is increased by 2%, and ηTOTAL can then be increased by 1.18%. Thus,
efficiency optimization for each stage is important.
As depicted in Fig. 2.1, the inductive coupling coils on both the primary inductor
and the secondary inductor can be connected either in series or in parallel with the
resonance capacitor. Thus, there are four types of resonance combinations for the
inductive power link: series-to-series, series-to-parallel, parallel-to-series, and par-
allel-to-parallel. The selection of resonance type for high system efficiency depends
on the load current level and the coupling coefficient that would affect the reflected
equivalent secondary impedance on the primary side of the WPT system [1–
3]. Detailed analyses of the coupled coils will be given in Chap. 3.
The load of a WPT system could be mixed-signal/digital circuits that are
commonly modeled as a resistor in parallel with a filtering capacitor, or analog
circuits or neuron stimulation electrodes that can be modeled as a current source, or
a rechargeable battery that is similar to a super capacitor. The regulator design and
the system design should fully take the load characteristics into consideration, and a
specific regulation circuit should be designed for a specific load [4, 5]. Sometimes a
high output voltage (say >10 V) is needed for a specific application, for example,
the neuron stimulation of a biomedical implant or the flash memory write operation
of a wirelessly powered data storage device. A large winding ratio between L1 and
L2 can be used to boost up the RX output voltage, eliminating one additional step-
up DC-DC converter in the RX side.

2.2 Output Voltage Regulation Schemes

The load on the secondary side is driven by a well-regulated voltage source or

current source. One simple scheme is as follows: the PA of the TX side always
transmits its maximum power, while the output of the rectifier is regulated by a
shunt regulator (such as a zener diode) to bypass the excessive power to ground.
Alternatively, a DC-DC converter or a linear regulator could be cascaded to the
rectifier stage to provide an accurately regulated output voltage [6–9]. In many
cases, multiple supply voltages are needed for different load circuits, for example,
0.5–1 V for low-power digital signal processing circuits, 1.2–1.8 V for analog
circuits, and 10–20 V for neuron stimulation or memory writing. Therefore,
multiple-output topologies have to be studied for the WPT systems. With the PA
always transmitting at the maximum power, the system efficiency is low when the
power demanded by the load is low. If a global voltage regulation scheme is
installed, the up-link data through load-modulation could be back-scattered to the
primary side to adjust the PA output power.
An example of a typical inductive power link for implantable medical devices is
shown in Fig. 2.2. For the RX chip, a shunt regulator provides coarse voltage
regulation and over-voltage protection, and a series-type low-dropout (LDO) reg-
ulator provides essential fine voltage regulation for the load circuits. The data
16 2 Wireless Power Transfer Systems

Fig. 2.2 A typical inductive wireless power transfer system with linear regulators and data up-link
through load modulation for power control

up-link is realized by back-scattering through changing the input impedance of the

rectifier (by shorting out the two AC inputs, for example) to transmit digitized data
of the voltage information VDC back to the primary side using the power-link
frequency carrier. In this case, the RX side needs more and larger energy-storing
components, as normally no energy can be extracted during the back-scattering
durations. The up-link data is recovered by magnetic sensing of the PA output
current through a detection coil and a load detector. The data is then used to control
the supply voltage of the PA and thus the transmitted output power.
The global voltage-regulation loop consists of several low-frequency poles due
to the DC-DC converter, the PA driven inductive link, the rectifier, etc. An
integrator with a pole at DC, that is, 1/s, is needed in the power control unit (PCU)
to stabilize the global loop. A frequency compensator with one or more zeros may
be used in the PCU to improve the phase margin. If a higher WPT frequency and/or
a higher DC-DC switching frequency is chosen, smaller passive components can be
used in the power converters, and the frequencies of the non-dominant poles can
also be higher. Consequently, the stability problem of the global loop can be
alleviated, the loop bandwidth can be widened, and the transient response can be
faster.
In many state-of-the-art designs, novel system-level output-voltage regulation
schemes have been proposed to eliminate the post-conversion stage, and conse-
quently system complexity can be reduced and the total efficiency can be increased
[10–26]. These schemes are discussed in the following sub-sections.

2.2.1 Primary Side Non-linear Power Control

Voltage regulation can be implemented on the primary side using linear control
methods (for example, amplitude modulation, AM) or using non-linear control
2.2 Output Voltage Regulation Schemes 17

methods. With TX side power control, regulation blocks in the RX side may be
eliminated in principle, and the total system efficiency can be higher. However, the
global control loop is usually not fast enough to respond to the load transient on the
RX side, and the local regulation blocks should not be removed. In one linear
control method, the supply voltage of the PA may be changed to tune the output
power [6, 7], because the on-resistance of the switches is almost linearly propor-
tional to its gate-to-source voltage VGS. To change the PA supply voltage linearly
and consequently the output power, the speed is limited by the large passive
components of the DC-DC converter and the resonance power link. Thus, for a
faster transient response to the load, primary side non-linear control methods may
be used [10–13] as discussed below.
Figure 2.3 shows a primary side non-linear control method by changing the PA
switching frequency between the LC resonance frequency FRES and its odd-order
sub-harmonic frequency FRES/3 [11]. In this system, the energy delivered from the
PA to the LC tank is reduced from once every resonance period at the input
frequency of FRES to once every 3 resonance periods at the input frequency of
FRES/3, while the amplitude of the PA output voltage is kept constant, as shown by
the conceptual waveforms in Fig. 2.3. Thus, the transmitted powers at these two
different input frequencies are changed. Note that although the input frequency of
the PA would vary between FRES and FRES/3, the LC resonance tanks of the power
link still always operate at their resonant frequency, because the resonance tanks are
band-pass filters.
The hysteretic comparator on the RX side serves as a one-bit analog-to-digital
converter (ADC), and the digitized RX power demand signal is obtained by
comparing the RX output voltage with a reference voltage, and fed back to the
TX side by the data up-link. At the TX side, the digitized power demand signal is

Fig. 2.3 A WPT system with output power controlled by transmission frequency hopping
18 2 Wireless Power Transfer Systems

Fig. 2.4 A WPT system with output power controlled by the phase difference between two
transmitters

integrated by a digital loop filter and processed by a ΣΔ-modulator for frequency

domain noise-shaping. A frequency-control signal is then generated for spurious
emission reduction. The power level is adjusted through mode-switching between
FRES and FRES/3, and higher power means the FRES-mode would occur more
frequently than the FRES/3-mode.
A two-transmitter topology was proposed in [12] also for non-linear primary-
side power control, as shown in Fig. 2.4. Two physically overlapping TX coils L1A
and L1B are driven by two separate PAs, and the input clocks of these two PAs have
the same frequency but different phases, and are controlled by a delay-locked loop
(DLL). When the power demand signal is fed back to the primary side, the phase
select circuit will increase or decrease the phase difference θ between the two clock
signals to adjust the combined output power of the two PAs. With larger phase
difference, the combined output power is lower, and vice versa. The combined
output power PO can be approximately obtained as POA  (1 + cosθ) where POA is
the output power of a single PA.
One problem with this two-PA structure is that, although the regulation stage on
the RX side is removed for higher total efficiency, the transmission efficiency is low
as the transmitted power is reduced while the power loss of the transmitter is not
reduced proportionally.
Another advanced primary-side power control technique is to set the duty ratio
of the operation of the PA according to the demand of the load [13]. When a “Stop”
signal comes in, the PA will stop switching to reduce the output power and thus
reduce the switching loss at the same time. In [13], the PA stops periodically for a
2.2 Output Voltage Regulation Schemes 19

fixed duration of time (which is also called constant-idle or constant-off time

control), while the operating time varies with the load condition.

2.2.2 Reconfigurable Rectifier for Adaptive Output

In a WPT system with no primary-side power control, a reconfigurable rectifier that

can adapt its operating mode according to the output voltage level can provide
coarse regulation instead and extend the power transmission range as demonstrated
in [14–16]. Figure 2.5 shows an inductively coupled WPT system with a
reconfigurable rectifier for low-power applications. A hysteretic comparator is
used to compare the rectifier DC output voltage with the reference voltage, and to
decide the operating mode of the reconfigurable rectifier. The hysteresis window
used in Fig. 2.5 is relatively large (1 V), and amounts to only 1-bit resolution, and
VDC is not accurate enough for driving the load. Thus, an LDO regulator is still
needed in such a system for accurate regulation.
A typical 1X/2X reconfigurable rectifier with passive diodes is also shown in
Fig. 2.5. When the mode-switch M1 is turned off, the four diodes operate as a full-
wave rectifier, denoted as the 1X mode. When M1 is turned on, the two diodes D1
and D2 along with the two capacitors CL1 and CL2 then operate as two half-wave

Fig. 2.5 A WPT system with reconfigurable rectifier for coarse regulation and transmission
distance extension
20 2 Wireless Power Transfer Systems

rectifiers stacked together to form a voltage doubler, denoted as the 2X mode. The
other two diodes stay off in this mode, and the voltage VAC2 is clamped to a DC
potential roughly equals to half of VDC.
Assume that the same AC input amplitude and the same load resistance are
maintained, and assume that the power conversion is ideal with unity efficiency.
The 2X mode will provide an output voltage that is two times that of the 1X mode,
and with the same load resistance, the load current is also doubled. Hence, the
power sourced from the AC input is four times larger, and the equivalent input
impedance of the 2X mode seen by the AC input is 1/4 that of the 1X mode. This
impedance characteristic should be taken into account when designing the system
operating point. However, the analysis is not as straightforward, as the assumption
of the AC amplitude remained unchanged under mode change basically does not
hold in a WPT system, because the load, be it load current or load resistance, will
change in different modes, and so as the equivalent impedance reflected to the
primary side. Consider the general case illustrated in Fig. 2.6a. The load resistor on
the RX side is mapped to the primary side as RL,EQ, and the PA has an equivalent
output impedance of RS. As shown in Fig. 2.6b, when RL,EQ is equal to RS, the
output power delivered to the equivalent load PL is the maximum, and the ideal
efficiency at this point is 50%. We learn that RL,EQ in 2X mode is smaller than that
in 1X mode, and if RL,EQ in 1X mode happens to be smaller than RS (on the left side
of the curves), the available output power will decrease when the rectifier changes
to 2X mode with an even smaller RL,EQ. Thus, to make the reconfigurable rectifier
scheme works properly, the system has to operate on the right side of the curves
(at low power levels). This limits the scheme to be valid only for low-power
applications, such as implantable medical devices.
Besides, the input reactance of the reconfigurable rectifier will also vary under
different operating modes. Thus, an adaptive input matching network that can tune
the resonance capacitor automatically would be helpful for achieving higher effi-
ciency and higher output power.
By considering all the above factors, a reconfigurable rectifier is proposed to
provide an alternative power control strategy for extending the output power level
and transmission distance, and increasing the system efficiency.

Fig. 2.6 (a) Simple equivalent circuit model of a WPT system, and (b) illustration of the
relationship of load impedance, output power, and efficiency
2.2 Output Voltage Regulation Schemes 21

2.2.3 Resonant Regulating Rectifier

Wireless power transfer systems can be classified into two categories: inductive
power transfer (IPT) and resonant wireless power transfer (R-WPT). Both schemes
generate a magnetic field by a resonant circuit to transmit power. An IPT system
requires the coupling coils be placed closely together and well-aligned for high
efficiency, and a magnetic core is often used. It can operate over a wide range of
transmission frequency, and as a low-Q system, it eases the requirements on the
passive components. For an R-WPT system, the coils can be loosely coupled such
that there is more spatial freedom for the related application. Both the primary coil
and the secondary coil are tuned with either a series or a parallel capacitor to form
LC resonant tanks with very high Q. Both coils are tuned to the same resonant
frequency such that the power transmission distance can be extended with a
reasonable efficiency. However, the resonant operation is sensitive to component
variations, since the LC resonant tank has high Q, and thus the transmitted power
spectrum is narrow band, and the efficiency is relatively lower than an IPT system
because of the weaker coupling.
Actually, an R-WPT system is pretty much like the topology of a conventional
resonant DC-DC converter system, with the transformer in the middle being
replaced by a pair of loosely coupled coils. When the switching frequency of the
resonant converter exactly coincides with the resonant frequency, the resonant
converter operates optimally with reduced switching loss, and consequently pro-
vides high power conversion efficiency. But when the resonant converter is opti-
mized at one operating point, it is hard to control the output power. Besides, in
R-WPT applications such as mobile phone charging or powering implantable
medical devices, it is difficult to achieve the resonant condition with cm-sized or
mm-sized coils at a low frequency in the kHz range, and a resonant frequency in the
MHz range is required instead.
A time-domain control method was proposed to control a resonant DC-DC
converter in [17] by adjusting the output voltage while still satisfying the optimum
operating conditions. By selectively enabling or disabling the converter at integral
multiples of half cycles, the output power can be tuned. A similar idea was applied
to control the power of an R-WPT system as well, and is discussed below.
Let us consider that the receiver side employs series resonance as shown in
Fig. 2.7. The resonator composed of L2 and C2 acts as an AC current source that
supplies current to the rectifier. A switch M1 with pulse-width modulation (PWM)
control is added to the rectifier output to control the output voltage, and is regarded
as a one-switch resonant regulating rectifier (3R) in [17]. When M1 is on, the
resonator is designed to operate in its resonating mode, so the resonant current
IRS increases and is delivered to the load, and VOUT goes up. When M1 is off, no
current goes to the load from the rectifier and the output capacitor is drained by the
load and VOUT decreases, the resonator deviates from its resonating point and IRS
decreases. Thus, by tuning the turn-on duty cycle of M1, the output voltage can be
regulated without using an additional power converter or linear regulator. The
22 2 Wireless Power Transfer Systems

Fig. 2.7 A resonant WPT system with one-switch pulse-width modulation regulating rectifier

limiting capacitor CLM is used to reduce the voltage peak on the node VX, thus
preventing the over-voltage condition when M1 is in the off state. The resonant
regulating rectifier is designed to operate in the discontinuous conduction mode
(DCM). It delivers current to the load only discontinuously and results in large
peak current of IREC that degrades the efficiency, as the conduction loss of M1 is
given by
Z t0 þNT
1
PCond:Loss ¼ I 2REC ðtÞ  RON dt, ð2:2Þ
NT t0

where RON is the total on-resistance of M1 and the diodes, T is the operating period
and N is an integer. Thus, reducing the peak current of IREC is favorable for
increasing the power conversion efficiency.
Consequently, the continuous conduction mode (CCM) operation was also
proposed in [17] with one flying capacitor CFLY and three switches M1–M3, as
shown in Fig. 2.8. The flying capacitor is switched to stack on top of the output
capacitor like a step-down charge pump to provide charge for the load. When M1
and M3 are off and M2 is on, CFLY is in series with CL. Hence, VOUT is roughly ½
2.2 Output Voltage Regulation Schemes 23

Fig. 2.8 A resonant WPT system with pulse-width modulation regulating rectifier and step-down
charge pump

times of VX, and IREC starts to decrease. When M1 and M3 are on and M2 is off,
CFLY is in parallel with CL, and the full-wave rectifier charges up VOUT. In CCM
operation, IREC only drops to zero temporarily and immediately rebounds, and
hence provides a continuous current to the load, and results in higher power
conversion efficiency and lower output voltage ripples. Moreover, the current
variations of IRS and IREC are not as pronounced, relieving the voltage stress on
VX, and consequently smaller CLM could be used.

2.2.4 Reconfigurable Resonant Regulating Rectifiers

Based on the knowledge of the above two sub-sections, a 1X/2X reconfigurable

resonant regulating (R3) rectifier was designed in [19] as illustrated in Fig. 2.9. The
reconfiguration switch M1 is now controlled by a PWM signal as well. When M1 is
off, the rectifier operates in 1X mode and the ideal output in this case is VAC,Peak.
When M1 is on, the rectifier operates in 2X mode and tends to reach to 2 times of
VAC,Peak. Thus, when the rectifier is switched between 1X mode and 2X mode,
24 2 Wireless Power Transfer Systems

Fig. 2.9 A WPT receiver with 1X/2X regulating rectifier with pulse-width modulation

VOUT decreases and increases periodically and can be regulated at the prescribed
voltage level. The waveforms plotted in Fig. 2.9 show the CCM case; and of course,
the regulating rectifier can operate in DCM at light-load conditions as well. Hence,
the output can be well regulated under different load conditions.
Another advanced version of the R3 rectifier was proposed in [20] as shown in
Fig. 2.10. This reconfigurable rectifier has three modes: 1X, ½X, and 0X modes. In
the 1X mode, both M1 and M2 are off, and the active diodes operate as a full-wave
rectifier that can provide large output current to the load. In the ½X mode, M1 is on
and M2 is off, VAC2 is shorted to ground. Then, only one diode out of the four will
conduct current I1 to the load as a half-wave rectifier. Compared to the 1X mode,
the current delivered to the load is halved, and this mode is named as the ½X mode.
In the 0X mode, both M1 and M2 are on, and the receiver resonant tank L2 and C2 is
freewheeling. This is different from the M1 off-state of the one-switch 3R opera-
tion, whence the rectifier is disconnected from the load, and breaks the path of the
inductor current.
Output regulation of the above topology can be achieved by switching between
two of the three modes, to achieve a finer regulation. In heavy load conditions,
mode-switching between 1X and ½X modes are activated; and in light load
conditions, ½X and 0X modes are activated. Therefore, CCM operations can be
maintained for a wide load current range. A smooth transition between different
modes during load transient can be achieved with accurate load current sensing
techniques which add minor circuit complexity to the on-chip implementation.
2.2 Output Voltage Regulation Schemes 25

Fig. 2.10 A WPT receiver with 1X/½X/0X regulating rectifier with pulse-width modulation

2.2.5 Pre-rectifier Regulation

Besides the above mentioned primary-side power control and reconfigurable and/or
regulating rectifier topologies for output regulation, pre-rectifier regulation topol-
ogy was proposed in [21, 22], as shown in Fig. 2.11. Similar to the previous mode-
switching schemes using PWM signal, the pre-rectifier regulation scheme (named
as Q-modulation in [21]) modulates the load impedance as seen from the resonator,
and achieves output regulation.
As shown by the conceptual waveforms in Fig. 2.11, the switch M1 is turned on
at the zero-crossing point of the resonating current IRS, which is commonly known
as zero-current switching (ZCS). To avoid the switch from experiencing high
voltage and high current simultaneously that causes unnecessary conduction loss,
ZCS is an important operation principle to achieve high efficiency. During the
on-state of M1, the high-Q resonant tank L2 and C2 stores the maximum energy that
is transferred from the primary side. During the off-state of M1, the energy stored in
the resonant tank together with the continually transferred energy is delivered to the
load through I1 and I2 of the rectifier. Therefore, the amount of energy that is
transferred to the load can be controlled by tuning the duty cycle D of the switch.
Different from the mentioned regulation schemes, this scheme achieves regulation
within one cycle at the resonant frequency and requires faster control circuits (faster
transistors).
26 2 Wireless Power Transfer Systems

Fig. 2.11 A WPT receiver with PWM pre-rectifier regulation

The maximum input amplitude (the carrier envelope) is tracked by a dedicated

feedback loop as designed in [21], such that the duty cycle D will be increased or
decreased accordingly. Since the loop only tracks the input voltage, an LDO
regulator is still needed to obtain an accurate output voltage. On the other hand,
in [22], the rectifier output was used to compare with a reference voltage to generate
the PWM signal. Therefore, the post-stage LDO regulator can be removed.
In fact, this topology and its operation principle are similar to a resonant DC-DC
boost converter, in which the inductor accumulates energy first and then delivers
the energy to the load through a diode. The switch M1 can be implemented by an
NMOS transistor with the gate-drive referenced to the ground potential, as shown in
Fig. 2.11. The equivalent load impedance RL,EQ seen from the resonator can be
roughly computed as

ð8=π 2 ÞRL  
RL, EQ ¼ 2
¼ ð1  DÞ2 8=π 2 RL , ð2:3Þ
M

where M ¼ 1/(1  D) is the voltage conversion ratio of the boost converter operating
in CCM. The full-wave rectifier converts the impedance RL into (8/π2) RL, assuming
that the LDO regulator is ideal. With a PWM feedback loop, the Q-modulation
technique can transform the load impedance automatically for any load and cou-
pling variations.
2.2 Output Voltage Regulation Schemes 27

2.2.6 Multi-Level Single-Inductor Multiple Output

Operation

In many applications, different power supply levels are required by the system for
various functions [26, 27], while the ripples generated by the converters should be
reasonably small for noise-sensitive loads. Therefore, the bulky passive compo-
nents of the converters should be utilized effectively [15] or even be reused with
time multiplexing. For an application that requires multiple outputs, single-inductor
multi-output (SIMO) techniques could be employed to reduce the number of
inductors [27, 28]. A multi-level SIMO operation for the WPT RX was proposed
in [26], which merged a multi-level SIMO switching converter with a multi-stage
rectifier as shown in Fig. 2.12.
In such configuration, any output voltage that has a value between VDCk and VDC
(k1) (k ¼ 1, 2, . . ., N), can be regulated by sinking currents from those two rectifier
outputs through L3 as a buck converter. The voltage across L3 can be smaller than
that of the typical two-level operation, such that the inductor current and the output
voltage ripples are reduced because of the reduced voltage swing across L3.
Moreover, for the voltage boosting application, the AC input is boosted without
introducing the well-known right-half-plane zero that exists in boost and buck-
boost converters, which means that the loop bandwidth of the buck converter can be
designed at higher frequency for fast transient responses. It is also noted that the
maximum achievable efficiency of the series-parallel multi-stage rectifier does not
change with the number of stages, since all the stages get energy from the AC input
in one phase and then being stacked to attain a high VDC in the complementary
phase.
To demonstrate the idea, a 3-level single-inductor dual-output DC-DC converter
that inherently cooperates with a 2X active rectifier (voltage doubler) that gives two
DC outputs (3-level) was designed for the WPT RX [26], as shown in Fig. 2.13.

Fig. 2.12 A WPT receiver with a 2(N  1)-stage rectifier merged with N-level single-inductor
multi-input multiple-output converter
28 2 Wireless Power Transfer Systems

Fig. 2.13 A WPT system with 2X rectifier and 3-level SIMO converter

Assume the VAC amplitude is 3.2 V, VDC1 will be around 2.7 V and VDC2 will be
approximately 5.5 V. The higher output voltage VO2 retrieves current from VDC2
and VDC1, and can be programmed to range from 3.3 V to 5 V for I/O and memory
circuits; while the lower output voltage VO1 retrieves current from VDC1 and Gnd,
and can be programmed to range from 1.0 V to 1.8 V for core circuits.
The SIMO converter also switches at the WPT frequency of 6.78 MHz. One
benefit of operating the DC-DC converter at the WPT frequency is that, part of the
discontinuous rectifier output currents will directly go to the DC-DC converter
inputs in every half cycle, bypassing the rectifier load capacitors CDC1 and CDC2,
thus further reduces the output ripple. Now, the volume of a passive component is
roughly proportional to its value. In this work, smaller L3 and capacitors can be
used, benefiting from the 3-level and 6.78 MHz discontinuous conduction mode
(DCM) operation. An independent PWM control loop is used for each output, such
that cross-regulation can be reduced as long as the converter works in DCM.
The timing diagram of the 3-level SIMO converter in DCM operation is shown
in Fig. 2.14. The clock pulse Clk’ that initiates the PWM control for VO1 is
recovered from VAC by an inverter and a pulse generator, and the zero current
detection (ZCD) signal that determines the connection of VX2 is generated by
sensing the current of MP2. Since both VO2 and VO1 need to get current from
2.3 Summary and Discussion 29

Fig. 2.14 Timing diagram of the 3-level SIMO converter in DCM operation

VDC1, MP2 is kept on during the output transition period to avoid one-time switching
loss of MP2 in every cycle. A comparator is used to detect the VX1 voltage crossing
point. When VX1 > VDC1 during the on-state of SIN1, a pulse ZCD’ that initiates the
PWM control for VO2 will swap the output control signals SO2 and SO1. A large
quiescent current is needed to increase the speed of the comparator so as to reduce
the reverse current of MP2. Alternatively, the speed requirement on the ZCD can be
relaxed by using an additional slow auto-calibration loop to adjust the comparator
offset, as demonstrated in [3]. Since the calibration loop only requires a low
bandwidth, for example 200 kHz in [3], its current consumption is only on the
order of 1 μA. A freewheel switch SFW will be turned on at the end of each cycle
when both AD3 and MP4 are off, to suppress the possible ringing caused by L3 and
the parasitic capacitors at the VX1 and VX2 nodes when they are floating [28]. For
higher conversion efficiency and/or large power handling capability of the SIMO
DC-DC converter, lower switching frequency can be used [29].

2.3 Summary and Discussion

For wireless power transfer systems, as reviewed in this chapter at the system level,
output voltage regulation can be achieved by using primary side power control,
reconfigurable/regulating rectifiers, as well as pre-rectifier regulation topologies, or
simply cascading a DC-DC converter stage in the receiver. For the regulating
30 2 Wireless Power Transfer Systems

rectifiers and the pre-rectifier regulation schemes, pulse-width modulation is com-

monly used that is similar to DC-DC converter control of an accurate output. The
equivalent load impedance is automatically tuned by the dedicated PWM loop that
adapts to the load and coupling distance/orientation variations. Consequently, high
efficiencies can be achieved for the WPT receiver and also the entire WPT system.
Besides the mentioned equivalent load impedance modulation techniques, there
are two more direct ways to further improve the WPT system efficiency. One is to
achieve the goal at the circuit level, that is, to improve the efficiencies of each
cascading power stages, which will be discussed in the following chapters. Take the
active rectifier design as an example, optimizing the size of the cross-connected
transistors can enhance the efficiency, because the parasitic capacitors of the cross-
connected transistors are actually part of the resonant tank that should not be taken
as switching loss [30]. The other feasible solution is to reduce the number of
converter stages. For example, a wireless charger can be designed without a post-
stage DC-DC charger [31, 32], but directly charges the battery or super-capacitor
through the rectifier only. In such case, the system regulation loop should control
the charging current instead of the output voltage. One stage of conversion loss can
thus be eliminated. However, sensing the averaged charging current for regulation
would be a challenge for circuit designers.
In terms of device volume, bulky passive components of the AC-DC and DC-DC
converters should be utilized effectively or be reused with time multiplexing for
miniaturized devices. In addition, operating at a higher WPT frequency can signif-
icantly reduce the sizes of the passive components. Moreover, smaller inductance
with higher Q can be more easily achieved at higher frequencies within a limited
space, which is one of the key factors for improving the WPT link efficiency.
Last but not least, similar to all other analog circuit designs, a dedicated
feedback loop controlling the critical parameter is essential for a good WPT design.
Meanwhile, for robust operation, a WPT system that has multiple loops, the
dynamics of each local (fast) and global (slow) loop has to be analyzed carefully
and thoroughly.

References

1. Wang C-S, Covic GA, Stielau OH (2004) Power transfer capability and bifurcation phenom-
ena of loosely coupled inductive power transfer systems. IEEE Trans Ind Electron
51:148–157. doi:10.1109/TIE.2003.822038
2. Ahn D, Hong S (2014) Wireless power transmission with self-regulated output voltage for
biomedical implant. IEEE Trans Ind Electron 61:2225–2235. doi:10.1109/TIE.2013.2273472
3. Cheng L, Ki WH, Lu Y, Yim TS (2016) Adaptive on/off delay-compensated active rectifiers
for wireless power transfer systems. IEEE J Solid State Circuits 51:712–723. doi:10.1109/
JSSC.2016.2517119
4. Lee H-M, Park H, Ghovanloo M (2013) A power-efficient wireless system with adaptive
supply control for deep brain stimulation. IEEE J Solid State Circuits 48:2203–2216. doi:10.
1109/JSSC.2013.2266862
References 31

5. Lee H-M, Ghovanloo M (2013) A power-efficient wireless capacitor charging system through
an inductive link. IEEE Transac Circuits Syst II Express Briefs 60:707–711. doi:10.1109/
TCSII.2013.2278104
6. Wang G, Liu W, Sivaprakasam M, Kendir G (2005) Design and analysis of an adaptive
transcutaneous power telemetry for biomedical implants. IEEE Transac Circuits Syst I
Regul Pap 52:2109–2117. doi:10.1109/TCSI.2005.852923
7. Li X, Lu Y, Tsui C-Y, Ki W-H (2014) An adaptive wireless powering and data telemetry
system for optic nerve stimulation. In: IEEE international symposium on circuits and systems
(ISCAS), 2014, pp 1404–1407. doi:10.1109/ISCAS.2014.6865407
8. Park H, Jang J, Kim H, Park Y, Oh S, Pu Y, Hwang KC, Yang Y, Lee K (2016) A design of a
wireless power receiving unit with a high-efficiency 6.78-MHz active rectifier using shared
DLLs for magnetic-resonant A4 WP applications. IEEE Trans Power Electron 31:4484–4498.
doi:10.1109/TPEL.2015.2468596
9. Moti K-G, Neri F, Moon S, Yeon P, Yu J, Cheon Y, Roh Y, Ko M, Park B-H (2015) 12.9 A
fully integrated 6W wireless power receiver operating at 6.78MHz with magnetic resonance
coupling. In: IEEE international solid- state circuits conference – (ISSCC), 2015, pp 1–3
10. Radecki A, Chung H, Yoshida Y, Miura N, Shidei T, Ishikuro H, Kuroda T (2011) 6W/25mm2
inductive power transfer for non-contact wafer-level testing. In: IEEE international solid-state
circuits conference digest of technical papers (ISSCC), 2011, pp 230–232
11. Shinoda R, Tomita K, Hasegawa Y, Ishikuro H (2012) Voltage-boosting wireless power
delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching.
In: IEEE international solid-state circuits conference digest of technical papers (ISSCC), 2012,
pp 288–290
12. Tomita K, Shinoda R, Kuroda T, Ishikuro H (2012) 1-W 3.3–16.3-V boosting wireless power
transfer circuits with vector summing power controller. IEEE J Solid State Circuits
47:2576–2585. doi:10.1109/JSSC.2012.2211698
13. Huang C, Kawajiri T, Ishikuro H (2016) A wireless power transfer system with enhanced
response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control
for implants. In: 2016 I.E. symposium on VLSI circuits (VLSI-Circuits). doi:10.1109/VLSIC.
2016.7573491
14. Lee H-M, Ghovanloo M (2012) An adaptive reconfigurable active voltage doubler/rectifier for
extended-range inductive power transmission. IEEE Transac Circuits Syst II Express Briefs
59:481–485. doi:10.1109/TCSII.2012.2204840
15. Lu Y, Li X, Ki W-H, Tsui C-Y, Yue CP (2013) A 13.56MHz fully integrated 1X/2X active
rectifier with compensated bias current for inductively powered devices. In: 2013 IEEE inter-
national solid-state circuits conference (ISSCC), pp 66–67. doi:10.1109/ISSCC.2013.6487639
16. Lee H (2016) An auto-reconfigurable 2/4 AC-DC regulator for wirelessly powered bio-
medical implants with 28% link efficiency enhancement. IEEE Transac Very Large Scale
Integ (VLSI) Syst 24:1598–1602. doi:10.1109/TVLSI.2015.2452918
17. Joung GB, Rim CT, Cho GH (1989) Integral cycle mode control of the series resonant
converter. IEEE Trans Power Electron 4:83–91. doi:10.1109/63.21875
18. Choi J-H, Yeo S-K, Park S, Lee J-S, Cho G-H (2013) Resonant regulating rectifiers
(3R) operating for 6.78 MHz resonant wireless power transfer (RWPT). IEEE J Solid State
Circuits 48:2989–3001. doi:10.1109/JSSC.2013.2287592
19. Li X, Tsui C-Y, Ki W-H (2015) A 13.56 MHz wireless power transfer system with
reconfigurable resonant regulating rectifier and wireless power control for implantable medical
devices. IEEE J Solid State Circuits 50:978–989. doi:10.1109/JSSC.2014.2387832
20. Cheng L, Ki W-H, Wong Y-T, Yim T-S, Tsui C-Y (2016) A 6.78MHz 6W wireless power
receiver with a 3-Level 1/½/0 reconfigurable resonant regulating rectifier. In: 2016 IEEE
international solid-state circuits conference (ISSCC), pp 376–377
21. Kiani M, Lee B, Yeon P, Ghovanloo M (2015) A Q-modulation technique for efficient
inductive power transmission. IEEE J Solid State Circuits 50:2839–2848. doi:10.1109/JSSC.
2015.2453201
32 2 Wireless Power Transfer Systems

22. Ahn D, Kim S, Moon J, Cho IK (2016) Wireless power transfer with automatic feedback
control of load resistance transformation. IEEE Trans Power Electron. doi:10.1109/TPEL.
2015.2513060
23. Lee B, Kiani M, Ghovanloo M (2016) A triple-loop inductive power transmission system for
biomedical applications. IEEE Transac Biomed Circuits Syst 10:138–148. doi:10.1109/
TBCAS.2014.2376965
24. Zhao J, Yao L, Xue RF et al (2016) An integrated wireless power management and data
telemetry IC for high-compliance-voltage electrical stimulation applications. IEEE Transac
Biomed Circuits Syst 10:113–124. doi:10.1109/TBCAS.2015.2404038
25. Lee KFE (2010) A timing controlled AC-DC converter for biomedical implants. In: 2010 IEEE
international solid-state circuits conference – (ISSCC), pp 128–129
26. Lu Y, Huang M, Cheng L et al (2017) A dual-output wireless power transfer system with active
rectifier and three-level operation. IEEE Trans Power Electron 32:927–930. doi:10.1109/
TPEL.2016.2601623
27. Ma D, Ki W-H, Tsui C, Mok PKT (2003) Single-inductor multiple-output switching con-
verters with time-multiplexing control in discontinuous conduction mode. IEEE J Solid State
Circuits 38:89–100. doi:10.1109/JSSC.2002.806279
28. Ma D, Ki W-H, Tsui C (2003) A pseudo-CCM/DCM SIMO switching converter with free-
wheel switching. IEEE J Solid State Circuits 38:1007–1014. doi:10.1109/JSSC.2003.811976
29. Jing X, Mok PKT, Lee MC (2011) A wide-load-range constant-charge-auto-hopping control
single-inductor-dual-output boost regulator with minimized cross-regulation. IEEE J Solid
State Circuits 46:2350–2362. doi:10.1109/JSSC.2011.2162188
30. Lu Y, Ki W-H (2014) A 13.56 MHz CMOS active rectifier with switched-offset and compen-
sated biasing for biomedical wireless power transfer systems. IEEE Transac Biomed Circuits
Syst 8:334–344. doi:10.1109/TBCAS.2013.2270177
31. Lazaro O, Rincón-Mora GA (2013) 180-nm CMOS wideband capacitor-free inductively
coupled power receiver and charger. IEEE J Solid State Circuits 48:2839–2849.
doi:10.1109/JSSC.2013.2280053
32. Huang M, Lu Y, U S-P, Martins RP (2017) A reconfigurable bidirectional wireless power
transceiver with maximum current charging mode an 58.6% battery-to-battery efficiency.
In: 2017 IEEE international solid-state circuits conference – (ISSCC), pp 376–377.
doi:10.1109/ISSCC.2017.7870418
Chapter 3
Analysis of Coupled-Coils

Abstract This chapter introduces a design-oriented analysis of various wireless

power links driving a resistive load, which include the ideal coupled-coils, the
coupled-coils with parasitic resistors, the coupled-coils with series-resonant pri-
mary and series-resonant secondary, and the coupled-coils with series-resonant
primary and parallel-resonant secondary. The standard equation-pair of coupled-
inductors is employed to analyze the above configurations to obtain (1) the reflected
impedance of the secondary circuit detected at the primary side, (2) the link voltage
gain and (3) the link efficiency. We label the analysis as design-oriented by
presenting the equations with parameters arranged in a way that expose the physical
meaning of the results and help with designing the coupled-coils more systemati-
cally and effectively.

Keywords Wireless power transfer • Coupled coils • Coupled inductors • Parallel

resonant • Series resonant • Link voltage gain • Link efficiency • Reflected
impedance

3.1 Introduction

One of the pioneer researches of wireless power transfer for biomedical implants is
[1]. This paper did not derive the equations from the first principle, and it is difficult
for readers to identify the relations among the several loads R, Ro and RL. Typo-
graphical errors also obscure the reading of the results. For example, Fig. 1 of [1]
shows a parallel-resonant secondary circuit, but in Fig. 2 the secondary equivalent
circuit becomes a series-resonant circuit. Moreover, the inductor, resistor and
capacitor of the secondary circuit are labeled L1, R1 and C1 that should belong to
the primary circuit. Similar ambiguities apply to [2], and there is no explanation on
why the coupling coefficient k has to be smaller than 0.509, or how Pi(ω) is
computed.
In [3], various configurations of coupled-coils such as the non-resonant coupled-
coils, and coupled-coils with juxtaposed series-resonant and parallel-resonant coils
for the primary and the secondary have been analyzed and even optimized. It seems
that the analysis works have been completed, and we only need to worry about
applying the results for design. However, the design equations are shrouded in

© Springer Nature Singapore Pte Ltd. 2018 33

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_3
34 3 Analysis of Coupled-Coils

symbols that could be difficult to decipher. For example, the term R2/RL is easily
recognized as the ratio of the parasitic resistor R2 over the load resistor RL, but in [3]
it is written as QL/Q2 (¼(ωoL2/RL)/(ωoL2/R2)) and the meaning is not readily recog-
nized. If all the quality factors (Q’s) are expanded in full the equations again become
too complicated to read. One essential ingredient of design-oriented analysis is to
group the terms tactically that expose the physical meaning underneath.
It should be noted that the basic analysis of a pair of coupled-inductors has been
discussed in undergraduate textbooks such as [4]. The derivation is direct and
uncomplicated. It is our aim to work out various configurations of coupled-coils
following a straightforward methodology, as will be illustrated in the sections
below.

3.2 Coupled-Coils and Modeling

3.2.1 Ideal Transformer

Before working on the coupled-coils, let us consider the ideal transformer and its
modeling, as shown in Fig. 3.1.
The ideal transformer has turns-ratio of 1:n and with the dot-orientation as
shown, the (s-domain) I-V characteristic is described by the following equations:

V 2 ¼ nV 1 ð3:1Þ
I 1 ¼ nI 2 ð3:2Þ

The circuit model in the s-domain is shown in Fig. 3.1b, and the input impedance
zin(s) can be computed as

V1 1
zin ðsÞ ¼ ¼ 2 Z L ðsÞ ð3:3Þ
I1 n

Simply put, in the above discussion, the ideal transformer is modeled using one
current-controlled current source and one voltage-controlled voltage source. In fact,
it is possible to construct other equivalent circuits that substitute each controlled
source with a current/voltage-controlled current/voltage source. However, in prac-
tice, the one shown in Fig. 3.1b proves to be the most convenient.

3.2.2 Ideal Coupled-Coils

Next, Fig. 3.2a shows a pair of ideal coupled-inductors with primary inductance L1,
secondary inductance L2, and mutual inductance M driving a load resistor RL. The
coil system is described in the time-domain by the equation-pair of the coupled-
inductors that drive a resistive load:
3.2 Coupled-Coils and Modeling 35

Fig. 3.1 Ideal transformer: (a) circuit; and (b) circuit model

dI 1 dI 2 0
V 1 ðtÞ ¼ L1 þM ð3:4Þ
dt dt
dI 1 dI 2 0
V 2 ðtÞ ¼ M þ L2 ¼ I 2 0 RL ð3:5Þ
dt dt

The computation would be much simpler when working in the s-domain, and it
is beneficial to define I2 ¼ I20 as shown in Fig. 3.2b. The corresponding s-domain
equations with a generic load impedance ZL(s) are then given by

V 1 ðsÞ ¼ sL1 I 1  sMI 2 ð3:6Þ

V 2 ðsÞ ¼ sMI 1  sL2 I 2 ¼ I 2 Z L ðsÞ ð3:7Þ

To facilitate the computation in different settings, at least three equivalent circuit

models have been developed. They are (1) the T-model; (2) the transformer model;
and (3) the reflected impedance model. As discussed in Sect. 3.2.1, the transformer
model has many variations, and here we only show the most common ones.

3.2.3 T-Model of Coupled-Coils

The T-model is shown in Fig. 3.3, and one limitation is clear: the primary coil and
the secondary coil have to share a common ground.
Nevertheless, if we proceed with the derivation, we have

V 1 ðsÞ ¼ sðL1  MÞI 1 þ sMðI 1  I 2 Þ ð3:8Þ

V 2 ðsÞ ¼ sMðI 1  I 2 Þ  sðL2  MÞI 2 ¼ I 2 ZL ðsÞ ð3:9Þ

The above equations are the same as Eqs. (3.6) and (3.7). The requirement to
have a common ground for the primary side and the secondary side defeats the
purpose of wireless power transfer, and hence, this model is not useful for our
discussion.
36 3 Analysis of Coupled-Coils

Fig. 3.2 Ideal coupled-coils (a) in the time-domain with a resistive load; and (b) in the s-domain
with a generic load impedance ZL(s)

Fig. 3.3 T-model of ideal

coupled-coil

3.2.4 Transformer Model of Coupled-Coils

The transformer model is shown in Fig. 3.4. The mutual inductance can be
accounted for by using the coupling coefficient k and the turns-ratio n that are
defined as
rffiffiffiffiffi
M L2
k ¼ pffiffiffiffiffiffiffiffiffiffi , n ¼ ð3:10Þ
L1 L2 L1

The equations of the model can be derived as follows. With reference to

Fig. 3.4b, the input voltage V1(s) and the output voltage V2(s) are given by

V 1 ðsÞ ¼ sL1 ðI 1  knI 2 Þ ð3:11Þ

 
V 2 ðsÞ ¼ knV 1  s 1  k2 L2 I 2 ð3:12Þ

By substituting k and n of Eq. (3.10) into Eq. (3.11), we have

rffiffiffiffiffiffiffiffiffi
M L2
V 1 ðsÞ ¼ sL1 I 1  sL1 pffiffiffiffiffiffiffiffiffiffi I2 ð3:13Þ
L1 L2 L1

which is easily seen to be the same as Eq. (3.6). Similarly, with the help of Eq. (3.6),
Eq. (3.12) can be rewritten as
3.2 Coupled-Coils and Modeling 37

Fig. 3.4 (a) Transformer model of ideal coupled-coils, and (b) its equivalent circuits on each side

M M2
V 2 ðsÞ ¼ ðsL1 I 1  sMI 2 Þ  sL2 I 2 þ s L2 I 2 ð3:14Þ
L1 L1 L2

which is the same as Eq. (3.7). Hence, the equation-pairs ((3.5), (3.6)) and ((3.11),
(3.12)) are equivalent, and Fig. 3.4b is a valid circuit model of the coupled-coils. As
noted in Sect. 3.2.1, there is more than one equivalent model for the transformer,
which could be employed to model the coupled-coils, and three models other than
the one shown in Fig. 3.4 are discussed in [3].

3.2.5 Reflected Impedance Model of Coupled-Coils

In some applications, it may be convenient to incorporate (reflect) the equivalent

impedance of the secondary loop to the primary loop for analysis. The reflected
impedance model (also known as the equivalent impedance model in [3]) is shown
in Fig. 3.5. Note that the modeling of the secondary coil is the same as that of the
transformer model of Fig. 3.4, and the advantage of this model is to reflect all
components in the secondary side, including the output impedance ZL(s) and the
secondary coil inductance sL2, to the primary side, such that the two sides can be
analyzed independently.
The equations of the primary coil and the secondary coil are easily written down
from Fig. 3.5b as
 
V 1 ðsÞ ¼ sL1 þ Zeq ðsÞ I 1 ð3:15Þ
 
V 2 ðsÞ ¼ knV 1  s 1  k2 L2 I 2 ð3:16Þ

To show that Eq. (3.6) is equivalent to Eq. (3.15), we may write I2 of Eq. (3.6) in
terms of I1 using Eq. (3.7), that is,
 
sM
V 1 ðsÞ ¼ sL1 I 1  sM I1 ð3:17Þ
sL2 þ Z L ðsÞ

With s ¼ jω so that s2 ¼ ω2, we define Zeq(s) as

38 3 Analysis of Coupled-Coils

Fig. 3.5 Reflected impedance model. (a) Circuit model, and (b) model reorganized for clarity

ω2 M 2
Z eq ðsÞ ¼ ð3:18Þ
sL2 þ ZL ðsÞ

and Eq. (3.17) is then the same as Eq. (3.15), and is in turn also equivalent to
Eq. (3.6).

3.2.6 Link Voltage Gain and Link Efficiency

One important reason of developing an equivalent circuit model of the coupled-

coils is to facilitate the computation of the link voltage gain AT and the link
efficiency ηT in the presence of parasitic components, where the subscript
T indicates the complete wireless power link, that is, from the source to the load.
These two parameters are defined as

j Vo j
AT ¼ ð3:19Þ
VS
Po
ηT ¼ ð3:20Þ
PS

where VS and PS are the source voltage amplitude and the source power at the
primary coil, respectively; and |Vo| and Po are the load voltage amplitude and the
load power at the secondary coil, respectively. Note that by construction, VS is
necessarily real.
Computing power in the time-domain involves solving differential equations
and evaluating integrals that are daunting tasks. Instead, we assume the circuit to be
operating in the sinusoidal steady state, and the computations could then be
performed in the phasor domain. Consider a circuit port X with port-voltage
Vx( jω) and port-current Ix( jω), both of which are phasors. The (total) complex
power PXT is given by [5]

1
PXT ¼ PX þ jQX ¼ V x ðjωÞI x ðjωÞ∗ ð3:21Þ
2
3.2 Coupled-Coils and Modeling 39

where PX is the average real power, QX and is the average reactive power, and
Ix( jω)* is the complex conjugate of Ix( jω).

3.2.7 Computing A and η of the Ideal Coupled-Coils

Let us consider the ideal coupled-coils with a resistive load RL using the reflected
impedance (Zeq) model. First, the equivalent impedance of the secondary circuit
reflected to the primary side is given by Eq. (3.18), which is equal to

ω2 M 2
Z eq ðsÞ ¼ ð3:22Þ
RL þ sL2

We may define the quality factor of the inductor of the secondary coil driving the
load RL as QL:

ωL2
QL ¼ ð3:23Þ
RL

and Eq. (3.22) can be written as

ω2 M 2
Zeq ðjωÞ ¼   ð1  jQL Þ ð3:24Þ
RL 1 þ QL 2

or equivalently,

k2 QL 2
Z eq ðjωÞ ¼   RL ð1  jQL Þ ð3:25Þ
n2 1 þ Q L 2

The link voltage gain can easily be obtained by referring to Fig. 3.5b as
 
j V o j  RL 1

AT ¼ ¼ knV S    ð3:26Þ
VS  RL þ jω 1  k L2 V s
2

kn
) AT ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 2 ffi ð3:27Þ
1 þ 1  k2 QL 2

The coupling coefficient cannot be larger than unity, that is, k  1; and for the
weak coupling case it could be very small, that is, k < <1. Moreover, if the load
resistance is large then QL will not be high, and could even be lower than unity, that
is, QL < 1.
The computation of the link efficiency is more involved. First of all, the average
power of the load is given by
40 3 Analysis of Coupled-Coils

1 1
Po ¼ V o I o ∗ ¼ RL jI o j2 ð3:28Þ
2 2

Similarly, the complex power of the source PST is

1
PST ¼ PS þ jQS ¼ V S I S ∗ ð3:29Þ
2

In general, the product VSIS* cannot be guaranteed to be real, but only the real
part will be used to compute the link efficiency. Moreover, the source VS would be
outputting power instead of absorbing power, and to arrive at a positive PS, IS is
taken as the negative of the port current of VS instead.
One simple way to compute Eq. (3.29) is to express VS and IS in terms of I2.
From Eq. (3.7) (with ZL(s) ¼ RL) we have

RL þ jωL2
I1 ¼ I2 ð3:30Þ
jωM

Eq. (3.30) is then substituted into Eq. (3.6) to obtain

 
RL þ jωL2
V1 ¼ jωL1  jωM I 2 ð3:31Þ
jωM

With VS ¼ V1, IS ¼ I1 and Io ¼ I2, Eq. (3.29) becomes

 
jI o j2 RL þ jωL2 RL  jωL2
PST ¼ jωL1  jωM ð3:32Þ
2 jωM jωM
2 
jI o j RL þ ω2 L2 2
2
) PST ¼ RL  jωL2 þ jωL1 ð3:33Þ
2 ω2 M 2

Clearly, the real part of PST is

1
PS ¼ ReðPST Þ ¼ RL jI o j2 ð3:34Þ
2

The link efficiency is then equal to unity:

Po jI o j2 RL =2
ηT ¼ ¼ ¼1 ð3:35Þ
PS jI o j2 RL =2

This result is both encouraging and discouraging. It is encouraging because

Eq. (3.35) shows that if the system is ideal and has no parasitic resistance, and
even if the coupling is very weak (k << 1), there will be no loss, and this is what is
to be expected of an ideal system. It is discouraging exactly for the same reason: it is
3.2 Coupled-Coils and Modeling 41

clear that power is consumed by the primary coil even if there is no load resistance
(RL ¼ 0 Ω), and Eq. (3.35) simply means that the model is not accurate enough to
account for the loss due to electromagnetic radiation. Nevertheless, by recognizing
the limitation of a circuit model of the coupled-coils (as compared to using Maxwell
equations), we could still proceed to derive the case with parasitic resistance, and
obtain some insights of how power is transferred and how power is lost.

3.2.8 Design-Oriented Analysis of Coupled-Coils

with Parasitics

Let us consider the coupled-coils driving a resistive load RL with parasitic coil-
resistors R1 and R2 as shown in Fig. 3.6. We will follow a similar procedure of
computing the link voltage gain AT and the link efficiency ηT as for the ideal
coupled-coils. Design-oriented analysis is adopted in the sense that results are
presented in the form that help with designing and optimizing the system.
With reference to Fig. 3.6, the s-domain equations are

V S ¼ R1 I 1 þ V 1 ¼ ðR1 þ sL1 ÞI 1  sMI 2 ð3:36Þ

V 2 ¼ sMI 1  sL2 I 2 ¼ ðRL þ R2 ÞI 2 ð3:37Þ

Let the quality factor of the primary coil L1 driving its coil-resistor R1 be Q1; the
quality factor of the secondary coil L2 driving its coil-resistor R2 be Q2; and the
quality factor of the secondary coil L2 driving (RL + R2) be QS. They are thus given
as

ωL1 ωL2 ωL2

Q1 ¼ , Q2 ¼ , QS ¼ ð3:38Þ
R1 R2 RL þ R2

Note that for an efficient system the parasitic components should be very small
and the quality factors Q1 and Q2 should be very high, that is,

Q1 , Q2 >> QS ð3:39Þ

The reflected (or equivalent) impedance is given by (c.f. Eqs. (3.18) and (3.25))

ω2 M 2
Z eq ðsÞ ¼ ð3:40Þ
RL þ R2 þ sL2
k 2 QS 2
) Z eq ðjωÞ ¼ ðRL þ R2 Þð1  jQS Þ ð3:41Þ
n2 1 þ Q S 2

To compute the link voltage gain, express I1 in terms of I2 using Eq. (3.37) and
substitute the result into Eq. (3.36), then
42 3 Analysis of Coupled-Coils

Fig. 3.6 (a) The circuit of coupled-coils with parasitic resistances, and (b) the reflected
impedance model

 
RL þ R2 þ sL2
VS ¼ ðR1 þ sL1 Þ  sM I o ð3:42Þ
sM

Clearly, |Vo| ¼ |IoRL|, and with AT ¼ |Vo( jω)|/VS, we have

j jωMRL j
AT ¼ ð3:43Þ
j ðR1 þ jωL1 ÞðRL þ R2 þ jωL2 Þ þ ω2 M2 j

The above equation can also be expressed in terms of Q0 s, and a few lines of
arithmetic gives

knQ1 RL
AT ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
   2 ð3:44Þ
2 RL þ R2
1  1  k Q1 QS þ ðQ1 þ QS Þ
2

We may maximize AT w.r.t. RL by working out the following condition:

dAT
¼0 ð3:45Þ
dRL

Satisfying Eq. (3.45) requires RL to be negative, which means that there is no

feasible solution to Eq. (3.45). Hence, the minimum and the maximum AT occurs at
the boundary values, that is,

AT , min ¼ AT jRL ¼0 ¼ 0 ð3:46Þ

knQ1
AT , max ¼ AT jRL ¼1 ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð3:47Þ
1 þ Q1 2

To compute the link efficiency we follow the same procedure as in Sect. 3.2.7 by
noting that the load power is Po ¼ ½|Io|2RL, and IS can be expressed in terms of Io in
PST ¼ ½VSIS*, that is,
3.2 Coupled-Coils and Modeling 43

   
1 RL þ R2 þ jωL2 RL þ R2 þ jωL2 ∗ ∗
PST ¼ ðR1 þ jωL1 Þ  jωM I o  Io
2 jωM jωM
ð3:48Þ

Eq. (3.48) can be manipulated to read

     !
n2 1 n2 1 þ 1  k2 QS 2 jI o j2
PST ¼ RL þ R2 þ 2 1 þ 2 R1 þ j 2 2
ωL1 ð3:49Þ
k QS k QS 2

The link efficiency is then given by

Po 1
ηT ¼ ¼  ð3:50Þ
PS 1 þ n2 1 þ 1 2 R1 þ R2
2
k Q RL RL S

Although this circuit-model derivation cannot account for radiation loss,

Eq. (3.50) is very informative. First, let us consider a battery with internal resistance
Rbattery driving a load resistance RL, and note that Rbattery is in series with RL. It is
easy to derive that the efficiency is given by

1
η¼ Rbattery
ð3:51Þ
1þ RL

Let us consider Eq. (3.50) again. The effect of R2 on the efficiency is simply
similar to that of the internal resistance of a battery. However, the effect of R1 is
much worse. For an implantable medical device (IMD) powered through the
coupled-coils, the coupling coefficient k is usually very small, on the order of a
few percent, making the term with R1 very large, thus degrading the link efficiency.
Hence, it is of utmost importance to lower the parasitic resistance of the
primary coil.
The link efficiency ηT has been worked out in [3] (pp. 48–49). First, in the course
of derivation, a parameter R is defined as

k2
R¼ ð RL þ R2 Þ ð3:52Þ
n2

and the link efficiency is derived as

R L ω2 L 1 2 k 4
ηT ¼ ð3:53Þ
ðR þ R1 Þω2 L1 2 k4 þ R2 R1

Next, by substituting QL from Eq. (3.23) and Q1 and Q2 from Eq. (3.38), ηT is
computed to be
44 3 Analysis of Coupled-Coils

1
ηT ¼   ð3:54Þ
QL QL QL
1þ Q2 þ 1
k2 Q1 þ 1
Q1 QL þ 2
Q1 Q2 þ Q1 Q2 2

It can be shown that Eq. (3.54) is equivalent to Eq. (3.50), and the two underlined
terms are typographical mistakes in [3] that have been corrected above. Although
Eq. (3.54) is correct, it is not as useful as Eq. (3.50), which shows the immediate
relationships of RL, R1 and R2.
As a final remark of this section, we allege that the equations Eqs. (3.41), (3.44)
and (3.50) are useful for design because important information is revealed. For
example, Eq. (3.41) shows how the resistance combination RL + R2 of the secondary
circuit got reflected to the primary side, and how it is being reduced by the coupling
coefficient k and the turns-ratio n.

3.3 Resonant Coupled-Coils

For the majority of the wireless power transfer systems, capacitors are added to both
the primary-coil and the secondary-coil to resonate at the frequency of power
transmission. A capacitor can be added in series with or in parallel to the inductor,
and the coil, be it the primary or the secondary, can be made series-resonant or
parallel-resonant accordingly. In the majority of cases, the source would be a
voltage source VS that drives a series-resonant circuit. Hence, in the following
analysis, the primary side is assumed to have series resonance only.

3.3.1 Series-Series Resonant Coupled-Coils

If a capacitor is added in series with each of the primary-coil and the secondary-
coil, then we have a pair of series-series resonant coupled-coils (S-S coils), as
shown in Fig. 3.7.
With reference to Fig. 3.7, the s-domain equations are

V S ¼ ð1=sC1 þ R1 þ sL1 ÞI 1  sMI 2 ð3:55Þ

V 2 ¼ sMI 1  sL2 I 2 ¼ ðR2 þ 1=sC2 þ RL ÞI 2 ð3:56Þ

The equivalent impedance is given by

ω2 M 2
Z eq ðjωÞ ¼ ð3:57Þ
RL þ R2 þ 1=jωC2 þ jωL2
3.3 Resonant Coupled-Coils 45

Fig. 3.7 (a) The circuit of series-series resonant coupled-coils with parasitic resistances, and
(b) its reflected impedance model

It is clear that Zeq( jω) can be made real at the power-carrier frequency fo ¼ ωo/
2π if

1
pffiffiffiffiffiffiffiffiffiffi ¼ ωo ð3:58Þ
L2 C2

Next, we define the quality factors at ωo as

ωo L1 ωo L2 ωo L2
Q1 ¼ , Q2 ¼ , QS ¼ ð3:59Þ
R1 R2 RL þ R2

Then,

ω2o M2 k2
Z eq ðjωo Þ ¼ ¼ 2 Q s 2 ð R L þ R2 Þ ð3:60Þ
RL þ R2 n

From Eq. (3.56) we have

jωo M
I 2 ðjωo Þ ¼ I 1 ðjωo Þ ð3:61Þ
R L þ R2

By substituting Eq. (3.61) into Eq. (3.55) we have

 
1 ω2o M2
V S ¼ R1 þ þ jωo L1 þ I 1 ðjωo Þ ð3:62Þ
jωo C1 RL þ R2

Similarly, I1( jωo) can be made real at ωo if

1
pffiffiffiffiffiffiffiffiffiffi ¼ ωo ð3:63Þ
L1 C1

and
46 3 Analysis of Coupled-Coils

VS
I 1 ðjωo Þ ¼ ω2 M2
ð3:64Þ
R1 þ RLoþR2

It is worth noting that by setting 1/(L1C1)½ ¼ 1/(L2C2)½ ¼ ωo, the reflected

impedance of the secondary Zeq is purely real, and so is I1, but I2 is purely
imaginary.
Next, the link voltage gain AT can be computed by using Eqs. (3.61) and (3.62),
and
pffiffiffiffiffiffiffiffiffiffi
j V o j ωo k L1 L2 RL 1
AT ¼ ¼ ð3:65Þ
VS RL þ R2 R1 þ ω2o k2 L1 L2
RL þR2

The link voltage gain can then be rewritten as

knQ1 RL
AT ¼   ð3:66Þ
1 þ k Q 1 Q S R L þ R2
2

To compute the link efficiency ηT we note that the load power is Po ¼ ½|Io|2RL,
and the complex source power is PST ¼ ½VSIS*. A simple way to compute ηT is
again to make use of 1/(L1C1)½ ¼ 1/(L2C2)½ ¼ ωo and use Eq. (3.61) as follows:

V S I∗ 1
PST ¼ S
¼ ðR1 I 1  jωo MI2 ÞI ∗
1 ð3:67Þ
2 2
 
1 RL þ R2 RL þ R2 ∗
) PST ¼ R1  jωo M I o I ð3:68Þ
2 jωo M jωo M o
!
jI o j2 ðRL þ R2 Þ2
) PST ¼ PS ¼ RL þ R2 þ R1 ð3:69Þ
2 ω2o M2

Hence, the link efficiency is given by

Po 1
ηT ¼ ¼ ð3:70Þ
PS 1 þ n22 1 2 R1
RL þ RRL2
k Q S

By comparing Eq. (3.70) with Eq. (3.50), it is clear that the resonant circuit gives
a better link efficiency.
3.3 Resonant Coupled-Coils 47

Fig. 3.8 (a) The circuit of series-parallel resonant coupled-coils with parasitic resistances, and
(b) its reflected impedance model

3.3.2 Series-Parallel Resonant Coupled-Coils

If a capacitor is added in series with the primary-coil and a capacitor is added in

parallel to the secondary-coil, then we have a pair of series-parallel resonant
coupled-coils (S-P coils), as shown in Fig. 3.8.
With reference to Fig. 3.8, the s-domain equations are

V S ¼ ð1=sC1 þ R1 þ sL1 ÞI 1  sMI 2 ð3:71Þ

V 2 ¼ sMI 1  sL2 I 2 ¼ ðR2 þ 1=sC2 jjRL ÞI 2 ð3:72Þ
1=sC2 1
Io ¼ I2 ¼ I2 ð3:73Þ
1=sC2 þ RL 1 þ sC2 RL

The equivalent impedance is given by

ω2 M 2
Zeq ðsÞ ¼ ð3:74Þ
sL2 þ R2 þ 1=sC2 jj RL
ω2 M2 ð1 þ jωC2 RL Þ
) Zeq ðjωÞ ¼ ð3:75Þ
R2 þ RL ð1  ω2 L2 C2 Þ þ jωðL2 þ C2 R2 RL Þ

In [3], Zeq( jωr) is designed to be real by assigning the resonance frequency ωr to

be
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
u
u 1 1 1 L2
ωr ¼ t  ¼ pffiffiffiffiffiffiffiffiffiffi 1  ð3:76Þ
L2 C2 C22 R2L L2 C2 C2 R2L

The only advantage of this assignment is that Zeq( jωr) is real, but the disadvan-
tages are at least threefolds. First, ωr is load-dependent, and if the load (current or
resistance) changes, Zeq( jωr) will not be real anymore. Second, it will become
apparent later that the parallel-resonant secondary would be good for low-power
applications, and therefore, RL would be large or even very large, for example,
RL > 100 Ω or even larger than 1 kΩ. Hence, the factor L2/(C2RL2) would be much
smaller than 1 and can be ignored. Third, using Eq. (3.76) would make the
computation of AT and ηT unnecessarily complicated. Based on the above reasons,
it is advisable to follow the same assignment as Eq. (3.58), which is repeated below:
48 3 Analysis of Coupled-Coils

1
ωo ¼ pffiffiffiffiffiffiffiffiffiffi ð3:77Þ
L2 C2

The equivalent impedance at ωo is then equal to

ω2o M2 ðR2 þ ωo C2 RL ðωo L2 þ ωo C2 R2 RL Þ  jωo L2 Þ

Zeq ðjωo Þ ¼ ð3:78Þ
R22 þ ðωo L2 þ ωo C2 R2 RL Þ2

To further proceed with the computation good approximations have to be

instituted. Here, we assume that the output voltage is adequately filtered, which
requires that

ωo C2 RL >> 1 ð3:79Þ

Moreover, the load resistor RL is much larger than the parasitic resistor R2, that
is,

RL >> R2 ð3:80Þ

Finally, to further simplify the expression we note that ωoL2 ¼ 1/(ωoC2), and we
have

L2 ð ωo L 2 Þ 2
¼ ¼ Q2 QL ð3:81Þ
C2 R2 RL R2 R L

where the quality factors are defined as follows:

ωo L1 ωo L2 ωo L2
Q1 ¼ , Q2 ¼ , QL ¼ ð3:82Þ
R1 R2 RL

From the above assumptions the imaginary part is then negligible compared to
the real part, and assigning ωo ¼ 1/(L2C2)½ is a good choice. Next, the real part of
the reflected impedance is then given by

  ω2 M2  ω2o C2 RL  ð1 þ Q2 QL ÞC2 R2 RL
Req ¼ Re Z eq ðjωo Þ  o ð3:83Þ
ð1 þ Q2 QL Þ2 ðωo C2 R2 RL Þ2
ω2o M2
) Req  ð3:84Þ
ð1 þ Q2 QL ÞR2

Note that the equivalent resistance is a weak function of RL (the dependence is

only through the parameter (1 + Q2QL)). In fact, the reason is very simple: at ωo, RL
>> |1/jωoC2|, and the impedance of the parallel branch is approximated by a small
real part plus the impedance of the capacitor 1/( jωoC2), which is then cancelled by
3.3 Resonant Coupled-Coils 49

the impedance of the inductor jωoL2, leaving only the resistor R2 plus the small real
part, which is together given by (1 + Q2QL)R2.
The computation of the link voltage gain involves the primary coil, and similar
to the secondary coil, eliminating the imaginary part of the primary coil is load-
dependent, and we again adopt the simple assignment of

1
pffiffiffiffiffiffiffiffiffiffi ¼ ωo ð3:85Þ
L1 C1

Now, Eq. (3.71) is equal to

V S ¼ R1 I 1 ðjωo Þ  jωo MI 2 ðjωo Þ ð3:86Þ

From Eq. (3.72) we have

sL2 þ R2 þ 1=sC2 jj RL
I 1 ðsÞ ¼ I 2 ðsÞ ð3:87Þ
sM
R2 þ jωo ðL2 þ C2 R2 RL Þ
) I 1 ðjωo Þ ¼ I o ðjωo Þ ð3:88Þ
jωo M

Substituting Eq. (3.88) into Eq. (3.86) gives

 
R2 þ jωo ðL2 þ C2 R2 RL Þ
VS ¼ R1  jωo Mð1 þ jωo C2 RL Þ I o ðjωo Þ ð3:89Þ
jωo M

The link voltage gain AT ¼ |Io|RL/VS is

j jωo MRL j
AT ¼ ð3:90Þ
j R1 R2 þ jωo ðL2 þ C2 R2 RL ÞR1 þ ω2o M2 ð1 þ jωo C2 RL Þ j

With M ¼ k(L1 L2)½ we have

knQ1 RL =R2
AT ¼    ð3:91Þ
ω2o M2 ω2 M2 
1 þ R1 R2 þ R2 þ jωo C2 RL 1 þ Ro1 R2 
jωo L2

Recall ωoC2 ¼ 1/ωoL2, and Eq. (3.91) can be rewritten as

knQ1 Q2 =QL
AT ¼    ð3:92Þ
1 þ k Q1 Q2 þ jQ2 þ jQ1L 1 þ k2 Q1 Q2 
2

Note that QL << 1, and we have

50 3 Analysis of Coupled-Coils

knQ1 Q2
AT     ð3:93Þ
j 1 þ Q2 QL þ k2 Q1 Q2 
knQ1 Q2
) AT  ð3:94Þ
1 þ Q2 QL þ k2 Q1 Q2

The final task is to compute the link efficiency, with the load power Po ¼ ½|Io|2
RL and the complex source power PST ¼ ½VSI1*. Hence, using Eq. (3.73) we have
 
R2 þ jωo ðL2 þ C2 R2 RL Þ I o ðjωo Þ
PST ¼ R1  jωo Mð1 þ jωo C2 RL Þ
jωo M 2
R2  jωo ðL2 þ C2 R2 RL Þ
 I o ðjωo Þ∗ ð3:95Þ
jωo M

Now, the real part of PST is PS ¼ Re(PST), and

!
R22 þ ω2o ðL2 þ C2 R2 RL Þ2 jI o j2
PS ¼ R1 þ R 2 þ R L þ ω 2 2 2
C R R
o 2 L 2 ð3:96Þ
ω2o k2 L1 L2 2

By using the relations in Eqs. (3.79), (3.80) and (3.81), we have

!
R2L n2 ð1 þ Q2 QL Þ2 ðC2 R2 RL Þ2 jI o j2
PS  RL þ 2 2 R2 þ 2 R 1 ð3:97Þ
ωo L2 k L22 2

Finally, the link efficiency is given by

1= 2
2 jI o j RL 1
ηT ¼  2 ð3:98Þ
PS n2 ð1þQ2 QL Þ R1
1þ k2 Q22 Q2L RL þ Q12 R2
RL
L

3.4 Summary

In this chapter, a design-oriented analysis is used to analyze various coupled-coils

driving a resistive load. The configurations include the ideal coupled-coils, the
coupled-coils with parasitic resistors, the coupled-coils with series-resonant pri-
mary and series-resonant secondary, and the coupled-coils with series-resonant
primary and parallel-resonant secondary. For all the configurations, the reflected
(or equivalent) impedance, the link voltage gain and the link efficiency are com-
puted. All the expressions are written in a form that directly relates to the circuit
parameters such as k, n, R1, R2 and RL, and hence are useful for the design and
optimization of the coupled-coils.
References 51

References

1. Ko WH, Liang SP, Fung CDF (1977) Design of radio-frequency powered coils for implant
instruments. Med Biol Eng Comput 15:634–640
2. Fuller JW (1968) Apparatus for efficient power transfer through a tissue barrier. IEEE Trans
Biomed Eng:63–65
3. van Schuylenbergh K, Puers R (2009) Inductive powering. Springer, Dordrecht
4. Irwin JD, Kerns DV Jr (1995) Introduction to electrical engineering. Prentice Hall, New York
5. Hart DW (2011) Power electronics. McGraw Hill, New York
Chapter 4
Circuit Design of CMOS Rectifiers

Abstract This chapter discusses the design considerations and the state-of-the-art
designs of CMOS rectifiers for wireless power receivers. First, the forward current
conduction capability and the reverse leakage current of on-chip passive diodes are
investigated and compared. Next, comparator-based active rectifiers for near-field
WPT solutions are discussed and demonstrated with a couple of design examples.
Moreover, a near-optimal adaptive on- and off-delay compensation technique is
introduced. Other rectifier topologies, such as the delay-locked-loop (DLL) based
rectifier and the threshold-voltage compensated rectifier, are also discussed. In
addition, rectifiers for RF energy harvesting for far-field WPT are discussed as well.

Keywords Wireless power transfer • AC-DC conversion • Rectifier • Comparator •

Delay • RF-DC • Energy harvesting

4.1 Introduction

Wireless power transfer (WPT) has a wide range of applications (from low to high
power levels) including radio frequency identification (RFID), implantable medical
devices (IMDs), and wireless chargers for portable and wearable devices, and for
electric vehicles (EVs). As mentioned in Chap. 1, at different power levels, the
considerations on circuit design and device selection can be very different. The
focus of this book is on the designs of low to medium power level (<10 W) WPT
systems that can be realized in standard CMOS technologies.
The performance of the WPT receiver limits the output power of the whole
system, and many works have been focused on the WPT receiver design. Note that
the rectifier is a critical part in the receiver chip. For IMD applications, the form
factor of the power receiver is one of the principal concerns because these devices
have to be as non-invasive as possible. For output power level in the milli-watt
range, full on-chip integration is realizable and thus favorable with the elimination
of discrete components [1]. For consumer electronics that cater for portable or
wearable devices, for example, wireless chargers for mobile phones or tablet
computers, the power level is around 10 W. For EV power management, fast-
charging the automotive battery system needs very high power in the kilo-watt
range, and discrete diodes/transistors fabricated by dedicated processes such as the

© Springer Nature Singapore Pte Ltd. 2018 53

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_4
54 4 Circuit Design of CMOS Rectifiers

Fig. 4.1 Schematics of (a) the half-wave rectifier and (b) the full-wave rectifier

III-V direct bandgap Gallium Nitride (GaN) or the laterally diffused MOSFET
(LDMOS) processes are commonly employed. Hence, circuit designers are facing
the challenges of designing wireless power transfer systems that could range from
milli-watt to kilo-watt. For applications of 10 W or lower, the rectifier is preferred
to be fully integrated on-chip to avoid using discrete Schottky diodes, and thus
saves the circuit board area. For high-power and/or high-voltage applications, GaN
devices are popular to provide higher conversion efficiencies, and LDMOS tran-
sistors are essential for high-voltage operation.
In WPT receiver and RF energy-harvesting systems, the input AC sources have
to be converted into DC sources to power up downstream electronics, which
necessitates the process of rectification. Diodes, the simplest semiconductor devices
that only allow the current to flow in one direction and block it from flowing in the
reverse direction, are commonly used to convert AC power into DC power as
shown in Fig. 4.1. Figure 4.1a shows a half-wave rectifier, with one terminal of
the AC source (VAC2) tied to ground. For the half cycle when VAC1 is higher than
VAC2, the diode D1 will conduct when VAC1 goes higher than the DC output voltage
VDC; and for the half cycle when VAC1 is lower than VAC2, D1 is reverse-biased for
sure. Hence, the half-wave rectifier delivers current from the AC source to the DC
output VDC only once in every cycle. Figure 4.1b shows a full-wave rectifier. First,
consider the half-cycle when VAC1 is higher than VAC2. The diodes D1 and D4 will
conduct when VAC1–VAC2 is higher than VDC. Next, consider the half-cycle when
VAC1 is lower than VAC2, and D2 and D3 will conduct when VAC2–VAC1 is higher
than VDC. Hence, the full-wave rectifier delivers current to the output at both the
positive and the negative peaks of VAC ¼ VAC1  VAC2. This means that the time
interval for charge transfer of a full-wave rectifier is only half of that of a half-wave
rectifier. Therefore, in delivering the same load currents with the same value of
output capacitors, the output voltage ripple of a half-wave rectifier is basically two
times that of a full-wave rectifier. In addition, the peak amplitude of the pulse
current conducted through a half-wave rectifier is roughly doubled compared to that
4.2 Diodes and Diode-Connected Transistors 55

Fig. 4.2 A reconfigurable rectifier (universal rectifier) with 1X (rectifier) mode and 2X (voltage
doubler) mode

of a full-wave rectifier, while higher peak current may result in higher conduction
loss from the diode.
Ideally, the voltage difference between the two terminals VAC ¼ VAC1  VAC2 is
a sinusoidal wave; but it could be a distorted sinusoidal wave in practice, which will
be discussed later in this chapter.
Figure 4.2 shows a passive reconfigurable rectifier (universal rectifier) with 1X
(rectifier) mode and 2X (voltage doubler) mode. It is commonly installed in
electrical appliances that are designed to work in different countries with AC supply
voltages of either 220 VRMS or 110 VRMS. The reconfigurable rectifier also found its
use in WPT applications. To cater for coupling coefficient k variations with distance
and/or orientation of the coupled-coils, a reconfigurable rectifier may be employed
to increase VDC without increasing the transmitted power. Examples can be found
from the loosely coupled inductive power link with active rectifiers to extend the
coupling range [2, 3]. It may also be used to modulate the input impedance of the
WPT receiver, as in the ideal cases, the input impedance of the 1X mode is four
times that of the 2X mode when driving the same resistive load. It is because the 2X
mode generates twice the output voltage, and with a fixed load resistor, the power
consumed is four times that of the 1X mode, and hence the current from VAC is four
times that of the 1X mode. This change in impedance should also be taken into
consideration when designing the matching network.
This chapter starts with introducing the basic rectifier topologies and selecting
diodes and diode-connected transistors. Emphases are focused on active rectifier
designs that are low-cost high-efficiency solutions for various low-power applica-
tions. Rectifiers for RF energy harvesting are discussed as well.

4.2 Diodes and Diode-Connected Transistors

Figure 4.3 shows the diodes and the diode-connected transistors that are available in
standard CMOS processes. The P+/N-well junction diode is readily available in
CMOS processes, because the N-well can be connected to any potential higher than
the ground potential. However, the parasitic PN junction (N-well to substrate) may
affect high-frequency performance of the circuit and may also introduce DC
leakage current.
56 4 Circuit Design of CMOS Rectifiers

Fig. 4.3 Symbols and schematics of (a) normal PN junction diode, (b) Schottky diode, (c) diode-
connected PMOS, (d) diode-connected NMOS, and (e) composite CMOS diode

A Schottky diode, as shown in Fig. 4.3b, is formed by the junction between a

semiconductor and a metal. It has low forward voltage drop and achieves fast
switching. Schottky diodes have been widely used in conventional discrete-type
AC-DC converters for rectification, and are still in use for various low-voltage high-
power applications. Although the process of making Schottky diodes is compatible
with CMOS processes, additional masks are needed that increase the
manufacturing cost.
Alternatively, PN junction diodes may be replaced by diode-connected transis-
tors as shown in Fig. 4.3c and 4.3d. A PMOS diode-connected transistor is called a
PMOS diode, and an NMOS diode-connected transistor is called an NMOS diode.
They could be used to implement a cost-effective passive rectifier. It should be
noted in rectifier designs the body bias of the diode-connected MOSFET should be
connected to its drain terminal as shown in the figure, to make sure that the parasitic
diode has the same polarity as the MOS diode; otherwise, the parasitic diode will be
forward biased when a reverse voltage is applied, and large reverse current will
flow. This body bias connection is different from that in a usual analog circuit.
Performance comparison of different diodes can be evaluated by their on/off
current ratios; and to compare the turn-off scenarios of different diodes, we need to
study the I-V characteristic of MOS transistors working in the sub-threshold region.
For an NMOS transistor, the sub-threshold I-V characteristic is given by

VGS 
I D ¼ I 0 e ζVT  1 , ð4:1Þ

where ζ > 1 is the non-ideality factor, VGS is the gate-to-source voltage, and
VT ¼ kT/q is the thermal voltage. The non-ideality factor ζ for a PN junction
diode is usually lower than that of a MOS transistor, and therefore results in a larger
exponential ID/VD relationship. With a typical value of ζ, VGS has to decrease by
4.2 Diodes and Diode-Connected Transistors 57

roughly 80 mV for ID to decrease by one decade at room temperature [4]. If

low-threshold voltage transistors are used to give a lower VGS, the reverse leakage
current would increase exponentially.
Consider the case when the wirelessly transmitted power is discontinued, the
energy stored in the devices will be drained by leakage currents and thus the stand-
by time would be reduced. The reverse leakage current of an NMOS diode is given
by
 
jV GS jþV TH jV DS j
ID ¼ I0 e ζV T
1e VT
, ð4:2Þ

Where VTN is the threshold voltage and VDS is the drain-to-source voltage.
Obviously, the reverse leakage current has an exponential relationship with two
parameters: VGS and VDS. In a diode-connect MOSFET, VGS ¼ VDS. If short-
channel transistors in an advanced process are employed to increase the conducting
current capability and to reduce the parasitic components, the reverse leakage
current will also be increased, because the shorter channels are relatively easier to
be depleted with a lower |VDS|, and the charge carriers will then shoot through the
channel. Since the MOS diode and its parasitic junction diode are in parallel, the
reverse leakage current of a MOS diode consists of two parts: the leakage current
through the channel, and the leakage current through the parasitic junction diode.
The second part is much smaller than the first part because the junction area is small
and the channel is short.
Figure 4.4a shows the simulated I-V curve of a diode-connected 1.8 V PMOS
diode with ten fingers of W ¼ 10 μm and L ¼ 0.2 μm. When the reverse bias is
small, the I-V curve follows Eq. (4.2). When the reverse bias is lower than 2 V, in
this case, the channel starts to be depleted, and the reverse current starts to increase
significantly. In the forward conduction region, the forward current of the PMOS
diode increases significantly when the parasitic junction diode is turned on at
VD > 0.8 V.
To reduce the reverse leakage current of a MOS diode, a composite CMOS diode
as shown in Fig. 4.3e was proposed in [5], and has been applied in low-power
CMOS rectifier designs [6, 7]. The simulated I-V curve of the composite CMOS
diode is shown in both Fig. 4.4a and 4.4b and compared with other diodes. In the
forward-bias mode, the composite CMOS diode can be regarded as two serially
connected forward-bias NMOS and PMOS diodes. The forward current is thus
comparable to that of the PN junction diode (on the same order of magnitude).
When the composite CMOS diode is reversely biased, both transistors operate with
negative |VGS| in the accumulation region. Starting from |VDS| ¼ 0 V, the reverse
current increases initially as VDS goes negative, due to the factor (1  e|VDS|/VT).
However, as the reverse bias goes further negative, the reverse current is then
dominated by the e|VGS|/ζVT term, and decreases with a slope of less than
200 mV per decade. Note that for both the PMOS and the NMOS transistors,
their |VDS| are roughly half of their |VGS| because
58 4 Circuit Design of CMOS Rectifiers

Fig. 4.4 Comparisons of the I-V characteristics (a) between PMOS diode and composite CMOS
diode, and (b) between Schottky diode, composite CMOS diode, and normal PN junction diode

jV DSN j þ jV DSP j ¼ jV GSN j ¼ jV GSP j: ð4:3Þ

This is different from the case of the simple PMOS and NMOS diodes, where
VDS is always equal to VGS. As can be explained by Eq. (4.2), this leads to a low
leakage solution by limiting one of the exponential factors (e|VDS|/VT). When a
reverse-bias voltage of some hundreds of milli-Volts is applied, the reverse leakage
current of a composite CMOS diode is as low as the junction leakage current.
4.3 Comparator-Based Active Rectifiers 59

4.3 Comparator-Based Active Rectifiers

For applications with power level higher than mW, using diode-connected transis-
tors may not achieve high efficiency, because their |VGS| can only be slightly higher,
say by 100 mV, than their |VTH|, and result in large chip area. Instead, active diodes
that are essentially comparator-controlled MOSFETs can be used to replace the
passive diodes in a passive rectifier, and to form an active rectifier, as shown in
Fig. 4.5. Active diodes have low forward voltage and thus low loss, and are
particularly important for low input voltage applications. In addition, a fully-
integrated active rectifier reduces the number of discrete components needed and
thus reduces the system cost.
Two important benchmark parameters in evaluating active rectifiers are the
voltage conversion ratio M and the power conversion efficiency PCE. The voltage
conversion ratio is defined as

V DC
M¼ , ð4:4Þ
jV AC j

where |VAC| is the amplitude of the input AC signal to the rectifier, and VDC is the
averaged rectified output DC voltage. The power conversion efficiency of an
AC-DC converter is defined as

POUT V 2 =RL
PCE ¼ ¼ R t0 þNT DC ð4:5Þ
PIN 1
NT t0 V AC ðtÞ  I AC ðtÞdt,

where T is the period of the input sinusoidal wave, N is the number of cycles that are
integrated for PIN calculation, and VAC(t) and IAC(t) are the instantaneous voltage
and current of the AC source.
For the passive rectifiers, as discussed in Sect. 4.2, both the voltage conversion
ratio and the power conversion efficiency are low because the forward voltage drop
VD of a PN junction diode is around 0.6–0.7 V, and that of a Schottky diode is
around 0.15–0.45 V. An active rectifier that only uses CMOS transistors is shown in
Fig. 4.6. The two high-side diodes in the passive full-wave rectifier that shown in

Fig. 4.5 PMOS and NMOS active diodes

60 4 Circuit Design of CMOS Rectifiers

Fig. 4.6 (a) An active full-wave rectifier with (b) simulated AC voltage and current waveforms
showing the reverse current problem in active rectifier

Fig. 4.1b are replaced by two cross-coupled PMOS transistors, and the low-side
diodes are replaced by two comparator-controlled NMOS switches (active diodes).
In this configuration, the forward voltage drops are reduced from 2VD to 2VDS,
where VDS is the turn-on voltage (that is equal to the drain-to-source voltage) of the
power switches.
The operation principle of the active full-wave rectifier can be described as
follows. Assume the process starts with VAC1 going down and VAC2 going up. When
4.3 Comparator-Based Active Rectifiers 61

VAC2  VAC1 > |VTHP| (threshold voltage of MP1,2), MP1 is turned on and therefore
VAC2 ¼ VDC. Then VAC1 swings below the ground voltage, the comparator CMP1
turns on the switch MN1, and IAC1 charges up VDC through the AC source. After VAC
reaches its low peak point, VAC1 starts to go up. When VAC1 swings above zero, MN1
is then turned off by CMP1, finishing one half cycle of the full-wave rectification
period. During the next half of the AC input cycle, the other half of the rectification
circuit will conduct in a similar fashion as described above. Thus, by replacing the
four diodes of a full-wave rectifier with power transistors, M can be significantly
increased especially when the input amplitude is low. However, when operating at a
high frequency, such as 13.56 MHz, the comparator delay and the gate-drive buffer
delay would affect the efficiency of the rectifier. As demonstrated by the simulated
IAC waveforms, the reverse current will occur if the large power switches are not
turned off immediately when VAC1 or VAC2 is higher than the ground voltage.
In this architecture, the main losses include the conduction loss and the
switching loss of the power transistors, and the static power loss of the comparator.
In terms of power loss and PCE, the extra loss caused by the reverse current is
already included in the above mentioned conduction loss, as the energy goes from
the DC output back to the AC input is recycled. But in terms of energy extraction
from the source, the reverse current obviously reduces the maximum power that can
be extracted from the source. From either of the perspectives, the reverse current
should be eliminated.
A simple example of a comparator-based active diode is shown in Fig. 4.7
[8]. The two comparators CMP1 and CMP2 are common-gate push-pull
differential-input comparators, with the bias currents provided by M7 and M8. As
described above, when VAC2 – VAC1 > |VTHP|, MP2 is turned on, and VAC1 keeps
going down. When VAC1 swings below 0 V, M1 of CMP1 sinks a larger current than
M2 does. As M4 is diode-connected, therefore, V2 drops with VAC1, and reduces
VGS3. The current of M1 is mirrored to M6 through M5, causing M6 to source a
larger current than M3 can sink, thus driving VOUT as well as VGN1 high and turns on
the active-diode switch MN1. In the other half cycle, VAC1 goes up and VAC2 goes
down, then MN2 will be turned on in a similar manner and conducts current from
ground to VOUT through the AC source.

4.3.1 Delay Compensation Schemes

Due to the speed of the comparator and the gate-drive buffer, the propagation delay
of the rising edge (from low to high, tpLH) will shorten the current conduction time
Δt, limiting the highest operation frequency of the active rectifier. On the other
hand, the propagation delay of the falling edge (from high to low, tpHL) forces the
power NMOS transistors MN1,2 to be turned off late, and the charge of the output
capacitor will flow back to ground through MN1,2, resulting in reverse conduction
current. Moreover, MN1,2 have to be large to handle a large output current,
62 4 Circuit Design of CMOS Rectifiers

Fig. 4.7 A comparator-based active diode with push-pull common-gate differential input pairs

increasing the response time of the active diodes. This problem is more pronounced
when the operation frequency is high (for example, 13.56 MHz) and the input
amplitude |VAC| is low (for example, below 1.5 V), because delay time of compar-
ators and buffers are inversely proportional to the supply voltage.
Many schemes have been proposed to compensate for the delays of the active
diodes [8–17]. Comparators with unbalanced bias currents or asymmetric differen-
tial inputs are used to set an artificial input offset voltage to compensate for the
delay and to turn the power switches on and off properly. Prior comparator offset-
control schemes for reverse current control fall into one of the cases sketched in
Fig. 4.8.
Figure 4.8a shows the circuit symbol of an artificial input offset circuit with an
Enable pin. The operation is as follows: when the Enable bit is high, a non-zero
offset voltage is added (to the comparator); and when the Enable bit is low, the
offset voltage is zero, which means that the symbol represents a shorted wire. To get
familiar with the defined symbol, the well-known hysteretic comparator is given in
Fig. 4.8b, for showing a complementary example to the delay compensation
schemes given in Fig. 4.8c. When the hysteretic comparator just switches to output
a “0” (or “1”), a positive offset will be added to its negative (or positive) input
terminal, such that the hysteretic comparator output is relatively more difficult to be
switched back over to “1” (or “0”) due to jitters. For the delay compensation
schemes, it is the other way round, as discussed in details below.
Consider the case when VAC1 is swinging down initially. In Case 0, the compar-
ator has no added offset, and thus there is reverse current due to delays. In Case
1, an offset voltage of +VOS1 is added between V of the comparator and VAC1.
When VAC1 swings down to 0 V, V is still at +VOS1, and it takes some time before
4.3 Comparator-Based Active Rectifiers 63

Fig. 4.8 (a) Symbol of the switched-offset circuit for comparator delay compensation, and
schematics of (b) the hysteretic comparator and (c) comparator offset-control schemes for reverse
current control

V swings to 0 V and VGN1 trips. Hence, VGN1 is switched high later than without
+VOS1. After VAC1 reaches the lowest voltage, it swings back up. Due to the offset
voltage, V reaches 0 V earlier than VAC1 and hence, VGN1 is switched low earlier.
If +VOS1 is designed correctly, reverse conduction can be prevented; but note that
MN1 is turned on later than required. In Case 2, +VOS1 is added only when VGN1 is
high, and hence the timing of turning on MN1 is the same as if no +VOS1 is added. In
Case 3, besides adding +VOS1 to V, a second offset voltage +VOS2 is added
between V+ of the comparator and Gnd. When +VOS2 is added, VGN1 is switched
high earlier, and +VOS2 is added only when VGN1 is low. If the offset voltage levels
are designed correctly, both the rising edge delay and the falling edge delay can be
compensated.
64 4 Circuit Design of CMOS Rectifiers

To evaluate different comparator offset-control schemes on the performance of

the corresponding active rectifiers, the parameter Crest Factor (CF) that used in
evaluating electrical appliances and also used in signal analyses could be employed.
The crest factor is defined as the ratio of the peak load current to its RMS (root mean
square) value, that is,

IP
CF ¼ : ð4:6Þ
I RMS

A DC current has the minimum CF of 1. A higher CF means a higher peak

current for the same average load current, resulting in a larger I2R conduction loss.
Hence, for a load current profile that has a high CF, larger power transistors are
needed to achieve a high voltage conversion ratio. Routing metal wires have to be
wider as well. The cresting factors of the above cases are considered below.
The scenarios of current conduction of Case 0 to Case 3 are sketched in Fig. 4.9,
and discussed as follows. Case 1 was implemented in [9], with constant offset
introduced to the comparators using unbalanced bias currents. The power NMOS
switches are turned off earlier by td to eliminate the reverse current; however, they
are turned on later by 2td than the ideal case, and the conduction time Δt1 is 2td
shorter. For the same load current, the peak current Ip1 has to be higher, limiting its
operation at a higher frequency. The effects of the delays get worse when the AC
input amplitude |VAC| is low.
In [8], self-biased active diodes were employed, and to reduce or eliminate td, a
reverse current control (RCC) scheme (Case 2) is introduced as shown in Fig. 4.10.
M9 serves as the RCC switch, which is turned on together with the active diode. The
bias current of this active diode is determined by two diode-connected transistors
M3 and M5, and thus both the bias current and the operation of the RCC transistor
are highly affected by |VAC| and process variations, making the rectifier hard to be
optimized over a wide input range. Moreover, as the reverse current control is
realized by a time-varying offset, the artificial offset would disappear right after the
power NMOS transistor is turned off. If the RCC switch turns on prematurely (for
example, due to process variations) and turns off the active diode while |VAC| is still
higher than VDC, the comparator will go high again in the same cycle. Simulation
waveforms of the described scenario are shown in Fig. 4.11. This multiple-pulsing
problem incurs larger switching loss, especially in light-load condition when
switching loss dominates, and the efficiency is reduced. The remedy is to use SR
latches that allow only one switch-on per cycle [10] and the details are to be
discussed in Sect. 4.3.4.
Case 3 was realized in [11], with an offset-control circuit to control the com-
parators to compensate for both turn-on and turn-off delays such that Δt3 could be
maximized (to achieve the lowest CF). However, it suffers from the same and even
worse multiple-pulsing problem as [8], as the dynamic offset (+/ offset voltages)
transition of the offset-control circuit is unstable: when the comparator outputs a
“1” (or “0”), the dynamic offset flips the output to “0” (or “1”), and this positive
feedback makes the comparator undergoes self-oscillation. This phenomenon is
4.3 Comparator-Based Active Rectifiers 65

Fig. 4.9 Conceptual waveforms of the voltages and conducted currents for active rectifiers with
different comparator delay compensation schemes

what a hysteretic comparator is designed to avoid. To make the scheme work, a

delay cell tdp in the offset-control path is added in [11]. If the delay time tdp is large
enough (comparable to Δt), the comparator could be stable, but then the power
switch would be turned on for at least the duration of tdp that limits the minimum
conduction time (Δtmin > tdp). This property makes its operation more like a
66 4 Circuit Design of CMOS Rectifiers

Fig. 4.10 A self-biased

active diode with reverse
current control

Fig. 4.11 Simulated waveforms of the multiple-pulsing problem associated with dynamic offset
schemes

constant on-time control at light-load condition. As a result, its light-load efficiency

is degraded.
Recently, Case 3 was also realized in [16] with more comprehensive consider-
ations. Figure 4.12 shows a near-optimum switched-offset compensation scheme
implemented for both on- and off-delays with additional sample-and-hold (S&H)
voltage-sensing feedback loops. The values of VAC1 at both turn-on and turn-off
points of the active diodes are sampled on respective sampling capacitors CSAMPLE
of the feedback loops. The values of the offset voltages for optimum turn-on/off
timing control are then automatically adjusted by the outputs of the operational
transconductance amplifiers (OTAs). As such, the optimum comparator offset will
be gradually and automatically adjusted according to the AC input amplitude, WPT
frequency, bias current, and load current conditions etc. Furthermore, to avoid the
multiple-pulsing problem, a hard one-shot logic that allows the power transistors to
turn on only once per cycle is installed. Consequently, zero-voltage switching
4.3 Comparator-Based Active Rectifiers 67

Fig. 4.12 Case 3: Active diode with additional feedback loops for near-optimum offset control

(ZVS) of the power transistors is realized, and the reverse current in [16] is
eliminated elegantly.
To summarize, Case 2 has longer Δt than Case 1, and Case 3 has the largest Δt in
the ideal situation. However, a comparator with both compensated turn-on and turn-
off delays is logically unstable: the hysteresis goes the opposite direction as a
normal hysteretic comparator goes, and the robustness of the rectifier is degraded,
and special logic blocks are needed to achieve a stable operation. Last but not least,
the recent solution implemented in [16, 17] with on/off-delay sampled control
loop solves the reverse current problem with additional circuit blocks.

4.3.2 Delay Time Analysis of Active Diodes

One aspect of active rectifier design that has not yet been discussed is its bias
current generation circuit. But before discussing the current source to be used to
bias CMP1 and CMP2, let us investigate the delay time of the active diode td,AD
first.
The active-diode delay td,AD consists of the comparator delay td,C and the gate-
drive buffer delay td,B. To simplify the calculation, as shown in Fig. 4.13, the supply
voltage of a typical comparator and buffer is connected to VDC that is AC input
dependent, and the input signal is assumed to be sinusoidal, that is, VIN(t) ¼ α|
VAC|  sin(2πt/T ), where α is a scaling factor. Let the trip point of the inverter
buffer be the 50% point of VDC, that is, M|VAC|/2 (M  0.9). Consider the
comparator output capacitor COUT. The charging/discharging current ICD(t) of
COUT can be approximated by the small-signal model current as
68 4 Circuit Design of CMOS Rectifiers

Fig. 4.13 Simplified

schematic of active diode
1 with emphasis on supply
voltage, input signal and
load capacitor for delay
calculations

I CD ðtÞ ¼ gm V in ðtÞ ¼ gm αjV AC j sin ð2πt=T Þ, ð4:7Þ

where gm is the transconductance of the comparator input stage. The comparator

delay td,C is the time that ICD(t) charges COUT from 0 V to VDC/2:
R td, c Rt
I CD ðtÞdt ¼ 0d, c gm αjV AC j sin ð2πt=T Þdt
0 ð4:8Þ
¼ COUT V DC =2 ¼ COUT MjV AC j=2:

For t << T, sin(2πt/T )  2πt/T, and we have

1
g αjV AC j2πt2d, C =T ¼ COUT MjV AC j=2: ð4:9Þ
2 m

Therefore,
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
MCOUT T MCOUT T
td, C ¼ ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi: ð4:10Þ
2παgm 2πα 2I B kn ðW=LÞ
pffiffiffiffiffiffiffiffiffiffi
From (4.10), we have td, C / 4 1=I B . If IB is independent of VDC, then so does td,
C. The simulated td,C of Fig. 4.13 is plotted in Fig. 4.14, which verified the above
calculations that td,C has a very weak dependence on IB. Assume that the bias
current generation circuit would provide an IB that is more or less proportional to
VDC, then in such a case,
p ffiffiffiffiffiffiffiffiffiffi p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
td, C / 4
1=I B / 4 1=jV AC j: ð4:11Þ
4.3 Comparator-Based Active Rectifiers 69

Fig. 4.14 Simulated active

diode delay td,AD,
comparator delay td,C and
gate drive buffer delay td,B
with respect to |VAC|

On the other hand, the buffer delay td,B would change inversely proportional to
the supply voltage, according to the calculated propagation delay tP (the time to
reach the 50% point) of an inverter [18]:
 
3 CL V DC 7
tP ¼ 0:69 1  λV DC
4 I DS 9 
7 ð4:12Þ
CL V DC 1  λV DC
9
¼ 0:52 0 ,
k ðW=LÞV DSAT ðV DC  V TH  V DSAT =2Þ

where IDS is the drain current, k0 ¼ μCox, VTH is the threshold voltage, λ is the
channel-length modulation factor, and CL is the parasitic gate capacitance of the
power transistor MN1. Assuming that VDC >> VTH, VDSAT ¼ VDC – VTH, and λ ¼ 0,
Eq. (4.12) can be written as

2CL
tP ¼ td, B  : ð4:13Þ
k0 ðW=LÞV DC

From the above first-order approximation, we learn that td,B is approximately

inversely proportional to the supply voltage. As previously mentioned, delay
compensation of the comparator is realized by introducing an input offset voltage
such that the power transistor is turned on and off earlier. Similarly, to better
compensate for td,B, we need an adaptive current source that is approximately
inversely proportional to VDC. Although the first-order model could provide insight
into the operation of the circuit to determine the dominant parameters, trial-and-
error simulations have to be conducted in practical designs.
70 4 Circuit Design of CMOS Rectifiers

4.3.3 Biasing Circuits of Active Rectifiers

For a WPT receiver, the active rectifier has to start working first before the
subsequent circuits could work. Therefore, for a robust design, the biasing circuit
of the active rectifier should be self-started and not require a start-up circuit.
Moreover, a start-up circuit consumes quiescent current even when it finishes its
job and is cut open from the main circuit, and thus affects the efficiency. Hence, the
commonly used supply-insensitive Widlar current source may not be the best
candidate for biasing the active rectifier in a WPT receiver.
Figure 4.15 shows a few biasing circuits without the need of a start-up circuit
that were used in WPT receivers [2, 8–16]. In [2, 9], a simple current source that is
formed by a diode-connected MOS transistor driving a resistor is used; and in
[8, 11, 12], self-biased current sources are used. For the above schemes, the bias
current is approximately proportional to the input voltage amplitude |VAC|. In
[10, 15, 16], the peaking current source (PCS) is used to bias the comparators so
that the bias current would stay approximately constant when |VAC| changes.
The bipolar peaking current source was invented in [19], and the CMOS peaking
current source was discussed in [20]. The frequency response of the CMOS PCS
was compared with the Widlar current source in [21]. With reference to Fig. 4.15c,
it is easily shown that I1 and IB are given by
 
V DD  V GS1 1 W
I1 ¼ ¼ kn ðV GS1  V THN Þ2 ð4:14Þ
RB 2 L 1
 
1 W
IB ¼ kn ðV GS1  V THN  I 1 R1 Þ2 : ð4:15Þ
2 L 2

For IB to be insensitive to the change of I1, we set dIB/dI1 to zero, and using
(4.14) and (4.15), the condition for locating the maxima is

1
I 1 R1 ¼ ðV GS1  V THN Þ, ð4:16Þ
2

and the bias current peaks at the nominal VDC that we use to calculate I1, that is,
I1 ¼ (VDC,nom  VGS1)/RB. A simple assignment is to set (W/L)2 ¼ 4(W/L )1 to give
IB ¼ I1.
However, as previously mentioned, for a constant td,AD over a wide range of AC
input amplitude, the bias current of the active diode should be approximately
inversely proportional to |VAC|. In the open-loop designs of [3, 14], to further
improve the performance at low |VAC| a dual-peaking current source was used, as
shown in Fig. 4.16b. By setting the transistor size ratios among MN1, MN2 and MN3
appropriately, the bias current can be set to be quasi-inversely proportional to |VAC|
(VDC) as shown in Fig. 4.16c, labeled as a QIPV bias, or can be set to a bias
current that is more insensitive to supply variations as shown in Fig. 4.16d. By using
the QIPV bias, the comparator offset could be well controlled over the whole AC
4.3 Comparator-Based Active Rectifiers 71

Fig. 4.15 Biasing circuits without start-up requirement: (a) resistor-based biasing, (b) diode-
connencted transistor biasing, and (c) peaking current source

input range, because a larger bias current at low VDC will increase the comparator
speed, and also generate a larger comparator offset for delay compensation.
To realize a bias current that is inversely proportional to VDC, one may set the
peak current point to be the lowest VDC in the application, such as the IB1 in
Fig. 4.16c. However, due to the square relation, the bias current will drop too
much at the highest VDC. Therefore, a dual-peaking current biasing circuit was
proposed [3, 14]. The resistor R1 in Fig. 4.16a is split into R1A and R1B. Two output
currents (IB1 and IB2) can be set with different peak current points and be summed
together through MP1. In doing so, no additional current branch is needed. The peak
current point of IB1 (VPEAK1) is set to be near the lowest VDC, while the peak current
point of IB2 (VPEAK2) is set to be near the higher end of the VDC range. IB2 is used to
compensate IB1 at the high end of the VDC range when it drops significantly. The
peak currents of IB1 and IB2 can be calculated by

  "sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi #2
1 W 2I 11
I B1, PEAK ¼ kn  I 11 ðR1A þ R1B Þ , ð4:17Þ
2 L 2 kn ðW=LÞ1
  "sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi #2
1 W 2I 12
I B2, PEAK ¼ kn  I 12 R1A , ð4:18Þ
2 L 3 kn ðW=LÞ1

where I11 is the value of I1 at VPEAK1, and I12 is the value of I1 at VPEAK2.
72 4 Circuit Design of CMOS Rectifiers

Fig. 4.16 Schematics of (a) the peaking current source, and (b) the dual-peaking current biasing
circuits for (c) inversely proportional to supply bias current and (d) more insensitive to supply bias
current

Basically, by tuning the peaking points of these two currents and the transistor
sizes of MN2 and MN3, the final output bias current IB can be designed to many other
shapes if needed. Another benefit of using the PCS is to have a well-controlled
quiescent current over a wide supply range.

4.3.4 Full-Wave Rectifier Design Examples

Two full-wave active rectifiers with the Case 2 switched-offset comparator delay
compensation scheme have been designed, implemented, and measured in a
0.35 μm CMOS N-well process. The first one (labeled as Rec1) [10] used a peaking
current source, while the second one (Rec2) [14] used the proposed quasi-inversely
proportional to VDC (QIPV) current bias. Detailed analysis, optimization and
measurement results will be presented in this sub-section.
The schematic of the NMOS active diode is shown in Fig. 4.17. Time-varying
offset is introduced to the comparator by dynamic switched biasing currents from
M9 and M10 that are implemented in a push-pull fashion.
Note that VSW of CMP1 can be equal to “1” only when VGN1 is “0” and VGN2 is
“1”. Assume that VGN2 is “1” in the previous phase such that VSW is also “1”, and
4.3 Comparator-Based Active Rectifiers 73

Fig. 4.17 The active diode 1 (2) with the Case 2 delay compensation scheme

the switches M11 and M12 are turned off. In the present phase, VGN1 drives VSW low
and turns on M11 and M12, allowing auxiliary bias currents from M9 and M10 to
introduce the designed DC offset. This offset voltage of the differential pairs with
unbalanced bias currents is
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2I þ 2I 
V OS ¼ 
kn ðW=Lr Þ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
kn ðW=L
ffi Þ
ð4:19Þ
pffiffiffi 2I  pffiffiffi
¼ ð n  1Þ ¼ ð n  1ÞV OV- ,
kn ðW=LÞ

where kn ¼ μnCox, I+ and I are the unbalanced bias currents, n is the ratio of I+ and
I, and VOV– is the gate overdrive voltage of M1 through M4 when they are
operating with balanced bias current (1X). The sizes of the common-gate input
pairs M1 through M4 are the same, with VOV– lower than 100 mV. The bodies of M1
through M4 are all connected to the on-chip ground, such that the threshold voltage
VTHN of M1 and M4 would be smaller than VTHN of M2 and M3 when VAC1 < 0 due
to the body effect. The bias currents of M7 through M10 are 1X, 1X, 3X and 4X
respectively. The current of M10 should be 3X (same as M9); however, taking the
body effect of M4 into consideration, it is set as 4X instead to make V2 even higher.
The auxiliary bias currents also serve as slew-rate enhancement currents that charge
up V1 and V2, starving M6 and feeding M1. Hence, VOUT is pulled low, turning off
the power switch MN1 right before VAC1 > 0 to prevent the occurrence of reverse
current. The NOR SR-latch is added at each output of the comparators to avoid the
aforementioned multiple-pulsing problem that can be caused by the dynamic offset
scheme. Due to the NOR implementation of the SR-latch, VSW stays low even when
VGN1 goes low, keeping the artificial offset operative and preventing MN1 from
74 4 Circuit Design of CMOS Rectifiers

turning on again in the same phase even if VAC1 is still lower than 0 V, and the
multiple-pulsing problem is thus avoided. Another one-shot per cycle configuration
used in [16] that pulls down the comparator output is not more reliable for
eliminating multiple pulsing.
To save static power, the power supplies of the comparators CMP1 and CMP2
can be connected to (the distorted sinusoidal waveforms) VAC2 or VAC1, respec-
tively, such that only one comparator has the bias current to work in each half-cycle
[8]. In addition, the VOUT node of the comparators is coupled to ground in the
layout, to make sure that this high-impedance node would not jump when the
supply (VAC2 or VAC1) is low. However, to eliminate multiple pulsing, the power
supply of the gate-drive buffers and the latches should be connected to the DC
output VDC. All N-wells are connected to VDC. Some PN junctions (P+ active area
to N-well) are slightly forward biased by VAC2  VDC (or VAC1  VDC, equal to VDS
of the power PMOS that is approximately 70 mV), the associated leakage current is
negligible. When VAC2 or VAC1 is slightly higher than VDC during the conduction
time, the matched currents of M7 through M10 would be larger than the designed
bias current with larger VGS. This arrangement is good for the comparators to have
more instantaneous current and faster response.
The measured biasing current of the peaking current source used in Rec1 is
shown in Fig. 4.18a, which matches well with simulation results. The peak current
is designed to be around 4.1 μA when the supply voltage is 2.3 V, and the minimum
bias current is 3.2 μA when VDC ¼ 3.8 V. When VDC changes from 1.2 to 3.8 V, I1
changes by over 50%, but the bias current changes by only 12.3%.
Simulated and measured results of the proposed QIPV bias circuit are shown in
Fig. 4.18b. The size of MN3 is the same as MN1, while (W/L )2 is still four times of
(W/L )1, because I1 at VPEAK2 is roughly two times higher than I1 at VPEAK1. With
this assignment, IB2,PEAK is about half of IB1,PEAK. The combined bias current
IB ¼ IB1 + IB2 then resembles a QIPV output current. The measured IB1 peaks at
around 1.6 V with a current of 2.68 μA, and drops to 0.5 μA at VDC ¼ 4 V. The
measured IB2 peaks at around 2.9 V with a current of 1.53 μA. Meanwhile, IB peaks
at around 1.7 V with 3.95 μA, and drops to 1.97 μA at VDC ¼ 4 V. The dual-peaking
current biasing circuit can be easily modified to bias an amplifier designed to have a
constant (or adaptive) bandwidth, for example, to compensate for the negative
effects due to decreasing supply voltage.

4.3.4.1 Power Transistor Sizing

NMOS transistors are chosen to implement the active diodes and PMOS transistors
to implement the cross-coupled pair for two reasons. First, by using PMOS tran-
sistors for the cross-coupled pair, they are driven by the AC input, not by the
comparator. Thus, their parasitic gate capacitors do not affect the speed and the
switching loss of the rectifier, as the gate capacitors are now part of the LC resonant
tuning capacitor C2 that recycles the charge, and the energy is just transferred
between C2 and the secondary coil L2.
4.3 Comparator-Based Active Rectifiers 75

Fig. 4.18 Simulated and

measured output current
versus supply voltage of (a)
the peaking current source
for Rec1 and (b) the QIPV
biasing for Rec2

Second, the mobility of NMOS transistors is higher, and results in smaller W/L
ratios that reduce switching loss. For the trade-off between switching loss and
conduction loss, WN is set to be 600 μm with minimum channel length; otherwise,
W/L of the power PMOS has to be large to achieve a small turn-on voltage drop
(WP ¼ 4000 μm). In this design, the turn-on voltage drops of power NMOS VDSN
and PMOS |VDSP| are set to be roughly 250 mV and 70 mV, respectively, at |
VAC| ¼ 1.5 V and RL ¼ 500 Ω. The total voltage drop is only about 320 mV in the
worst case, which is much smaller than using passive diodes.

4.3.4.2 Start-Up Process

The lowest input amplitude VAC,MIN for our proposed rectifiers to work is deter-
mined by the minimum supply voltage of the comparators. The rectified DC voltage
76 4 Circuit Design of CMOS Rectifiers

should be higher than VGS + VDSAT for the comparators to work, so VAC,MIN is given
by

V AC, MIN ¼ V DC, MIN þ V Drop ¼ V GS þ V DSAT þ V DSN þ jV DSP j, ð4:20Þ

where VDSN and |VDSP| are the drain-to-source voltages of the power transistors.
However, the lowest input amplitude for start-up is the same as that of using passive
diodes, because when the active rectifier is relaxed, the DC output voltage VDC is
0 and is unable to turn on the power NMOS switches. Instead, as illustrated in
Fig. 4.19, parasitic diodes of the power NMOS switches will be forward-biased
when VAC > VDC during start-up. After the output capacitor is charged up to higher
than the minimum supply voltage required by the comparators that are biased by the
QIPV current source, the power NMOS switches are then activated, and the active
rectifier could then function as designed. Latch-up problem could be avoided by
careful layout. In more complicated control schemes, a start-up circuit may be
needed to obtain a smooth transition or avoid malfunction.

4.3.4.3 Measurement Results

The proposed active rectifiers were designed and fabricated in a 0.35 μm CMOS
N-well process. Micrographs of the rectifiers are shown in Fig. 4.20. The sizes of
these two rectifiers, including the pads, are 0.12 mm2 and 0.19 mm2, respectively;
and the active areas are 0.041 mm2 and 0.065 mm2, respectively. The measurement
setup is shown in Fig. 4.21, including the planar coupling coils that are etched on
single-side printed circuit boards (PCBs). The primary and secondary coils each
have three turns with inner and outer radii of 0.75 cm and 1 cm respectively, and
were separated by 1 cm during measurements. The measured inductance of the coils
is 310 nH, and the series resistance is 480 mΩ at 13.56 MHz and 190 mΩ at
DC. The DC output of the rectifier drives a 1.5 nF off-chip filtering capacitor.
Figure 4.22 shows the measured AC input and DC output waveforms of the
proposed active rectifiers Rec1 and Rec2, respectively. The peak of IB1 is eventu-
ally designed to be located at 1.6 V instead of 1.2 V to reserve adequate margin for
keeping the PCE high in the middle and higher range of VAC. The optimized case is
when the input amplitude VAC is 3 V and RL is 500 Ω. The input voltage ripples
across VAC1 and VAC2 are due to the large input current changes during turning on
and off the power NMOS switches. As can be observed from Fig. 4.22a and 4.22b,
reverse current is well eliminated, which means that the NMOS switch is turned off
when its drain voltage is higher than the ground voltage. The worst operating
condition for the rectifier is at heavy load and low input amplitude, as shown in
Fig. 4.22c and 4.22d. In this case, a small amount of reverse current is observed due
to slower response time of the rectifier at lower supply voltages. Conduction loss of
the power transistors increases at heavy load and when the gate overdrive voltage is
small at low VAC. The performance could further be improved if the bias current of
the comparator is slightly increased to have a larger offset for faster response.
4.3 Comparator-Based Active Rectifiers 77

Fig. 4.19 Simulated start-up process of the active rectifier (Rec2)

Fig. 4.20 Micrographs of (a) Rec1 and (b) Rec2

Figure 4.23 summarizes the measured voltage conversion ratios M of the recti-
fiers versus VAC under different loading conditions (RL ¼ 500 Ω and 5 kΩ,
respectively). The peak voltage conversion ratios of Rec1 and Rec2 are 92.3%
and 93.1%, respectively, when RL ¼ 5 kΩ. The minimum M of Rec1 and Rec2 are
74% and 79%, respectively, when RL ¼ 500 Ω.
For PCE measurement, as shown in Fig. 4.24, a 10 Ω resistor is inserted in the
input path to measure the AC input current IAC. C2B is used to filter the distorted
VAC waveforms caused by the 10 Ω resistor during large dI/dt transients. The data
of VAC and IAC can be collected by two identical differential probes with the setup
shown in Fig. 4.24a; or by two identical single-ended probes as shown in Fig. 4.24b.
78 4 Circuit Design of CMOS Rectifiers

Fig. 4.21 Measurement setup for the 13.56 MHz active rectifiers

Fig. 4.22 Measured waveforms of AC inputs and DC output at RL ¼ 500Ω and VAC ¼ 3 V of (a)
Rec1 and (b) Rec2; at RL ¼ 500 Ω and VAC ¼ 1.5 V of (c) Rec1 and (d) Rec2

In addition, a voltage meter with floating terminals not connected to the ground
(a handheld digital multimeter, for example) is needed for the measurement with
single-ended probes. Note that according to (4.5), the PCE is not necessarily lower
than the voltage conversion ratio at the same loading condition, as the highest PCE
4.3 Comparator-Based Active Rectifiers 79

Fig. 4.23 Measured voltage conversion ratios of Rec1 and Rec2 with different loadings

usually is designed to be at heavy load, while the highest M is always obtained at

light load.
In our experiments, two differential active probes with 1 GHz bandwidth were
used to measure VAC and IAC. About 10,000 points of VAC and IAC (6 cycles) were
integrated and averaged for PIN in each PCE calculation. The secondary coil L2
resonated with C2A + C2B at 13.56 MHz, with C2B/C2A ¼ 0.15. As shown in
Fig. 4.25, the measured IAC is the sum of ICap that passes through C2B and IRec
that flows into the rectifier. To obtain accurate PCE results, C2B/C2A cannot be
large, otherwise, the large ICAP of C2B that does not dissipate power will affect the
accuracy of the relatively small rectifier input current IREC that dissipates power.
Note also that the scales of the two identical probes should be kept the same to
guarantee accuracy.
As summarized in Fig. 4.26a, with RL ¼ 500 Ω, the PCEs of Rec2 were
measured to be 82.2–90.1% with |VAC| that varied from 1.5 to 4 V; while in
Fig. 4.26b the PCEs of 82.3% and 71.2% were measured at |VAC| ¼ 3 V with
RL ¼ 100 Ω and 5 kΩ, respectively. Simulated PCEs are also included for reference:
84.2–90.7% were obtained with a load resistor of 500 Ω, and 82.9–81.3% were
obtained at |VAC| ¼ 3 V with RL ¼ 100 Ω and 5 kΩ, respectively. All the above
results were measured and simulated at an input frequency of 13.56 MHz. In
Fig. 4.26c, measured and simulated PCEs of Rec2 that operated at the transmission
frequencies from 10 to 20 MHz are shown, with RL ¼ 500 Ω and |VAC| ¼ 3 V. The
measured PCEs matched quite well with the simulated PCEs at heavy load, and
started to deviate from the simulated PCEs at light load of 1 kΩ since IREC became
too low to be measured accurately.
80 4 Circuit Design of CMOS Rectifiers

Fig. 4.24 The PCB schematics for PCE measurements with (a) differential voltage probes or (b)
single-ended probes

Fig. 4.25 Measured waveforms of VAC, IAC and VDC for PCE calculation

Table 4.1 summarizes and compares the performance of our works with state-of-
the-art designs. With inductively-coupled air coils operating at 13.56 MHz in the
ISM frequency band, the proposed rectifier achieved good voltage conversion ratio
and power conversion efficiency over a wide input range and loads.
4.3 Comparator-Based Active Rectifiers 81

Fig. 4.26 Measured and simulated PCEs of the proposed Rec2 operating at 13.56 MHz with (a)
RL ¼ 500 Ω and (b) |VAC| ¼ 3 V; and (c) its frequency response with condition of RL ¼ 500 Ω and |
VAC| ¼ 3 V
 82

Table 4.1 Comparison to the state-of-the-art rectifiers

TBCAS This work Rec1 This work Rec2
TCAS-II 06 [8] JSSC 09 [9] TCAS-I 11 [11] 12 [36] JSSC 12 [13] [10] [14]
Technology 0.35 μm 0.35 μm 0.5 μm 0.18 μm 0.18 μm 0.35 μm 0.35 μm
Chip area 0.107 mm2 1.03 mm2 0.263 mm2 0.608 mm2 0.34 mm2 0.12 mm2 0.19 mm2
Frequency 13.56 MHz 1.5 MHz 13.56 MHz 10 MHz 13.56 MHz 13.56 MHz 13.56 MHz
Input Amp. 1.5 ~ 3.5 V 1.2 ~ 2.4 V 3.3 ~ 5 V 0.8 ~ 2.7 V N/A 1.5 ~ 4 V 1.5 ~ 4 V
Load Cap. 200 pF 1 μF 10 μF 200 pF 5.8 μF 1.5 nF 1.5 nF
Output voltage 1.2 ~ 3.22 V 1.13 ~ 2.28 V 2.5 ~ 3.9 V 0.3 ~ 2.0 V 1.2 V (w/load 1.28 ~ 3.65 V 1.28 ~ 3.56 V
(RL ¼ 1.8 kΩ) (RL ¼ 2 kΩ) (RL ¼ 500 Ω) (RL ¼ 2 kΩ) chip) (RL ¼ 1.8 kΩ) (RL ¼ 1.8 kΩ)
0.98 ~ 2.08 V 1.13 ~ 3.50 V 1.19 ~ 3.52 V
(RL ¼ 100 Ω) (RL ¼ 500 Ω) (RL ¼ 500 Ω)
Coil Diam. 6.0 cm N/A 3.0 cm N/A 7 mm 2.0 cm 2.0 cm
POUT (Max.) 5.76 mW 43.3 mW 30.42 mW 2 mW 112.5 mW 24.5 mW 24.8 mW
Voltage conver- 0.78 ~ 0.92 0.94 ~ 0.95 0.76 ~ 0.81 0.6 ~ 0.89 N/A 0.85 ~ 0.9 0.873 ~ 0.93
sion ratio, M (RL ¼ 1.8 kΩ) (RL ¼ 2 kΩ) (RL ¼ 500 Ω) (RL ¼ 2 kΩ) (RL ¼ 1.8 kΩ) (RL ¼ 1.8 kΩ)
0.82 ~ 0.84 0.74 ~ 0.88 0.79 ~ 0.89
(RL ¼ 100 Ω) (RL ¼ 500 Ω) (RL ¼ 500 Ω)
PCE (simulated) 65% ~ 89% 82% ~ 87% 71% ~ 84.5% 60% ~ 86% 93% 82.5% ~ 89.6% 84% ~ 90.7%
(RL ¼ 1.8 kΩ) (RL ¼ 100 Ω) (RL ¼ 500 Ω) (RL ¼ 2 kΩ) (w/load chip) (RL ¼ 500 Ω) (RL ¼ 500 Ω)
PCE (measured) N/A N/A 68% ~ 80.2% 37% ~ 80% N/A N/A 82% ~ 90.1%
(RL ¼ 500 Ω) (RL ¼ 2 kΩ) (RL ¼ 500 Ω)
4 Circuit Design of CMOS Rectifiers
4.3 Comparator-Based Active Rectifiers 83

Fig. 4.27 Fully integrated 1X/2X active rectifier with QIPV bias current

4.3.5 Reconfigurable Rectifier Design Example

To cater for coupling coefficient k variation with distance and/or orientation, as

discussed in Chap. 2, a reconfigurable rectifier may be used to increase VDC without
increasing the transmitted power under certain conditions. A fully integrated
reconfigurable active rectifier (labeled as Rec3) [3] that can be switched between
the full-wave rectifier (1X) mode and the voltage doubler (2X) mode in the 30 mW
range with all capacitors fabricated on-chip is shown in Fig. 4.27.
In the traditional reconfigurable rectifier shown in Fig. 4.2, the output capacitors
are connected in series which is not area-efficient for on-chip implementation. The
effectiveness of utilizing on-chip capacitors in this design is significantly improved
by the switching arrangement that avoids connecting the output capacitors in series
in the 2X mode. Reverse current is reduced for |VAC| that ranges from 1.25 V to 4 V
by the bias current that is quasi-inversely proportional to the output DC voltage VDC
(QIPV).
Figure 4.28 shows the conventional and the proposed arrangement of CL.
Assume that the total capacitance available is 4C for implementing CL, in the
conventional topology, two 2C capacitors are connected in series that results in
CL,EQ equal to C in both the 1X and the 2X mode. In the proposed topology,
CFLY ¼ C and CL ¼ 3C are connected through switches S1 and S2. In the 1X mode,
S1 is turned on, the two capacitors are in parallel, and CL,EQ is 4C; and in the 2X
mode, S1 is opened, CFLY acts as a flying capacitor to charge up CL, and CL,EQ is
3C. As a result, the proposed topology increases CL,EQ by 4 and 3 times compared
to the universal rectifier in the 1X and the 2X mode, making it possible to integrate
the capacitors on-chip. In our case, CFLY and CL are equal to 1 and 3 nF respec-
tively. Note that CFLY serves as a pumping capacitor for voltage doubling in a
charge pump, and a small CFLY will limit the VCR and consequently the PCE.
84 4 Circuit Design of CMOS Rectifiers

Fig. 4.28 The conventional and the proposed arrangement of CL, assuming that the total capac-
itance available is 4C for implementing CL

Based on the considerations of the VCR at the maximum loading condition in the
2X mode, CFLY is set to be 1 nF.
The schematics of the comparators CMP1 (CMP2) with MN1 (MN2), and the
comparator CMP3 with MP1, are shown in Fig. 4.29. The “Mode” signal also
changes the value of the unbalanced currents in CMP1 and CMP2, such that the
offsets of CMP1 and CMP2 are set to different values in the two modes, because the
input sinusoidal wave has different slew rates in the 1X and the 2X mode. Note that
for Rec3 the minimum value of VDC is 1.6 V as the rectifier would operate in the 2X
mode in low-voltage conditions. Thus, the proposed QIPV IBIAS helps the rectifier
to reduce the reverse current for VDC from 1.6 to 4 V.
The comparator CMP3 is disabled in the 1X mode by cutting off its bias current
with an “En” signal, because the power PMOS transistors are cross-coupled in the
1X mode. In the 2X mode, CMP2 is not disabled even it does not need to work in
this mode, because its input terminal VAC2 is always equal to roughly half of VDC
(always above Ground voltage) in the 2X mode. It means that the CMP2 output
would not fluctuate in the 2X mode, and no extra switching loss will be induced by
CMP2 and MN2.
In designing the transistor sizes of the power MOS, we need to consider the
tradeoff for peak VCRs and PCEs between the 1X mode and the 2X mode. Ideally
with a resistive load, the output voltage VDC in the 2X mode is double of the |VAC|
input, and therefore the input current of the converter is double of the output
current. Thus, for the same load condition, larger current needs to be conducted
4.3 Comparator-Based Active Rectifiers 85

Fig. 4.29 Schematics of the CMP1 (CMP2) with MN1 (MN2), and the CMP3 with MP1

in the 2X mode, and consequently larger transistors are needed for the 2X mode.
Another point is that, as mentioned in Sect. 4.3.4.1, when the PMOS transistors are
configured as cross-coupled pair, they are driven by the AC input, not the compar-
ator, and their parasitic gate capacitors do not affect the speed and the switching
loss of the rectifier, as they are part of the LC resonant tuning capacitor C2 that do
not dissipate power. However, for the 1X/2X reconfigurable rectifier, the power
PMOS MP1 is driven by CMP3 through a buffer in the 2X mode, and cannot be too
large as for the full-rectifiers Rec1 and Rec2.
86 4 Circuit Design of CMOS Rectifiers

Fig. 4.30 Chip micrograph of Rec3

The proposed 1X/2X rectifier was fabricated in a 0.35 μm CMOS process. The
chip micrograph is shown in Fig. 4.30. The active area is 0.1 mm2, and the capacitor
area is 1.3 mm2. The flying and output capacitors CFLY and CL are MOS capacitors
with a capacitance density of 3.2 fF/μm2 that could be much higher for an advanced
process with stacked metal capacitors. The coupling coils L1 and L2 for measure-
ments are 2 cm and 1.8 cm in diameter, respectively. The secondary inductor L2 is
268 nH and resonates with the tuning capacitor C2 ¼ C2A + C2B of 514 pF at
13.56 MHz.
The measured AC input and DC output voltage waveforms in both modes with
RL ¼ 500 Ω and CL ¼ 4 nF (on-chip) are shown in Fig. 4.31. The worst voltage
conversion ratio occurs at the lowest |VAC| points.
VCRs and PCEs under different conditions are plotted in Fig. 4.32. With
RL ¼ 500 Ω, the VCR is 0.85–0.9 in the 1X mode with the QIPV bias current
optimized for this case, and is 1.3–1.61 in the 2X mode. With RL ¼ 5 kΩ, the VCR
is 0.92–0.95 in the 1X mode, and is 1.73–1.77 in the 2X mode. With RL ¼ 500 Ω,
the PCEs of the 1X and the 2X mode are measured to be 81–84.2% and 61–76%,
respectively. Table 4.2 summarizes the performance of Rec1, Rec2, and Rec3 with
the state-of-the-art full-wave and reconfigurable designs.

4.4 DLL-Based Rectifiers

Besides the mentioned analog solutions, there are other variations of CMOS active
rectifiers that have been proposed [22–26] for near-field wireless power transfer.
Figure 4.33 shows a WPT active rectifier that operates at a relatively high frequency
4.4 DLL-Based Rectifiers 87

Fig. 4.31 Measured AC input and DC output voltage waveforms in both modes with RL ¼ 500 Ω
and CL ¼ 4 nF (on-chip) at their lowest |VAC| points

Fig. 4.32 Measured

voltage conversion ratios
and power conversion
efficiencies of the 1X/2X
rectifier in both modes

(150 MHz). It is a delay-locked-loop (DLL) based synchronous active rectifier that

uses the DLL to synchronize the gate control signals with the AC input waveforms
and to generate discrete timing slots for controlling the power switches. The clock
signal “Clk” is recovered by comparing the AC input signals, and then it is used to
generate multiple time-shifted pulses. The multiplexers (MUXs) are controlled by
the comparators to relay the “set” and “reset” timing signals to the gate drive
buffers.
88 4 Circuit Design of CMOS Rectifiers

Table 4.2 Comparison of full-wave and reconfigurable rectifiers

[8] [12] [2] Rec1 [10] Rec2 [14] Rec3 [3]
Tech. (μm) 0.35 0.18 0.5 0.35
Area (mm2) 0.107 0.009 0.585 0.04 0.065 0.1(w/o CL)
Freq. (MHz) 13.56
|VAC| (V) 1.5–3.5 0.9–2 3.2–5 (1X) 1.5–4 1.5–4 1.5–4 (1X)
1.7–2.5 1.25–2.5
(2X) (2X)
CL (nF) 0.2 10,000 2000 1.5 1.5 4
RL (Ω) 1.8 k 1k 500 500 500 500
VDC (V) 1.2–3.2 0.45–1.8 2.5–4.3 1.13–3.5 1.2–3.5 1.27–4
Coil (cm) 6.0 N/A 3.0 2.0 2.0 1.8
POUT,MAX 5.76 3.2 37 24.5 24.8 32
(mW)
VCR 1X 0.78–0.92 0.82–0.89 ~0.84 0.74–0.88 0.79–0.89 0.85–0.9
VCR 2X N/A N/A ~1.41 N/A N/A 1.3–1.61
PCE 1X 65–89% 60–82% 73–77% 82–90% 82–90% 81–84%
PCE 2X N/A N/A 64%–70% N/A N/A 61–76%

Fig. 4.33 A DLL-based

synchronous active rectifier
4.5 Rectifiers for RF Energy Harvesting 89

In the open-loop finite resolution design of [22], the RF signal envelope is

assumed to vary slowly and that small timing errors cause insignificant reduction
of the rectifier efficiency. This assumption applies better to the series-resonant
receiver than to the parallel-resonant receiver, as demonstrated in [16]. The reason
is that, for the parallel-resonant receiver, the delay of the active diode increases the
conduction time of the power transistors, resulting in extra conduction loss. More-
over, as the duration of the turn-off delay is comparable to the forward-current
conduction time when operating at high frequencies, this extra conduction loss is
significant and the efficiency degradation is severe. On the other hand, the series-
resonant tank works as a current source, and the forward conduction time is much
longer than that of the parallel-resonant receiver. Therefore, with the same amount
of turn-off delay, the reverse current in the series-resonant receiver is only a small
portion of the forward current, so the efficiency degradation is limited.
In another two LC series-resonant WPT designs [23, 24], replica delays were
inserted in the DLL to imitate the gate-drive delay. By doing so, the reverse current
can be well controlled when the replica delay matches well with the actual gate-
drive delay. Alternatively, a sampled voltage-to-time conversion block was used in
[25] to enable the power NMOS with zero-voltage switching (ZVS) and to elimi-
nate the reverse current.

4.5 Rectifiers for RF Energy Harvesting

Although most of the WPT applications employ near-field operation for high and
medium power levels, WPT with far-field operation has the advantage of longer
transmission distance. In addition, RF energy harvesting together with other
harvested ambient energy sources could serve as the power source for autonomous
ultra-low-power internet-of-things (IoT) devices.
The majority of communication systems are designed to operate in the ultra-
high-frequency (UHF) ISM bands (300 MHz–3 GHz), and the density of wireless
devices keeps increasing rapidly worldwide in the recent decade. Thus, there is
sufficient RF energy readily available in the environment in the UHF band. More-
over, using UHF for wireless power transfer could lead to a low-cost and/or small-
size solution.
RF energy harvesting requires the rectifier to operate in the UHF range, and the
rectification is commonly known as RF-DC conversion. While AC-DC conversion
is usually discussed in the voltage domain, RF-DC conversion is mostly considered
in the power domain. Since the RF input power level is usually low, multiple step-
up stages are needed to attain a reasonably high output voltage. Figure 4.34 shows
the voltage multiplier that is similar to the Dickson charge pump [27] used in [28] as
a multi-stage rectifier for the RF to DC conversion at UHF. Each stage is a voltage
doubler, and the ideal no-load output voltage of an N-stage converter is 2N times of
the RF input amplitude.
90 4 Circuit Design of CMOS Rectifiers

Fig. 4.34 Schematic of the

Dickson-type multi-stage
step-up rectifier

An interesting and useful characteristic of the multi-stage rectifier is that the

number of stages N does not affect the maximum achievable PCE [29]. Note that
each stage draws current from the RF input source in the charging phase of each
cycle, and the stages are stacked in the discharging phase to achieve a high output
voltage. In other words, the operation of each stage resembles that of a single-stage
rectifier, and thus the maximum achievable PCE is basically independent of the
number of stacking stages.
The appreciable diode drop is the main constraint that limits the low-voltage
operation of the rectifiers, and this problem is exacerabated for RF wireless power
transfer for longer distance transmission with very low coupling coefficient. There-
fore, the cross-connected (CC) CMOS rectifier [30], as shown in Fig. 4.35, is
commonly used for its low-voltage and auto-switching characteristics. Provided
that the RF input voltage is high enough, the MOS transistors will act as switches
with low on-resistance for rectification, and the forward voltage drop is minimized.
However, a high leakage current may occur if the RF input voltage is too high
because the PMOS and NMOS will be turned on simultaneously during the
transition instants, similar to the shoot-through current problem of a CMOS
inverter. To achieve better sensitivity and to achieve high heavy-load efficiency,
the rectifier needs larger transistors, but will then cause more reverse leakage
current that limits the efficiency at high input power. Larger transistors also
increase the parasitic loss during the step-up conversion [31]. It has been demon-
strated in [6] that the voltage conversion ratio (VCR) of the cross-connected
topology could be larger than 0.8 when the input amplitude of the rectifier was
higher than 150 mV.
To increase the received power, another solution that has much lower dynamic
leakage current and low diode drop is to use a VTH compensation voltage [33–36] to
bias the diode-connected MOSFET, and the circuit is also shown in Fig. 4.35.
4.5 Rectifiers for RF Energy Harvesting 91

Fig. 4.35 Schematics of half-wave rectifiers, cross-connected rectifiers, and rectifiers with VTH
compensation

However, if the compensation voltage is realized by a tiny bias current (due to a

restricted power budget) through a large resistor RB filtered by a large capacitor CB,
then considerably large area would be consumed for a multi-stage rectifier.
Figure 4.36 shows the simulated PCEs of the three mentioned RF-DC rectifier
topologies with RL ¼ 100 kΩ in a low-leakage 65 nm process. All three designs
consist of three cascade stages for fair comparison. Obviously, the CC rectifier
achieves the highest peak PCE among the three rectifiers. However, its high-PCE
range is narrow due to the dynamic leakage current. A high-PCE range extension
technique that consists of one high-power path and one low-power path with auto-
selection can be used [32]. For the rectifier with cross-connected NMOS and VTH-
compensated PMOS, the performance is better than the diode-connected MOS
92 4 Circuit Design of CMOS Rectifiers

Fig. 4.36 Simulated PCEs

of three rectifier topologies
with RL ¼ 100 kΩ

rectifier at a lower input power range, and achieves a wider input power range than
the CC rectifier. As shown in Fig. 4.37, the VCR for the CC topology will drop at
high input-power levels, while that of the diode-based rectifiers are monotonic with
respect to the input power.
An inter-stage VTH-compensation scheme was introduced in [37, 38], and a
5-stage example is shown in Fig. 4.38. The VTH-compensation was achieved by
connecting the gate terminal to the output of a higher stage and as such, no large RB
and CB have to be used while achieving similar performance. In fact, a similar
strategy has been employed in step-up charge pump designs [39, 40].
Detailed analysis and simulation results show that the output voltage of a
rectifier with the transistors operating in the subthreshold region is different from
that of operating in the saturation region. As it has been analyzed in Sect. 4.2, the
I-V characteristic of the transistors operating in the subthreshold region follows an
exponential ID/VD relationship. With a typical value of ζ at room temperature, VGS
decreases by roughly 80 mV for ID to decrease by one decade, which is independent
of the value of VTH. Therefore, it was shown that transistor size and VTH have no
effect on VDC, and 32 dBm sensitivity was achieved with 50 stages [41].

4.6 Summary and Discussion

Passive and active rectifiers have been extensively discussed in this chapter. For
passive rectifiers, using the composite CMOS diode results in low reverse leak-
age current and comparable forward current capability, which is favorable for
low-power rectifiers.
The operation mechanism of the comparator-based active rectifiers for near-field
WPT has been analyzed, and circuit design techniques and considerations have
been discussed. In addition, a couple of design examples of active rectifiers with the
4.6 Summary and Discussion 93

Fig. 4.37 Simulated VCRs

of three rectifier topologies
with RL ¼ 100 kΩ

Fig. 4.38 Schematic of the inter-stage VTH-compensation rectifier

switched-offset scheme are demonstrated. To optimally eliminate the reverse

current associated with active diodes, the adaptive on- and off-delay compensation
technique can be considered. Alternatively, DLL-based synchronous rectifiers have
also been demonstrated to achieve promising performance, especially for the series-
resonant receiver case.
For far-field WPT, voltage boosting is achieved by multi-stage rectifiers with
structures that are similar to step-up charge pumps. The cross-connected topology
was proven to be capable of achieving high efficiency at UHF, but it suffers from
dynamic leakage current when the RF input amplitude is too high. The inter-stage
VTH-compensation scheme has also demonstrated promising performance, and
more sophisticated inter-stage gate control of the switches might be a possible
solution.
94 4 Circuit Design of CMOS Rectifiers

References

1. Ghovanloo M, Najafi K (2004) Fully integrated wideband high-current rectifiers for induc-
tively powered devices. IEEE J Solid State Circuits 39:1976–1984. doi:10.1109/JSSC.2004.
835822
2. Lee H-M, Ghovanloo M (2012) An adaptive reconfigurable active voltage doubler/rectifier for
extended-range inductive power transmission. IEEE Trans Circuits Syst II Exp Briefs
59:481–485. doi:10.1109/TCSII.2012.2204840
3. Lu Y, Li X, Ki W-H, Tsui C-Y, Yue CP (2013) A 13.56MHz fully integrated 1X/2X active
rectifier with compensated bias current for inductively powered devices. In: 2013 I.E. inter-
national solid-state circuits conference digest of technical papers (ISSCC), pp 66–67. doi:10.
1109/ISSCC.2013.6487639
4. Razavi B (2000) Design of analog CMOS integrated circuits, 1st edn. McGraw-Hill, Inc.,
New York
5. Levacq D, Liber C, Dessard V, Flandre D (2004) Composite ULP diode fabrication, modelling
and applications in multi-Vth FD SOI CMOS technology. Solid State Electron 48:1017–1025.
doi:10.1016/j.sse.2003.12.016
6. Stoopman M, Keyrouz S, Visser HJ, Philips K, Serdijn W (2014) Co-design of a CMOS
rectifier and small loop antenna for highly sensitive RF energy harvesters. IEEE J Solid State
Circuits 49:622–634. doi:10.1109/JSSC.2014.2302793
7. Haddad PA, Gosset G, Raskin JP, Flandre D (2016) Automated design of a 13.56 MHz 19 μW
passive rectifier with 72% efficiency under 10 μA load. IEEE J Solid State Circuits
51:1290–1301. doi:10.1109/JSSC.2016.2527714
8. Lam Y-H, Ki W-H, Tsui C (2006) Integrated low-loss CMOS active rectifier for wirelessly
powered devices. IEEE Trans Circuits Syst II Exp Briefs 53:1378–1382. doi:10.1109/TCSII.
2006.885400
9. Guo S, Lee H (2009) An efficiency-enhanced CMOS rectifier with unbalanced-biased com-
parators for transcutaneous-powered high-current implants. IEEE J Solid State Circuits
44:1796–1804. doi:10.1109/JSSC.2009.2020195
10. Lu Y, Ki W-H, Yi J (2011) A 13.56MHz CMOS rectifier with switched-offset for reversion
current control. In: 2011 symposium on VLSI circuits (VLSIC), pp 246–247
11. Lee HM, Ghovanloo M (2011) An integrated power-efficient active rectifier with offset-
controlled high speed comparators for inductively powered applications. IEEE Trans Circuits
Syst I Regul Pap 58:1749–1760. doi:10.1109/TCSI.2010.2103172
12. Cha HK, Park WT, Je M (2012) A CMOS rectifier with a cross-coupled latched comparator for
wireless power transfer in biomedical applications. IEEE Trans Circuits Syst II Exp Briefs
59:409–413. doi:10.1109/TCSII.2012.2198977
13. Chung H, Radecki A, Miura N et al (2012) A 0.025-0.45 W 60%-efficiency inductive-coupling
power transceiver with 5-bit dual-frequency feedforward control for non-contact memory
cards. IEEE J Solid State Circuits 47:2496–2504. doi:10.1109/JSSC.2012.2206686
14. Lu Y, Ki W-H (2014) A 13.56 MHz CMOS active rectifier with switched-offset and compen-
sated biasing for biomedical wireless power transfer systems. IEEE Trans Biomed Circuits
Syst 8:334–344. doi:10.1109/TBCAS.2013.2270177
15. C-Y W, Qian X-H, Cheng M-S et al (2014) A 13.56 MHz 40 mW CMOS high-efficiency
inductive link power supply utilizing on-chip delay-compensated voltage doubler rectifier and
multiple LDOs for implantable medical devices. IEEE J Solid State Circuits 49:2397–2407.
doi:10.1109/JSSC.2014.2356459
16. Cheng L, Ki WH, Lu Y, Yim TS (2016) Adaptive on/off delay-compensated active rectifiers
for wireless power transfer systems. IEEE J Solid State Circuits 51:712–723. doi:10.1109/
JSSC.2016.2517119
17. Huang C, Kawajiri T, Ishikuro H (2015) A near-optimum 13.56 MHz active rectifier with
circuit-delay real-time calibrations for high-current biomedical implants. In: 2015 IEEE
custom integrated circuits conference, pp 1–4
References 95

18. Rabaey JM, Chandrakasan A, Nikolic B (2003) Digital integrated circuits: a design perspec-
tive, 2nd edn. Prentice-Hall, New Jersey
19. Frederiksen TM (1972) Constant current source. US Patent 3,659,121, 25 April 1972
20. Gray PR, Hurst P, Lewis S, Meyer RG (2009) Analysis and design of analog integrated
circuits, 5th edn. Wiley, New York
21. Lo MY, Ki W-H, Mow WH (2009) A 20MHz switched-current input sample-and-hold circuit
for current mode analog iterative decoders. In: IEEE International Symposium on Integrated
Circuits, Singapore, pp 283–286, December 2009
22. Radecki A, Chung H, Yoshida Y, et al (2011) 6W/25 mm inductive power transfer for non-
contact wafer-level testing. In: 2011 IEEE international solid-state circuits conference digest
of technical papers (ISSCC), pp 230–232
23. Moon Y-J, Roh Y-S, Yoo C, Kim D-Z (2012) A 3.0-W wireless power receiver circuit
with 75-% overall efficiency. In: 2012 IEEE Asian solid state circuits conference (A-SSCC),
pp 97–100
24. Park H, Jang J, Kim H et al (2016) A design of a wireless power receiving unit with a high-
efficiency 6.78-MHz active rectifier using shared DLLs for magnetic-resonant A4 WP appli-
cations. IEEE Trans Power Electron 31:4484–4498. doi:10.1109/TPEL.2015.2468596
25. Shinohara H, Miyaji K (2015) A ZVS CMOS active diode rectifier with voltage-time-
conversion delay-locked loop for wireless power transmission. In: 2015 IEEE Asian solid-
state circuits conference (A-SSCC), pp 1–4
26. Xu H, Lorenz M, Bihr U, et al (2014) Wide-band efficiency-enhanced CMOS rectifier. In:
2014 I.E. international symposium on circuits and systems (ISCAS), pp 614–617
27. Dickson JF (1976) On-chip high-voltage generation in MNOS integrated circuits using an
improved voltage multiplier technique. IEEE J Solid State Circuits 11:374–378. doi:10.1109/
JSSC.1976.1050739
28. Karthaus U, Fischer M (2003) Fully integrated passive UHF RFID transponder IC with 16.7-μ
W minimum RF input power. IEEE J Solid State Circuits 38:1602–1608. doi:10.1109/JSSC.
2003.817249
29. Yi J, Ki W-H, Tsui C-Y (2007) Analysis and design strategy of UHF micro-power CMOS
rectifiers for micro-sensor and rfid applications. IEEE Trans Circuits Syst I Regul Pap
54:153–166. doi:10.1109/TCSI.2006.887974
30. Facen A, Boni A (2006) Power supply generation in CMOS passive UHF RFID tags. In:
Research in microelectronics and electronics 2006, Ph D, pp 33–36
31. Ki W-H, Lu Y, Su F, Tsui C-Y (2012) Analysis and design strategy of on-chip charge pumps
for micro-power energy harvesting applications. In: VLSI-SoC: advanced research for systems
on chip. Springer, Berlin/Heidelberg, pp 158–186. doi:10.1007/978-3-642-32770-4_10
32. Lu Y, Dai H, Huang M et al (2017) A wide input range dual-path CMOS rectifier for RF energy
harvesting. IEEE Trans Circuits Syst II Exp Briefs 64:166–170. doi:10.1109/TCSII.2016.
2554778
33. Umeda T, Yoshida H, Sekine S, Fujita Y, Suzuki T, Otaka S (2006) A 950-MHz rectifier
circuit for sensor network tags with 10-m distance. IEEE J Solid State Circuits 41:35–41.
doi:10.1109/JSSC.2005.858620
34. Nakamoto H, Yamazaki D, Yamamoto T et al (2007) A passive UHF RF identification CMOS
tag IC using ferroelectric RAM in 0.35-μm technology. IEEE J Solid State Circuits
42:101–110. doi:10.1109/JSSC.2006.886523
35. Le T, Mayaram K, Fiez T (2008) Efficient far-field radio frequency energy harvesting for
passively powered sensor networks. IEEE J Solid State Circuits 43:1287–1302. doi:10.1109/
JSSC.2008.920318
36. Mounaim F, Sawan M (2011) Integrated high-voltage inductive power and data-recovery front
end dedicated to implantable devices. IEEE Trans Biomed Circuits Syst 5:283–291. doi:10.
1109/TBCAS.2010.2103558
37. Papotto G, Carrara F, Palmisano G (2011) A 90-nm CMOS threshold-compensated RF energy
harvester. IEEE J Solid State Circuits 46:1985–1997. doi:10.1109/JSSC.2011.2157010
96 4 Circuit Design of CMOS Rectifiers

38. Xia L, Cheng J, Glover NE, Chiang P (2014) 0.56 V, 20 dBm RF-powered, multi-node
wireless body area network system-on-a-chip with harvesting-efficiency tracking loop. IEEE J
Solid State Circuits 49:1345–1355. doi:10.1109/JSSC.2014.2305074
39. J-T W, Chang K-L (1998) MOS charge pumps for low-voltage operation. IEEE J Solid State
Circuits 33:592–597. doi:10.1109/4.663564
40. Su F, Ki W-H (2008) An integrated reconfigurable SC power converter with hybrid gate
control scheme for mobile display driver applications. In: 2008 IEEE Asian solid-state circuits
conference (A-SSCC), pp 169–172
41. Oh S, Wentzloff DD (2012) A 32dBm sensitivity RF power harvester in 130nm CMOS.
In: 2012 IEEE radio frequency integrated circuits symposium, pp 483–486
Chapter 5
Linear Regulators for WPT

Abstract Linear regulator is an area-efficient component for voltage regulation

that could achieve excellent power supply ripple rejection. With no switching
activities as compared to a switched-inductor or switched-capacitor power con-
verter, it can serve as a well-controlled power source for digital and especially
noise-sensitive analog circuits. It is very suitable for miniature and low-power
systems, such as wireless power receivers for portable and implantable applica-
tions. This chapter starts with the basic topologies of linear regulators followed by
control loop design. Various circuit techniques are demonstrated through the design
of two fully-integrated examples that were implemented in 65 nm and 28 nm bulk
CMOS processes, respectively.

Keywords Wireless power transfer • Low-dropout regulator • Power supply

rejection • PSRR • Digital LDO • Transient response

5.1 Introduction

As mentioned in the previous chapters, the simplest way to regulate the output
voltage of the wireless power receiver is to add a post-stage linear regulator, as
shown in Fig. 5.1. Linear regulators can filter out the input supply noise and provide
a clean supply voltage to drive noise sensitive sensor circuits, wireless communi-
cation front-end circuits, critical paths in VLSI chips, and simply provide a voltage
step-down function in low-cost applications [1, 2].
The operation principle of a linear regulator is to dynamically tune the series or
shunt resistance of the regulator, such that the resistive voltage divider, formed by
the source resistance and the load resistance, always maintains a desired ratio for
the intended output voltage. Figure 5.2 shows the schematics of a typical series
regulator and shunt regulator. In this chapter, we define the parameters VIN as the
regulator input voltage and VOUT as the regulator output voltage. The series
regulator consists of a power transistor (MP) controlled by an error amplifier
(EA) and a voltage reference. To obtain a fixed output voltage, the series linear
regulator adjusts the voltage headroom (VIN
VOUT) by its power transistor. The
shunt regulator also consists of a power transistor (MN) and an EA, but different

© Springer Nature Singapore Pte Ltd. 2018 97

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_5
98 5 Linear Regulators for WPT

Fig. 5.1 A simple wireless power system with linear regulator for post-stage voltage regulation

from the series regulator MN consumes an extra current that is parallel to the load.
Note that the input source, the rectifier in our case, unavoidably has a finite output
resistance, and therefore the extra current drawn by MN can regulate VOUT accord-
ingly. Since the energy source of the wireless power receiver would change
considerably, when the input current is too high, one more important function for
the shunt regulator is to bypass the extra energy to ground to prevent the device
from over-voltage breakdown.
For both the series and the shunt regulators, they regulate their output voltages
by controlling the on-resistance of their respective power transistors, and thus do
not generate any output ripples. In addition, a linear regulator can filter out the
supply input ripples that come from the previous converter stage. Moreover, a high
bandwidth control loop can be relatively easily realized for a linear regulator
compared to a switching converter that is usually limited by its switching frequency
(especially the inductor-based converter, to be introduced in details in the next
chapter). Rather, the bandwidth of a linear regulator is usually limited by the
constituent error amplifier and the load it drives, and it could be designed to achieve
fast line and load transient responses.
The major drawback of a linear regulator is the unavoidable conduction loss
across its power transistor due to the load current that passes through the output
voltage drop, and this loss is linearly proportional to VIN
VOUT. Note that when
VIN gets lower and lower, the output voltage VOUT may not be maintained, and the
dropout voltage VDO is defined as the difference between VIN,MIN and VOUT, that is,
VDO ¼ VIN,MIN
VOUT. In an application if VIN is allowed to be just a few hundred
milli-volt or lower above VOUT, then high efficiency could be achieved. However,
in such a case, the linear regulator has to have a very low dropout voltage. In fact, in
most portable applications, the linear regulators are low-dropout (LDO) regulators.
As shown in Fig. 5.2a, the power transistor of an LDO regulator is commonly a
P-type transistor because its gate can be driven by a low voltage and it can work in
the active region even VIN is very close to VOUT. Nevertheless, the N-type transistor
is at times preferred for its intrinsic transient response. Analysis and comparison of
these two types are given in the following section.
5.2 PMOS and NMOS LDO Regulators 99

Fig. 5.2 Schematics of (a) the series regulator and (b) the shunt regulator

5.2 PMOS and NMOS LDO Regulators

The schematic of an LDO regulator with P-type power transistor is shown in

Fig. 5.3a and that with N-type power transistor in Fig. 5.3b. Here, we call them
the PMOS LDO and the NMOS LDO for short. The power supply of the EA of the
PMOS LDO can be directly connected to VIN, because it only needs to output a low
voltage for driving MP1. However, the EA of the NMOS LDO should be supplied by
a step-up converter (usually a voltage doubler) to generate a sufficiently high
voltage to drive MN1. When the output voltage drop is larger than the VGS of
MN1, the charge pump may be removed, but then the efficiency would be low.
Besides the above mentioned drawbacks of the NMOS LDO, it does have a couple
of advantages over the PMOS LDO as discussed below.
The output impedance zoP of the PMOS LDO is

1 1
zoP ¼ r dsP jj jj , ð5:1Þ
sCL AðsÞ  gmP
r dsP
zoP ¼ , ð5:2Þ
1 þ s  r dsP CL þ AðsÞ  gmP r dsP

where gmP and rdsP are the transconductance and the output resistance of the P-type
power transistor, and A(s) is the transfer function of the EA. Similarly, the output
impedance zoN of the NMOS LDO is

1 1
zoN ¼ r dsN jj jj , ð5:3Þ
sCL ð1 þ AðsÞÞ  gmN
r dsN
zoN ¼ , ð5:4Þ
1 þ s  r dsN CL þ ð1 þ AðsÞÞ  gmN r dsN

where gmN and rdsN are the transconductance and the output resistance of the N-type
power transistor. Note that the multiplicative factors of gmP and gmN are slightly
different, and they are A(s) and (1 + A(s)), respectively. As the low-frequency
100 5 Linear Regulators for WPT

Fig. 5.3 Schematics of low dropout regulators with (a) PMOS power transistor or (b) NMOS
power transistor

(LF) gain is very high (|A(s)| >> 1 at LF), the above difference is not important, and
we have

zoP, LF  1=AðsÞ  gmP , ð5:5Þ

zoN, LF  1=AðsÞ  gmN : ð5:6Þ

However, as the EA has limited bandwidth and cannot respond to the out-of-
band high-frequency (HF) signals, hence A(s)  0 at HF. Therefore, at high
frequency the two output impedances are different, and are given by

zoP, HF  1=sCL , ð5:7Þ

zoN, HF  1=ðsCL þ gmN Þ: ð5:8Þ

Obviously, the NMOS LDO has lower output impedance than that of the PMOS
LDO at frequencies higher than the unity gain bandwidth of the EA. At such high
frequencies, PMOS LDO does not respond to the load changes as fast, and only the
load capacitor CL provides the transient current to the load. For the NMOS LDO, on
the other hand, when VOUT drops due to a heavy load step, MN1 automatically has a
larger VGS and thus provides more current immediately to the load. This is an
intrinsic property of a source-follower stage. Therefore, despite a higher driving
voltage is required, the NMOS LDO is commonly used for digital loads that
generate large and fast load transients and do not have stringent requirement on
supply accuracy [3, 4].
In addition, the electrons of an N-type transistor have higher mobility than the
holes of a P-type transistor. Hence, the size of an NMOS LDO can be very small,
even if the area of the additional step-up charge pump is included. Moreover, in
many emerging high-power technologies such as the Gallium Nitride (GaN) and the
5.3 Control Loop Design 101

laterally diffused MOSFET (LDMOS) processes, only the N-type power transistors
are available, and circuit designers have the only choice of designing NMOS LDOs.

5.3 Control Loop Design

5.3.1 Dominant Pole Considerations

Capacitors are needed for filtering and compensation but at the same time limit the
bandwidth of an analog circuit. For an LDO regulator, the largest capacitors are the
output filtering capacitor CL and the parasitic gate capacitor Cg of the power MOS
transistor. Hence, there are at least two low-frequency poles on the left-half-plane
(LHP): the pole at the output node –pOut, and the pole at the gate of the power MOS
–pGate, as sketched in Fig. 5.4 with either –pOut or –pGate being the dominant pole.
For convenience, we will refer to the magnitude of the pole pX as the pole, while it
is understood that the actual pole location is –pX. Now, the pole pOut would shift to a
lower frequency when the load resistance increases, and vice versa. Basically, LDO
regulators with an off-chip filtering capacitor are designed to be pOut dominant [5–
8], while most of the fully-integrated output-capacitor-less LDO regulators have an
internal dominant pole [9–13]. Thus, LDO regulators can be classified by the need
for an off-chip capacitor or not, or they can be classified by being output-pole
dominant or internal-pole dominant [1]. Therefore, there are 4 combinations of
which the pros and cons are summarized in Table 5.1 and discussed as follows.
There are many benefits in designing pOut as the dominant pole by using most of
the available capacitance (area) at the output node. First of all, a larger output
capacitor filters out power supply noise and glitches and serves as a buffer for load-
transient current changes, resulting in a smaller ΔVOUT. Second, as shown in
Fig. 5.4c and Fig. 5.4d, because the output voltage is well regulated by the control
loop at low frequency, and the noise is bypassed to ground by CL at high frequency,
the worst case power supply ripple rejection (PSRR) would occur at medium
frequency [14]. Thus, increasing both the output capacitance and the loop band-
width (that is, the unity-gain frequency, UGF) would improve the PSRR. Third, as
the load current decreases, pOut moves to lower and lower frequency, and it is easier
to maintain loop stability compared to the internal-pole dominant case. Actually,
the zero-load condition had been ignored/omitted in many output-capacitor-less
designs, and instead, a minimum load current (IO,Min) was required to satisfy the
stability requirements. If CL is reduced to satisfy the stability requirements, the
high-frequency PSRR performance will be degraded, and may not be acceptable in
many applications. For the WPT receiver, good PSRR at the WPT frequency and its
harmonic frequencies (in the 10 MHz or even 100 MHz range) are important to the
system.
For the pOut dominant case, pole-zero cancellation is usually used to extend the
loop bandwidth and to enhance the stability. The LHP zero may be generated by the
102 5 Linear Regulators for WPT

Fig. 5.4 Conceptual frequency response of generic LDO regulators with two LF poles: (a) open
loop-gain with pOut being its dominant pole, (b) open loop-gain with pGate being its dominant pole,
(c) PSRR with pOut being its dominant pole, and (d) PSRR with pGate being its dominant pole

Table 5.1 LDO categorization by dominant pole location

Integration With off-chip cap. Fully-on-chip
Dominant pole pGate pOut pGate pOut
Process scaling No Yes No Yes
Limit on IO,Min Yes No Yes No
UGF Low Medium Medium High
Transient ΔVOUT Medium Small Large Medium
PSRR – √  –
Quiescent current Low Medium Low High

equivalent series resistance (ESR) of CL, or by a high-pass feedback network

as proposed in [9], or by techniques published in the recent literature. Alterna-
tively, the non-dominant pole pGate may be pushed to frequencies higher than the
UGF by circuit techniques such as adaptive current biasing, gm boosting, enhanced
super source-follower (SSF), etc. [2, 6–8, 15]. The only drawback with the pOut
dominant case is that a relatively high quiescent current is needed to push the
internal poles to higher frequencies. This requirement can be relaxed by using
advanced processes that have lower parasitic capacitance. The transistors will have
smaller feature sizes, and the internal poles could be moved to higher frequencies
5.3 Control Loop Design 103

with the same bias current. At the same time, smaller CL can be used and results in
smaller chip area and higher UGF.
To summarize, an LDO regulator with pOut dominant can maintain small VOUT
variations and drive large capacitive loads. Also, it can benefit from process scaling
that is one of the most desirable characteristics in integrated-circuit design.

5.3.2 Replica Regulator

The replica biasing technique is widely used in source-follower based LDO regu-
lators, for supplying the digital circuits with ultra-fast load-transient responses, or
for realizing internal rails for gate-drive buffers. Figure 5.5 shows the schematic of
a typical replica regulator that has a replica biasing branch formed by IB and MN1.
The EA only senses VMIR that is the source voltage of MN1, and generates VG for
both MN1 and MN2, while MN2 supplies the current IL to the load. Obviously, to
make VOUT closely equal to VMIR and consequently VREF, the size ratio of MN2 and
MN1 should be the same as the ratio between IL and IB. As the load current IL
changes, VOUT will deviate from the designed value. This structure provides fast
load-transient response, but at the same time sacrifices output voltage accuracy that
sometimes are acceptable for driving digital loads.

5.3.3 Flipped Voltage Follower

The flipped voltage follower (FVF) [16] based LDO regulator is one of the most
popular architectures due to its simplicity and the potential for fast transient
response [1, 2, 10, 12, 13]. The schematic of a single-transistor-control LDO
based on FVF in [12] is shown in Fig. 5.6 as an example. This circuit can be
divided into three parts: the EA, the VSET generation, and the flipped voltage
follower. For simplicity, we assume I1 ¼ I2 and (W/L )7 ¼ (W/L )8. The mirrored
voltage VMIR is controlled by the EA to be equal to VREF, and VSET is generated
from VMIR by the diode-connected transistor M7. Followed by a FVF stage, VOUT is
set by VSET through M8, and it is a mirrored voltage of VMIR. In the FVF stage, M8
act as a common-gate amplifying stage from VOUT to VG.
Obviously, there are two low-frequency poles ( pG and pOut) in the FVF loop
when a relatively large on-chip CL is used to handle the large load-transient current.
This topology is very difficult (if not impossible) to be stable if pOut is the dominant
pole. Another issue associated with this structure is the DC accuracy of VOUT. The
offset voltage between VREF and VOUT can be divided into two parts. First, there is
an offset between VREF and VMIR that consists of systematic and random offsets of
the EA. Second, the mismatches between the voltage mirror (M7 and M8) and the
bias currents (I1 and I2) will generate an offset between VMIR and VOUT. Hence, the
FVF-based topology has low immunity to the process, voltage, and temperature
104 5 Linear Regulators for WPT

Fig. 5.5 Schematic of a

typical replica regulator

Fig. 5.6 Schematic of the single-transistor-control LDO regulator based on the FVF topology

(PVT) variations. Moreover, the loop gain of the simple FVF is low, which results
in poor load regulation, and tens of mV of VOUT variations can be easily observed
due to the load current change.
Since the FVF-based LDO regulator is a single-ended topology, for similar
dynamic performance, the FVF-based LDO regulator only consumes 50% of the
bias current compared to a conventional LDO regulator that uses a differential
EA. Although the FVF-based LDO regulator also consists of an auxiliary EA with
differential input stage, it is not in the main loop, and only serves as a bias voltage
generator and consumes only very low current. Thus, the FVF-based LDO regulator
can be more power-efficient. The FVF with folded-cascode gain stage used in
[10, 13] can provide higher loop gain and better DC regulation.
5.3 Control Loop Design 105

Fig. 5.7 Schematic of the

LDO regulator with an
impedance attenuation
buffer stage

5.3.4 Impedance Attenuation Buffer

To effectively push internal poles to higher frequencies, one can split a

low-frequency pole into two high-frequency poles. An impedance attenuation
buffer can be inserted between the gain stage that has high output impedance and
the power stage that has large input capacitance, as shown in Fig. 5.7. The buffer
presents low input capacitance to VA and low output impedance to VG, therefore,
generates two high-frequency poles pA and pG. The buffer can simply be a source
follower, or a super source follower (SSF) that further reduces the output imped-
ance by employing negative feedback loop [17]. Detailed analysis of the super
source follower is given in the design case study in the next section.

5.3.5 Digitally Controlled LDO Regulator

Digital low-dropout (D-LDO) regulator has been a popular research topic in recent
years for its low-voltage operation and process scalability [18–24]. The basic
operation principle is straightforward and can be illustrated by Fig. 5.8. The
D-LDO regulator employs one clocked-comparator which can be considered as a
1-bit analog-to-digital converter (ADC), one bi-directional shift-register array and
one power transistor array. The D[1:n] with unary code controls the number of unit-
transistors to be turned on and consequently the total output current. The compar-
ator compares VREF and VOUT in every clock cycle to decide whether the shift
register output bits D[1:n] shift to the left (add a “1”) or to the right (add a “0”).
Obviously, the shift register acts as an integrator in the control loop, and results in a
pole at DC. The clocked-comparator can operate at low supply voltages (0.5 V for
example) and consumes no static current, while other digital cells can operate at
low voltage as well.
The transient response time of the digital LDO regulator is proportional to its
clock frequency and the size of each power unit-transistor. Thus, coarse-fine tuning
and adaptive clock techniques can be used to improve its transient response without
increasing the standby power [22]. In addition, digital codes can be easily
106 5 Linear Regulators for WPT

Fig. 5.8 Schematic of a

conventional digital LDO
regulator

reprogrammed to achieve different step transitions and/or dynamic voltage scaling,

which enable convenient system-level reconfigurations. These features of the
digital LDO regulator help it to be implemented in low-power low-voltage appli-
cations, such as implantable medical devices and wireless sensor nodes.
Similar to the digitally-controlled switching converters, digital LDO regulators
also suffer from the problem of limit cycle oscillation (LCO) due to the finite
resolution of the output current. When LCO occurs, the code D[1:n] will periodi-
cally jump between two or multiple consecutive states, and results in undesirable
steady-state output voltage ripples. Furthermore, light-load condition results in a
larger load resistance RL, and the same unit-current will generate a larger LCO
amplitude. Meanwhile, lower clock frequency results in longer charging and
discharging times of CL, which will also incite a larger LCO amplitude. This
problem can be mitigated by using multi-bit ADC, or by adding a feed-forward
path with one-bit strength to compensate for the slow main shift-register loop, or by
introducing a dead zone to the comparator as discussed in [23, 24].

5.4 Design Case Study

In this section, two LDO regulators, one designed in a 65 nm CMOS process and
another in a 28 nm bulk CMOS process will be presented. The basic design
guideline for these LDO regulators is to set the dominant pole at the output node
by pushing the internal poles to high frequencies, and consequently the LDO
regulators enjoy better transient and PSRR performance from process scaling.

5.4.1 Design of Tri-Loop LDO Regulator

To realize a current-efficient LDO regulator with pOut dominant, internal poles

should be pushed to high frequencies not only by using large bias current but also
with innovative circuit techniques. This case study presents a fully-integrated
tri-loop LDO regulator designed in a 65 nm CMOS general purpose (GP) process
5.4 Design Case Study 107

to achieve ultra-fast transient response and full spectrum (DC to 20 GHz tested)
PSRR with limited chip area, current budget and voltage headroom [25].

5.4.1.1 Tri-Loop Design

The transistor-level schematic of the tri-loop LDO regulator is shown in Fig. 5.9,
with the signal paths of each loop superimposed on the schematic. Each loop has a
different function. Loop-1 is an ultra-fast low-gain loop with the dominant pole pOut
at the output, and internal non-dominant poles pGate and pA are pushed to the GHz
range by the impedance attenuation buffer technique. Loop-2 is composed of the
EA and the diode-connected M7 and is a slow loop that generates the voltages of
VMIR and VSET. Loop-3 feeds VOUT back to the EA such that the DC accuracy is
improved. In other words, Loop-1 is used to deal with the fast load-transient
current; Loop-2 generates DC biases; while Loop-3 is used to enhance the VOUT
DC accuracy. The output capacitor CL is 130 pF, the bias current of M8 is 20 μA,
and the buffer consumes another 20 μA at light load (60 μA at heavy load), and all
the above assignments help pushing the internal poles to the GHz range.
To increase the DC accuracy of the FVF-based LDO regulator, a third loop is
introduced through using a tri-input EA. In conventional architectures, only VMIR is
fed forward to generate VOUT, and VOUT is not fed back to the EA. Now, the EA
compares VREF with both VMIR and VOUT, and the W/L ratios of the three input
transistors M1, M2 and M3 are (W/L)1:(W/L)2:(W/L)3 ¼ 4:1:3 such that VOUT is
computed to be
 
1 3
V REF
V MIR
V OUT  AEA ¼ V OUT ð5:9Þ
4 4
V MIR ¼ V OUT þ ΔV, ð5:10Þ

where AEA is the gain of the EA (including the VSET generation stage), and ΔV is
the voltage difference between VMIR and VOUT due to PVT and load variations. By
substituting (5.10) into (5.9), and assuming AEA >> 1, we have

AEA ΔV  AEA =4 ΔV
V OUT ¼ V REF
 V REF
, ð5:11Þ
1 þ AEA 1 þ AEA 4
AEA 3ΔV  AEA =4 ΔV
V MIR ¼ V REF þ þ :
1 þ AEA 1 þ AEA 1 þ AEA
ð5:12Þ
3ΔV
 V REF þ
4

Therefore, VOUT is closer to VREF than VMIR by setting the size ratio of M2 and
M3 to be 1:3.
Since the EA is not in the high-speed path, the input transistors of the EA and its
tail current mirror are implemented with 2.5-V I/O devices for DC gain and
108 5 Linear Regulators for WPT

Fig. 5.9 Schematic of the tri-loop LDO regulator

electrostatic discharge (ESD) protection considerations. All on-chip MOS capaci-

tors are I/O devices to avoid gate leakage current if thin-oxide (1.0 V) devices are
used. Transistors in the FVF stage are all thin-oxide devices for fast response. To
save static current, the ratio of M7 and M8, and that of their bias currents, is set to be
1:4, as VSET is in the low-speed path that does not need much current, but VA is in
the high-speed path and needs more current.

5.4.1.2 Buffer Design

The full schematic of the tri-loop LDO regulator including the impedance attenu-
ation buffer is shown in Fig. 5.10. The modified super-source-follower (SSF) buffer
used for impedance attenuation consists of M9 through M11, and three parameters of
the buffer are of concern: the input capacitance CiB, the output resistance roB, and
the DC gain AB. The small-signal model of the buffer is shown in Fig. 5.11. The
input capacitance of the circuit can be computed by noting that

CiB ΔVg ¼ Cgs ΔVgs þ Cgd ΔVgd , ð5:13Þ

and in the small-signal limit, (5.13) can be rewritten as

CiB ¼ 1
vs =vg  Cgs þ 1
vd =vg  Cgd , ð5:14Þ

where Cgs and Cgd are the gate-to-source and gate-to-drain capacitances of M9. The
voltage gains are calculated as
5.4 Design Case Study 109

 
vs 1 2
AB ¼ ¼ 1= 1 þ þ , ð5:15Þ
vg A1 A1 A2

with

A1 ¼ gm9 =gds9 , ð5:16Þ

A2 ¼ ðgm11 þ gds12 Þ=gdsT , ð5:17Þ
gdsT ¼ gm10 þ gds10 þ gds11 þ gds13 : ð5:18Þ

and

vd vd vs 1 vs A1
¼ ¼
¼
: ð5:19Þ
vg vs vg A2 vg A1 A2 þ A2 þ 2

Here, A1 is the intrinsic gain of M9, and
A2 is the gain from the drain to the
source of M9. Assume A1 and A2 to be much larger than 1, then AB  1. Combining
(5.14), (5.15) and (5.19), we have
 
A2 þ 2 A1
CiB ¼ Cgs þ 1 þ Cgd
A1 A2 þ A2 þ 2  A1 A2 þ A2 þ 2
ð5:20Þ
1 1
 Cgs þ 1 þ Cgd  Cgd :
A1 A2

Since M9 operates in the saturation region, most of the channel charge is

associated with the source, which means that Cgs is much larger than Cgd, and
hence, CiB is small. The output resistance of the buffer roB is given by

1
r oB ¼ , ð5:21Þ
A3 ðgm9 þ gds9 Þ þ gdsT

where A3 ¼ (gm11 + gds12)/(gds12 + gds9). To further attenuate roB, the gain A3 needs
to be increased. The last term gdsT includes gm10 and gds10 from M10, and gds11 from
M11. Lowering roB by increasing gm10 also increases the pull-up capability of the
modified SSF.
A fundamental trade-off of designing the SSF is identified between the DC gain
and the frequency response: to satisfy the assumption that A1, A2 >> 1, the channel
length L of M9 and M11 should be long; but to reduce Cgs and Cgd, L of M9 and M11
should be short. In this design, the minimum L is used for M9 and M11 for speed
consideration, and M11 operates in the sub- or near-threshold region (in light or full
load conditions, respectively) to give a larger gm11 to increase A2 and A3. Actually,
M9 and M11 formed a local negative feedback loop. The gate capacitance of M11,
which would generate an additional pole pD at node VD, is neglected in the analyses
above. This non-dominant pole pD is located in the GHz range as verified by the
following AC simulations and transient measurements.
110 5 Linear Regulators for WPT

Fig. 5.10 Full transistor-level schematic of the tri-loop LDO regulator

Fig. 5.11 Small-signal model of the super source follower

5.4.1.3 Stability Design

To simulate the frequency response of each loop, three simulation setups are
configured and described as follows.
Setup 1 As shown in Fig. 5.12 the signal path of Loop-1 is broken between VA and
the buffer input. The AC small signal is injected to the buffer input and the output is
observed at VA. To isolate the influence from Loop-2 and Loop-3, the path from M7
to M8 is also broken. To maintain the DC bias point, a DC voltage VSET is applied to
the gate of M8. And to account for the loading effect, a replica buffer stage is added
to VA to mimic CiB.
5.4 Design Case Study 111

Fig. 5.12 Break Loop-1 with replica buffer connected to VA to mimic the buffer input capacitance

Setup 2 Loop-2 and Loop-3 are broken from VMIR to M2 and from VOUT to M3,
respectively, as shown in Fig. 5.13. The AC small signal is injected into the EA
through M2 only. Now, the AC response of Loop-2 can be obtained at VMIR, and the
response of Loop-3 can be obtained at VOUT, simultaneously. Since the size ratio of
M2 and M3 is 1:3, the gain of Loop-3 should be 3 times higher than that of Loop-2.
Loop-2 and Loop-3 can be considered together because they both contain the EA in
their respective loops.
Simulation results of these two setups are combined in Fig. 5.14, which shows
the Bode plots of the three loops at heavy-load condition with RL ¼ 100 Ω and
VOUT ¼ 1.0 V. Loop-1 has a DC gain of 21 dB and its UGF1 is 600 MHz, with a
phase margin (PM1) of 60 . Loop-2 has one dominant pole located at VSET and a
non-dominant pole located at VEA, and PM2 ¼ 80 . Loop-3 has two non-dominant
poles located at VOUT and VEA, respectively, and PM3 is only 20 . Nevertheless, the
stability of the circuit is determined by the system loop gain, not individual loop
gains. A third loop-breaking setup for stability analysis is shown in Fig. 5.15, and
described as follows.
Setup 3 Loop-2 and Loop-3 contain the error amplifier, and by breaking the loops
between VEA and the gate of M6 we have

gm2 ðr o1 jjr o4 Þ
vea ¼ ðvmir þ 3vout Þ, ð5:22Þ
1 þ sCEA ðr o1 jjr o4 Þ
112 5 Linear Regulators for WPT

Fig. 5.13 Break Loop-2 and Loop-3 simultaneously for individual analysis

vmir
gm6 ðr o6 jjr o15 Þ

 , ð5:23Þ
vac 1 þ sCB ðr o6 jjr o15 Þ
vset 1
 , ð5:24Þ
vmir 1 þ 1=A7 ðsÞ
vout 1 1
 
vmir 1 þ 1=A8
1=A8 AP ðsÞ 1 þ 1=A7 ðsÞ
ð5:25Þ
1 1 A8 A7 ðsÞ
  ¼  ,
1 þ 1=A8 1 þ 1=A7 ðsÞ 1 þ A8 1 þ A7 ðsÞ
A7 ðsÞ ¼ gm7 r o15 =ð1 þ sCB r o15 Þ, ð5:26Þ
A8 ¼ gm8 r o8 , ð5:27Þ
gmP ðr oP jjRL Þ
A P ðsÞ ¼ , ð5:28Þ
1 þ sCL ðr oP jjRL Þ

where vac is the AC signal injected at the gate of M6, CEA is the parasitic capaci-
tance at the VEA node, and rop is the output resistance of MPass. The system loop-
gain function of the entire tri-loop LDO regulator is given by
5.4 Design Case Study 113

Fig. 5.14 Simulated frequency response of the three loops with VIN ¼ 1.2 V, VOUT ¼ 1.0 V and
RL ¼ 100 Ω

Fig. 5.15 Break the loop at the EA output

114 5 Linear Regulators for WPT

vea gm2 ðr o1 jjr o4 Þgm6 ðr o6 jjr o15 Þ

T ðsÞ ¼
¼
vac ð1 þ sCB ðr o6 jjr o15 ÞÞð1 þ sCEA ðr o1 jjr o4 ÞÞ
3gm2 ðr o1 jjr o4 Þgm6 ðr o6 jjr o15 Þ A8
þ  
ð1 þ sCB ðr o6 jjr o15 ÞÞð1 þ sCEA ðr o1 jjr o4 ÞÞ 1 þ A8
A 7 ðsÞ gm2 ðr o1 jjr o4 Þgm6 ðr o6 jjr o15 Þð1 þ 4gm7 r o15 þ sCB r o15 Þ
 :
1 þ A7 ðsÞ ð1 þ sCB ðr o6 jjr o15 ÞÞð1 þ sCEA ðr o1 jjr o4 ÞÞð1 þ gm7 r o15 þ sCB r o15 Þ
ð5:29Þ

There are three LHP poles and one LHP zero in the system loop-gain function,
while the dominant pole is generated by CB. The zero is generated by Loop-2,
which is a shorter path compared to Loop-3. It is a pole-zero tracking pair that
makes the entire LDO stable under all loading conditions. The simulated Bode plots
of Setup 3 in different corners are given in Fig. 5.16. The worst case phase margins
are 68 at 10 mA loading (RL ¼ 100 Ω) and 38 at no load condition, respectively.
In this design case, the (W/L) ratio of M2 and M3 is aggressively set to be 1:3.
This setting is to trade stability margin for better VOUT DC accuracy. To gain more
design margin for stability, the weighting of M2 and M3 could be set to 2:2 but with
lower DC accuracy. Alternatively, in another extreme case, with M2 (Loop-2) being
removed and M3 having the same size as M1, the DC accuracy is maximized.
However, the dominant pole of Loop-3 at VSET has to be much lower than before,
and the settling time of VOUT will be much longer due to a slow Loop-3.

5.4.1.4 Load Regulation

Simulated curves of load regulation are shown in Fig. 5.17, with the size ratio of M2
and M3, (W/L)2:(W/L)3, being set to 1:3, 2:2 and 1:0 (no Loop-3), respectively. In
the case of no Loop-3, VOUT changed by 34 mV when the load current is changed
from 10 μA to 10 mA. For our proposed case of 1:3, VOUT changed by only 11 mV
with the same change in load current. DC accuracy is improved by about 3 times by
adding Loop-3 without degradation in stability and speed performance. If the ratio
of M2 and M3 is set to 2:2, VOUT would change by 20 mV.

5.4.1.5 Power Supply Ripple Rejection

PSRR is the most important specification of an LDO regulator designed for noise-
sensitive loads. Supply ripples are mainly due to the output voltage ripples from the
pre-stage DC-DC converter or AC-DC rectifier, and from the on-chip noise gener-
ated by the digital/driver circuits. Ripples generated by the rectifier in the WPT
receiver could have harmonics as high as tens of mega-Hertz.
In the first design case, DC gain of Loop-1 has been sacrificed for fast transient
response. Increase DC gain of Loop-1 needs additional stages that will introduce
undesired LF poles. By setting pOut as the dominant pole, most of the silicon area
5.4 Design Case Study 115

Fig. 5.16 Simulated Bode plot of the tri-loop LDO with VIN ¼ 1.2 V and VOUT ¼ 1.0 V, at the
corners of TT at 25 , SS at 85 and FF at
20

Fig. 5.17 Load regulation

performances with (W/L)2:
(W/L)3 being set to 1:3 and
2:2, respectively; and the
case without Loop-3

(capacitance) can be effectively used to stabilize VOUT and reject noise from VIN.
The simulated PSRR curves of the proposed LDO regulator with full load and no
load are shown in Fig. 5.18a; and the PSRR of the tri-loop regulator with and
without CB, and the PSRR of the regulator with only Loop-1 and CB, are given in
Fig. 5.18b, respectively. At medium- and high-frequency ranges, the light-load
PSRR is better than the full-load PSRR, because CL can more effectively bypass the
ripple in the VHF (very high frequency, 30 MHz–300 MHz) range to ground when
it is in parallel with a larger RL.
116 5 Linear Regulators for WPT

Fig. 5.18 (a) Simulated PSRR of the designed LDO regulator; and (b) the PSRR of Loop-1 only
and the tri-loop regulator with or without CB, with VIN ¼ 1.2 V, VOUT ¼ 1.0 V, and RL ¼ 100 Ω

The PSRR at low frequencies with Loop-1 only is poor due to its low DC gain.
With the designed tri-loop architecture, a 9 dB PSRR improvement is observed at
frequencies lower than 1 MHz, compared to the case with Loop-1 only. For the
FVF-based structure, VOUT is a strong function of VSET. Therefore, adding a bypass
capacitor CB (about 7 pF in this design) at the VSET node could improve the PSRR
by filtering out the ripples that come from VMIR to VOUT. Adding CB is effective in
the medium-frequency range (around 100 MHz–1 GHz), as the stability of Loop-3
is improved with a lower frequency dominant pole at VSET. However, adding CB
will lower the bandwidths of Loop-2 and Loop-3, which are also the PSRR corner
frequency of around 1 MHz. The long-channel transistor M10 introduces an addi-
tional path from VIN to VG that slightly helps to improve PSRR at high frequencies.
5.4 Design Case Study 117

5.4.1.6 Measurement Results

The measurement setup of the LDO regulator with on-chip loading for load-
transient measurement is shown in Fig. 5.19. The on-chip RL is connected in series
with the switch S1 (implemented by a 1.0 V device) driven by an on-chip inverter
buffer that achieves load-current edge times TEdge (that is, rise and fall times) of less
than 200 ps. The static currents of the chip with S1 ON and with S1 OFF are
measured as IMAX and IQ, respectively. The dropout voltage is measured to be
150 mV at IMAX (the worst case). With chip-on-board setup, all the transient
waveforms are collected by a pair of 7-GHz differential probes with input imped-
ance of 50 kΩ || 0.32 pF connected to a 4-GHz oscilloscope. Single bond-wire is
bonded to each input/output terminal of the prototype. The parasitic RLC low-pass
filter consists of the 2-nH bond-wire inductance and the input impedance of the
probe, of which the cutoff frequency is over 6 GHz. With this setup, ultra-fast
transient currents and voltages are generated and measured.
The micrograph of the tri-loop LDO regulator with on-chip loading is shown in
Fig. 5.20. The chip area is 260  90 μm2, including 140 pF of on-chip capacitors
and the circuit for generating load transients. Fig. 5.21 shows the measured tran-
sient response of the output voltage VOUT with on-chip load current change from
0 μA to 10 mA within 200 ps, with zoom-in details of the undershoot and overshoot
voltages. With a quiescent current of only 50 μA, the measured undershoot voltage
was 43 mV, and VOUT recovered to its steady-state value in 100 ns with the help of
Loop-3 regulation. When the load current stepped from 10 mA to 0 μA, the
measured overshoot voltage was 82 mV, and VOUT was gradually discharged by
the bias current of M8, and then regulated by Loop-3 to its steady-state value. The
well-behaved transient waveforms of VOUT confirmed the stability of the designed
tri-loop LDO regulator. To make comparison, a figure-of-merit (FOM) of speed for
the LDO regulators is defined in [10] and widely adopted by other researchers. It
reads.

IQ C  ΔV OUT IQ
FOM ¼ T R ¼  , ð5:30Þ
I MAX I MAX I MAX

where IQ is the quiescent current, and the response time TR is a function of the total
on-chip capacitance C, load-transient glitches of the output voltage ΔVOUT and the
maximum load current IMAX. The FOM calculated for this design case is 5.74 ps,
with a response time of 1.15 ns. The FOM is expected to be improved further with
process scaling, as demonstrated in the following design case with a 28 nm bulk
CMOS process. Note that FOM improvement does not necessarily hold for the
internal-pole dominant cases, because low loop bandwidth is required by IO,MIN for
the LDO regulators to be stable, as discussed in Sect. 5.3.1.
Figure 5.22 shows the measured PSRR of the designed LDO regulator from DC
up to 20 GHz. For low frequencies, the PSRR is better than
21 dB; while the worst
case occurs at 5 MHz with
12 dB rejection. The PSRR at 1 GHz is
15 dB. For
frequencies higher than 2.5 GHz, PSRR would be dominated by the ESR of the
118 5 Linear Regulators for WPT

Fig. 5.19 Measurement

setup of the LDO regulator
with on-chip load

Fig. 5.20 Micrograph of

the LDO regulator with
on-chip load

filtering capacitors (CL and CB). Since the ESR zero is not needed in the proposed
architecture, ESRs of the on-chip capacitors are minimized in the layout design by
using multiple small capacitors in parallel to achieve good PSRR. Due to the
parasitic bond-wire inductance and the substrate-to-PCB resistance, PSRR varia-
tions are observed at the VHF region.
Performance comparisons with state-of-the-art LDO regulators are summarized
in Table 5.2. Compared to previous designs with ultra-fast transient response
[10, 26], response time on the order of nanosecond is achieved by the proposed
architecture with much smaller IQ and CL, and hence resulting in a very good FOM.
Furthermore, full spectrum PSRR characteristic is achieved, while other fully-
integrated LDO regulators only give good PSRR at specific frequencies.
5.4 Design Case Study 119

Fig. 5.21 Measured transient response with VIN ¼ 1.2 V, VOUT ¼ 1.0 V, and on-chip loading
change from 0 μA to 10 mA with edge times of 200 ps

5.4.1.7 Conclusions for the Tri-Loop Design

In this case study, a fully-integrated LDO regulator with fast transient response and
full spectrum PSRR characteristic is presented. The tri-loop architecture based on
the flipped voltage follower and impedance attenuation buffer techniques is
designed and verified in a 65 nm CMOS process. With the combined effects of
the high-bandwidth Loop-1, CL and CB, full-spectrum PSRR is achieved. With the
additional Loop-3, VOUT DC accuracy is improved by 3 times compared to the
conventional FVF-based LDO regulator. By comparing the performance and design
methods of previous non-fully-integrated and fully-integrated LDO regulators, a
gap between transient and PSRR performance has been identified and investigated
in this research. Of course, higher PSRR in the low and medium frequency ranges
will further be improved in the future. As the FOM of this design scales with the
120 5 Linear Regulators for WPT

Fig. 5.22 Measured PSRR

up to 20 GHz with full load
and no-load

Table 5.2 Comparisons for the Tri-loop LDO regulator

Publication [10] JSSC 2005 [13] JSSC 2010 [26] JSSC 2012 This work
CL On-chip
Technology 90 nm 90 nm 45 nm SOI 65 nm
VOUT 0.9 V 0.5–1 V 0.9–1.1 V 1V
Dropout 300 mV 200 mV 85 mV 150 mV
IQ 6 mA 8 μA 12 mA 50-90 μA
IMAX 100 mA 100 mA 42 mA 10 mA
Total Cap. 600 pF 50 pF 1.46 nF 140 pF
PSRR N/A 0 dB @1 MHz N/A
15.5 dB @1GHz
ΔVOUT@TEdge 90 mV @100 ps 114 mV @100 ns N/A 82 mV @200 ps
DC Load Reg. 90 mV 10 mV 3.5 mV 11 mV
TR 0.54 ns N/A 0.288 nsa 1.15 ns
FOM 32 ps N/A 62.4 psa 5.74 ps
a
Based on simulation

process, the proposed architecture will perform better by using more advanced
processes.

5.4.2 LDO Regulator with Enhanced Super Source Follower

The cascode FVF topology results in higher DC loop gain and consequently higher
UGF, but it is more difficult to make the loop stable, especially when the UGF is in
the ultra-high frequency (UHF) band. As shown in Fig. 5.23, with 28 nm process
available for the second case study, cascaded buffers are inserted to drive the power
5.4 Design Case Study 121

Fig. 5.23 Schematic of the cascode FVF-based LDO regulator with cascaded buffers

transistor MPass, which only add tiny load capacitance to the node VA2. The first
buffer B1 is simply an NMOS source follower, and the second one B2 is an
enhanced super source follower (E-SSF) [2].
The transistor-level schematic of the cascode FVF-based LDO regulator with
E-SSF is shown in Fig. 5.24. Similar to the previous case study, VOUT is a mirrored
voltage of VMIR, both of which are one VGS higher than VSET. The function of the
left part is to generate the bias voltage VSET. In conventional voltage reference
circuit design, VREF is commonly generated by feeding a current through a resistor.
When VREF is close to the supply voltage VIN, there is not enough voltage headroom
to implement an accurate current source, and the accuracy of VREF will be degraded.
To use a lower reference voltage VREF, a resistor ladder of R1 and R2 is employed to
divide down VMIR and to feed it back to the EA differential input.
The right part of the schematic shows the core circuits of the cascode FVF-based
structure with the enhanced super source-follower. M1 and M2 serve as two
common-gate amplification stages that provide the sufficient DC gain. M3 is an
NMOS source follower that presents low input capacitance to the VA2 node, and
also shifts VA2 down to VBUF, providing more voltage headroom for VG. To
effectively drive MP, a lower output impedance due to the SSF is needed. In the
conventional SSF, only M4 and M6 are used, while in the E-SSF, M5 is inserted
between M4 and M6. Now, M4, M5 and M6 form a negative feedback loop with
higher gain compared to the conventional SSF. The output impedances of the
conventional and the enhanced SSF are

1
r oB, SSF  , ð5:31Þ
gm4  gm6 r o4
122 5 Linear Regulators for WPT

Fig. 5.24 Schematic of the cascode FVF-based LDO regulator with E-SSF

1
r oB, E-SSF  , ð5:32Þ
gm4  gm6 r o4  gm5 r o5

respectively. The inserted common-gate amplification stage formed by M5 reduces

the output impedance of the SSF buffer by a factor of gm5ro5, therefore, providing a
larger driving capability.
To reduce the chip area, C1 and CL are implemented by low-voltage low-leakage
MOS capacitors, with the values of 19 pF and 100 pF, respectively. An additional
1 pF is connected to the gate of the NMOS current mirrors for decoupling. Although
M2 and M5 need gate bias voltages VB1 and VB2, their gates can be connected to
VMIR to save additional bias branches. This bias voltage sharing configuration will
not affect the frequency characteristics as both gates of M2 and M5 have to be
referenced to ground.
The LDO regulator is simulated in a 28 nm bulk CMOS process. Figure 5.25
shows the AC responses that include the Bode plots and the PSRR curves, with the
load current ranging from 0.1 to 10 mA. The UGF of the cascode FVF loop with the
E-SSF is 1.28 GHz with a phase margin of 49 . The low-frequency PSRR is around

27 dB. Benefit from the UHF bandwidth, full-spectrum PSRR is achieved with the
worst case of
18.9 dB at 1.55 GHz. The supply noise at above 1 MHz from the left
part of Fig. 5.24 is filtered out by C1. Thus, the PSRR is improved in the 1 to
100 MHz range.
Figue 5.26 shows the transient response when the load current changes from
0.1 mA to 10 mA with the edge time TEdge of 30 ps. The undershoot and overshoot
voltages are 26 mV and 21 mV, respectively. The performance summary and
5.5 Summary and Discussion 123

Fig. 5.25 Simulated (a) Bode plot and (b) PSRR of the proposed LDO with load current ranging
from 0.1 mA to 10 mA

comparison with state-of-the-art designs are shown in Table 5.3. Comparing to the
tri-loop LDO regulator [1], this work improves the low-frequency PSRR by 6 dB,
and also improved the worst-case PSRR by 6 dB. For the load transient response,
the change in the output voltage ΔVOUT is reduced by 70%.

5.5 Summary and Discussion

One major difference between a switching power converter and a linear regulator is
their nature of energy conversion. The switching power converters use inductors
and/or capacitors to store the energy in one phase and then release the energy in the
other phase, while linear regulators simply consume or dump away the extra
energy. Hence, the efficiency of a series linear regulator is equal to VOUT/VIN,
assuming that the quiescent current consumed by the error amplifier is negligible. It
is also easier for a linear regulator to achieve a higher bandwidth compared to a
switching power converter. However, a linear regulator can only realize the voltage
step-down function.
In selecting the type of power transistors, regulators with an N-type power
transistor may need a step-up charge pump to provide a higher gate-drive voltage,
but it has intrinsic faster load transient response. Regulators with a P-type power
transistor are very suitable for the low-dropout design, but may need a larger load
capacitor and a more complicated control loop to achieve small output variations.
Therefore, the selection of regulator topology should be based on system require-
ments including but not limited to voltage headroom, current efficiency, speed and
noise requirements.
124 5 Linear Regulators for WPT

Fig. 5.26 Simulated load transient response of the LDO regulator with VIN ¼ 1.0 V, VOUT ¼ 0.8 V

Table 5.3 Comparisons of state-of-the-art LDO regulators

Publication [10] 2005 [27] 2014 [1] 2015 This work
Technology 90 nm 350 nm 65 nm 28 nm
VOUT 0.9 V 1.2 V 1V 0.8 V
Dropout 300 mV 600 mV 150 mV 200 mV
IQ 6 mA 44 μA 50–90 μA 100 μA
IMAX 100 mA 12 mA 10 mA 10 mA
Total Cap. 600 pF 100 pF 140 pF 120 pF
Worst Case N/A
38 dB
12 dB
18.9 dB
PSR @50 MHz @5 MHz @1.55GHz
ΔVOUT@TEdge 90 mV 105 mV @500 ns 82 mV @200 ps 26 mV @30 ps
@100 ps
TRa 0.54 ns N/A 1.15 ns 312 ps
FOMa 32 ps N/A 5.74 ps 3.12 ps
a
Based on simulation

As discussed in this chapter, for fast transient response and good PSRR at high
frequency, it is highly recommended to design the dominant pole to be at the output
node of the regulator, because in such a case most of the available on-chip capacitor
(area) is used to filter/attenuate the ripples and disturbances at the output. The
design guidelines are verified by two fully-integrated LDO regulator design exam-
ples detailed in this chapter. The first design is fabricated in 65 nm CMOS process
with a tri-loop architecture, while the second design is implemented in 28 nm bulk
CMOS process with enhanced super source follower. Both designs achieved full-
spectrum PSRR with limited on-chip capacitors and with a quiescent current of
100 μA.
References 125

References

1. Lu Y, Wang Y, Pan Q et al (2015) A fully-integrated low-dropout regulator with full-spectrum

power supply rejection. IEEE Trans Circuits Syst I Regul Pap 62:707–716. doi:10.1109/TCSI.
2014.2380644
2. Lu Y, Li C, Zhu Y et al (2016) A 312 ps response-time LDO with enhanced super source
follower in 28 nm CMOS. Electron Lett 52:1368–1370. doi:10.1049/el.2016.1719
3. Lu Y, Ki W-H, Yue CP (2016) An NMOS-LDO regulated switched-capacitor DC–DC
converter with fast-response adaptive-phase digital control. IEEE Trans Power Electron
31:1294–1303. doi:10.1109/TPEL.2015.2420572
4. den Besten GW, Nauta B (1998) Embedded 5 V-to-3.3 V voltage regulator for supplying
digital IC’s in 3.3 V CMOS technology. IEEE J Solid State Circuits 33:956–962. doi:10.1109/
4.701230
5. Rincon-Mora G, Allen PE (1998) A low-voltage, low quiescent current, low drop-out regula-
tor. IEEE J Solid State Circuits 33:36–44. doi:10.1109/4.654935
6. Lam Y-H, Ki W-H (2008) A 0.9V 0.35μm adaptively biased CMOS LDO regulator with fast
transient response. In: 2008 IEEE international solid-state circuits conference – (ISSCC),
pp 442–626
7. El-Nozahi M, Amer A, Torres J et al (2010) High PSR low drop-out regulator with feed-
forward ripple cancellation technique. IEEE J Solid State Circuits 45:565–577. doi:10.1109/
JSSC.2009.2039685
8. Ho M, Leung KN, Mak K-L (2010) A low-power fast-transient 90-nm low-dropout regulator
with multiple small-gain stages. IEEE J Solid State Circuits 45:2466–2475. doi:10.1109/JSSC.
2010.2072611
9. Leung KN, Mok PKT (2003) A capacitor-free CMOS low-dropout regulator with damping-
factor-control frequency compensation. IEEE J Solid State Circuits 38:1691–1702. doi:10.
1109/JSSC.2003.817256
10. Hazucha P, Karnik T, Bloechel BA et al (2005) Area-efficient linear regulator with ultra-fast
load regulation. IEEE J Solid State Circuits 40:933–940. doi:10.1109/JSSC.2004.842831
11. Gupta V, Rincon-Mora GA (2007) A 5mA 0.6μm CMOS miller-compensated LDO regulator
with
27dB worst-case power-supply rejection using 60pF of on-chip capacitance. In: 2007
IEEE international solid-state circuits conference – (ISSCC), pp 520–521
12. Man TY, Leung KN, Leung CY et al (2008) Development of single-transistor-control LDO
based on flipped voltage follower for SoC. IEEE Trans Circuits Syst I Regul Pap
55:1392–1401. doi:10.1109/TCSI.2008.916568
13. Guo J, Leung KN (2010) A 6-μW chip-area-efficient output-capacitorless LDO in 90-nm
CMOS technology. IEEE J Solid State Circuits 45:1896–1905. doi:10.1109/JSSC.2010.
2053859
14. Gupta V, Rincon-Mora G., Raha P (2004) Analysis and design of monolithic, high PSR, linear
regulators for SoC applications. In: Proceedings of IEEE international SOC conference, pp
311–315
15. Al-Shyoukh M, Lee H, Perez R (2007) A transient-enhanced low-quiescent current
low-dropout regulator with buffer impedance attenuation. IEEE J Solid State Circuits
42:1732–1742. doi:10.1109/JSSC.2007.900281
16. Carvajal RG, Ramirez-Angulo J, Lopez-Martin A et al (2005) The flipped voltage follower: a
useful cell for low-voltage low-power circuit design. IEEE Trans Circuits Syst I Regul Pap
52:1276–1291. doi:10.1109/TCSI.2005.851387
17. Gray PR, Hurst P, Lewis S, Meyer RG (2009) Analysis and design of analog integrated
circuits, 5th edn. Wiley, New York
18. Okuma Y, Ishida K, Ryu Y, et al (2010) 0.5-V input digital LDO with 98.7% current efficiency
and 2.7-μA quiescent current in 65nm CMOS. In: 2010 IEEE custom integrated circuits
conference (CICC), pp 1–4
126 5 Linear Regulators for WPT

19. Chen W-C, Ping S-Y, Huang T-C et al (2014) A switchable digital–analog low-dropout
regulator for analog dynamic voltage scaling technique. IEEE J Solid State Circuits
49:740–750. doi:10.1109/JSSC.2013.2297395
20. Gangopadhyay S, Somasekhar D, Tschanz JW, Raychowdhury A (2014) A 32 nm embedded,
fully-digital, phase-locked low dropout regulator for fine grained power management in digital
circuits. IEEE J Solid State Circuits 49:2684–2693. doi:10.1109/JSSC.2014.2353798
21. Nasir SB, Gangopadhyay S, Raychowdhury A (2016) All-digital low-dropout regulator with
adaptive control and reduced dynamic stability for digital load circuits. IEEE Trans Power
Electron 31:8293–8302. doi:10.1109/TPEL.2016.2519446
22. Huang M, Lu Y et al (2016) A fully integrated digital LDO with coarse–fine-tuning and burst-
mode operation. IEEE Trans Circuits Syst II Exp Briefs 63:683–687. doi:10.1109/TCSII.2016.
2530094
23. Huang M, Lu Y et al (2016) Limit cycle oscillation reduction for digital low dropout
regulators. IEEE Trans Circuits Syst II Exp Briefs 63:903–907. doi:10.1109/TCSII.2016.
2534778
24. Huang M, Lu Y, et al (2016) A digital LDO with transient enhancement and limit cycle
oscillation reduction. In: 2016 IEEE Asia Pacific conference on circuits and systems
(APCCAS), pp 1–4. doi:10.1109/APCCAS.2016.7803886
25. Lu Y, Ki W-H, Yue CP (2014) 17.11 A 0.65ns-response-time 3.01ps FOM fully-
integrated low-dropout regulator with full-spectrum powersupply- rejection for wideband
communication systems. In: 2014 IEEE international solid-state circuits conference –
(ISSCC), pp 306–307. doi:10.1109/ISSCC.2014.6757446
26. Bulzacchelli JF, Toprak-Deniz Z, Rasmus TM et al (2012) Dual-loop system of distributed
microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout
voltage. IEEE J Solid State Circuits 47:863–874. doi:10.1109/JSSC.2012.2185354
27. Zhan C, Ki W-H (2014) Analysis and design of output-capacitor-free low-dropout regulators
with low quiescent current and high power supply rejection. IEEE Trans Circuits Syst I Regul
Pap 61:625–636. doi:10.1109/TCSI.2014.2300847
Chapter 6
DC-DC Converters for WPT

Abstract Operation principles of both inductor-based and switched-capacitor

DC-DC converters are introduced in this chapter. Different aspects of these two
types of DC-DC converters are investigated and compared. In particular, benefits
and design obstacles of the time-interleaving multiphase topology are reviewed and
discussed. Simulation and measurement results show that the unity-gain bandwidth
of a pulse-frequency modulation (PFM) control loop can be designed to be a few
times higher than the switching frequency suitable for fast transient applications.

Keywords Wireless power transfer • DC-DC converter • Switched-capacitor •

Buck • Boost • Pulse-frequency modulation (PFM)

6.1 Introduction

As mentioned in previous chapters, a DC-DC converter can serve as the power supply
of the power amplifier (PA), and to modulate the PA output power by adjusting the
converter’s output voltage. A DC-DC converter can also be used to regulate the
output voltage and/or output current of a wireless power receiver efficiently.
The components available for power conversion are shown in Fig. 6.1. They
include capacitors, inductors, transformers, diodes, and also MOSFETs that act as
variable resistors or switches. Different from linear regulators that use MOSFETs as
variable resistors, as introduced in Chap. 5, DC-DC converters are non-linear voltage
regulators that use MOSFETs as switches. An ideal switch has zero resistance when
closed and infinite resistance when opened, and hence is lossless whether it is closed
or opened. This is one of the two key benefits of using a switching converter over a
linear regulator. Another benefit is that a switching converter can be configured to
perform voltage step-up, step-down and even polarity inversion, but a linear regulator
can only given an output voltage that is lower than the input voltage.
DC-DC converters can be categorized by their energy storage components: the
inductor-based DC-DC converter and the switched-capacitor (SC) DC-DC con-
verter. The typical DC-DC converters are shown in Fig. 6.2. Every DC-DC con-
verter contains at least two terminals (T1 and T2) that can be assigned as either the
input terminal or the output terminal depending on the specific design, one
input capacitor and one output capacitor (C1 and C2, the functions of which depend

© Springer Nature Singapore Pte Ltd. 2018 127

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_6
128 6 DC-DC Converters for WPT

Fig. 6.1 Components

available for power
conversion

on design), energy storage component(s), and switches. For the inductor-based

converter, by switching on and off the switches S1 and S2 alternatively, the energy
is stored in the magnetic field of the inductor L1 in one clock phase, and then be
delivered to the output in the next clock phase. The output voltage can be controlled
by changing the duty cycle of the switches. Based on the relationship between the
input and output voltages, a DC-DC converter can be classified as a step-down
(buck), step-up (boost) or step-up/down (buck-boost) converter. For the SC con-
verter, the energy is stored in the flying capacitor CF in one clock phase and be
transferred out in the other clock phase. Different from a switched-inductor con-
verter, output voltage regulation of the SC converter is usually achieved by fre-
quency modulation or capacitance modulation [1–4]. An interesting observation of
a DC-DC converter is that its direction of energy delivery is reversible. In other
words, the input and output terminals are interchangeable, according to the voltage
step-up/down requirement of the application. For the converters shown in Fig. 6.2,
if the power source is placed on the left such that the power flows from left to right,
they are step-down converters; and if the power source is placed on the right and the
power flows from right to left, they are step-up converters.

6.2 DC-DC Converter Comparisons

One important performance indicator of a DC-DC converter is efficiency. For

applications such as wireless charging of portable devices as discussed in this
book, the power range is 1–10 W. Under the same power conversion efficiency,
power loss, and thus heat dissipation, increases proportionally as delivered power
increases and exacerbates the problem especially for implantable medical devices
(IMDs). Energy transfer between an inductor and a capacitor could be lossless;
therefore, the ideal efficiency of an inductor-based DC-DC converter could be
unity. In practice, efficiency of an inductor-based DC-DC converter is highly
dependent on the quality factor of the inductor at the frequency of interest. There
are three kinds of losses associated with the power inductor: (1) hysteresis loss due
to the difference of magnetic energy being put into the core during the first
switching phase and that being extracted from the core during the second switching
phase; (2) eddy current loss of the conductive core material and peripherals; and
6.2 DC-DC Converter Comparisons 129

Fig. 6.2 Typical (a) inductor-based DC-DC converter and (b) switched-capacitor DC-DC
converter

(3) conduction loss (ohmic loss, or I2R loss) caused by the series resistance of the
inductor windings. Furthermore, the sizes of high-quality inductors do not shrink as
fast as fabrication processes advance, and hence have limited the employment of
inductor-based DC-DC converters.
On the other hand, due to the charge redistribution loss [5, 6], the efficiency of an
SC DC-DC converter resembles that of a linear regulator, which is equal to the
actual output voltage over the ideal no-load output voltage [7]. For a fully on-chip
implementation, and especially using a bulk CMOS process, losses due to parasitic
capacitors associated with both the top and bottom plates of the flying capacitors
degrade the efficiency severely [6]. Note that the parasitic junction capacitance (for
example, the N-well to P-substrate junction) of a MOS capacitor could be as high as
7%. Nevertheless, for implantable medical devices the advantage of fully on-chip
implementation supersedes the relatively low efficiency, and the SC DC-DC con-
verter is a promising candidate with the other advantages to be discussed next.
Figure 6.3 shows the multiphase/interleaving architectures that are widely
adopted for DC-DC conversion to achieve both input current ripple and output
voltage ripple reduction. The multiphase topology enables the energy to be deliv-
ered to the load in smaller packages, while keeping the switching frequency FS the
same. Consequently, it reduces the ripples without increasing the switching loss.
However, a multiphase inductor-based DC-DC converter needs two or more induc-
tors that are hard to be integrated and occupy large chip and/or printed circuit board
(PCB) area. It is well known that the inductor-based converter has lower I2R loss
when working in the continuous-conduction mode (CCM). However, CCM oper-
ation requires a larger inductor and thus a larger volume. On the contrary, with the
advancement of fabrication processes, the on-chip capacitance density has been
significantly increased. For example, high power density SC DC-DC converters
with good efficiencies have been designed with deep-trench capacitors and/or
silicon-on-insulator (SOI) processes [8, 9]. Even in CMOS processes, losses due
to parasitic capacitors can be much reduced by appropriate topological consider-
ations and circuit techniques [10–12]. In addition, it is easy for an SC converter to
adopt the multiphase architecture with very little power and area overhead [4, 13]
and thus achieves ripple reduction, and at the same time, relaxes the requirement
130 6 DC-DC Converters for WPT

Fig. 6.3 Multiphase (a) inductor-based and (b) SC DC-DC converters

for both the input and output filtering capacitors. Thus, SC converters are preferred
for full on-chip integration in nanometer processes at relatively low power levels
[14, 15].
Fully-integrated power converters with fast transient responses are needed for
miniaturized devices. A switched-capacitor converter can be relatively easier to
achieve faster transient response than its switched-inductor counterpart. Note that
an inductor-based DC-DC converter with voltage-mode control contains an LC
filter that is of second order, and the control loop needs a complicated compensation
scheme (such as a Type III compensator) to maintain system stability while
achieving extended bandwidth. In comparison, the switched-capacitor power
stage (equivalent to a resistor in series with a capacitor) is only of first order, and
pole-zero compensation can be used to extend the bandwidth. Although the power
stage of an inductive DC-DC converter with current-mode control can be consid-
ered as first-order, the change of the output voltage has a 90
phase delayed
compared to the change of the inductor current. The above discussion suggests
that for fully on-chip integration, an SC DC-DC converter is more suitable for
realizing fast transient response as well. Moreover, because the power stage is of
first-order, many design techniques of linear (low dropout, LDO) regulators can be
applied to realize bandwidth extension.

6.3 Control Loop Design

6.3.1 Loop Design for Inductor-Based Converters

The voltage conversion ratio (VCR) of the inductor-based DC-DC converter is

determined by the duty cycle of the controlling switch, and pulse width modulation
6.3 Control Loop Design 131

Fig. 6.4 A typical voltage-mode PWM controlled Buck converter

(PWM) can be used in the control loop. Figure 6.4 shows a typical voltage-mode
controlled buck converter. The output voltage VOUT is compared with the reference
voltage VREF to generate a low-pass filtered voltage VA through the compensator. A
sawtooth waveform ramps up at the beginning of each clock cycle that sets the SR
latch with a fixed switching frequency FS. When the ramp passes above VA, the SR
latch will be reset. The SR latch thus generates the PWM waveform to control the
turning on and off of the switches S1 and S2.
The switching frequency FS of an inductor-based converter does not necessarily
be fixed, and there are control methods with a varying switching frequency such as
the constant on-time, constant off-time, pulse skipping, hysteretic control etc., and
FS of these control methods would vary with the load.
To maximize the loop bandwidth and achieve fast response, a rule-of-thumb
design of the unity-gain frequency (UGF) of the control loop of an inductor-based
DC-DC converter is 1/6 of FS [16], because the linearized small-signal model
becomes inaccurate when the frequencies of interest approach one-half of FS for
a single-phase converter [17].
Studies have confirmed that employing the interleaving topology for the DC-DC
converter can extend the theoretic limit of the control-loop bandwidth, and exam-
ples can be found for multiphase PWM buck converters [18–21] and for multiphase
pulse frequency modulation (PFM) SC converters [22]. As discussed in [19], in a
PWM controller, the compensator output voltage VA is sampled by the PWM
comparator (which compares VA with the ramp signal), and the perturbation of
VA will generate harmonics at the PWM comparator output due to sampling effect.
The low-frequency harmonic components that set limit to the control-loop band-
width can be cancelled by using the multiphase topology. However, the cancelling
effect will be degraded due to phase mismatch, and previous works on multiphase
buck converters only achieved an UGF slightly higher than FS [20], limited by the
132 6 DC-DC Converters for WPT

PWM comparator’s sampling effect [19] and the small number of phases. Consid-
erations for bandwidth extension of multiphase PFM SC converters are introduced
in the following sub-section.

6.3.2 Loop Design for SC DC-DC Converters

For SC DC-DC converters, hysteretic control with single- or multi-boundary is

popular due to its fast response and good stability [3, 23]. However, hysteretic or
any other ripple-based control methods cannot achieve small output ripple as they
need a relatively large output ripple to define the trip points unambiguously.
Figure 6.5 shows a SC converter with voltage-controlled-oscillator (VCO) based
PFM control with a load-dependent switching frequency. It has the advantage of
high efficiency over a wide load range. The error amplifier (EA) compares VOUT
and VREF to tune the VCO frequency through the control voltage VCTL. The
centralized current-starved (CS) VCO with a fixed supply voltage (VLDO) is a
ring VCO formed by cascading many inverter stages that inherently output multiple
interleaving phases for the SC power cells. To reduce the gate drive losses,
low-voltage devices are used to implement the switching components; and they
are powered up by internal low-voltage domains that prevent device breakdown.
Consequently, level-shifters (LSs) are needed to convert the control signals into
different voltage domains, and eventually control the switches of the power cells.
However, the conventional PFM control suffers from slow responses and a load-
dependent noise spectrum [1, 10]. In a conventional SC converter, the dominant
pole of the control loop is located at the VCTL node, and FS is low at light-load
conditions. Thus, the bandwidth is limited and the transient response is slow. To
achieve fast load response, Le et al. [10] proposed a fast loop triggered by an
additional 3.3 GHz clock that bypasses the main integrator loop when the output
voltage is lower than a predefined low limit. However, such a high-frequency clock
may not be available in many low-power applications, such as the wireless sensor
nodes or implantable medical devices. Besides, the reference tracking speed of a
converter that implements dynamic voltage scaling (DVS) depends on the

Fig. 6.5 A typical PFM controlled SC DC-DC converter

6.3 Control Loop Design 133

bandwidth of the main loop, not the large-signal loop. To achieve a high loop
bandwidth and small output ripple, a pseudo-continuous-time loop design method-
ology is introduced next.
As discussed in Chap. 5, there are many benefits of designing the dominant pole
of a voltage regulator at its output node. To satisfy the stability requirement, the
UGF of the internal-pole-dominated case has to be a few decades lower than the
output pole pO. On the other hand, the UGF of the pO-dominated case is of course
higher than pO. Thus, the maximum achievable UGF of the pO-dominated case is
higher than that of the internal-pole-dominated case [24]. Furthermore, with a large
load capacitor at the output node, the output voltage ripple would be smaller. More
importantly, capacitive digital loadings would result in a large load capacitor that
gives a low pO frequency, making the internal-pole-dominated case more difficult
to be compensated without sacrificing loop bandwidth.
As shown in Fig. 6.6, centralized clock phases of the conventional SC converter
are distributed to the power cells that are scattered over the whole chip through a
routing maze, and there could be serious path mismatches that weaken the ripple
cancellation effect. Therefore, for the proposed multiphase SC converter, FS is

Fig. 6.6 A proposed architecture with distributed VDD-controlled oscillator

134 6 DC-DC Converters for WPT

determined by the supply voltage of the VCO (VDDC) which is in turn controlled by
the EA through comparing VOUT with VREF. The VCO consists of many VCO cells
(inverters) that are distributed over the power cells, and the proposed distributed
VDD-controlled oscillator (VDDCO) is driven by an NMOS buffer stage. The
localized clock phases are the outputs of the distributed inverters among the VCO
cells. Note that each current VCO cell is driven by its previous VCO cell, and the
phase differences among the cells are significantly reduced. Hence, more interleav-
ing phases can be used. In addition, when the control signal VDDC changes, the
output frequency of all the phases changes simultaneously that enables a fast
transient response for the PFM control.
Now, the question is: can AC small signals at frequencies higher than FS pass
through the switching power stage, such that the limit is no longer the switching
frequency and achieve an UGF that is much higher?
To answer this question, simulations of time-domain AC responses have been
carried out for the multiphase SC converter as shown in Fig. 6.7. The SC power
stage is a switching stage and the frequencies of interest are close to or higher than

Fig. 6.7 AC simulation of the multiphase SC converter power stage

6.3 Control Loop Design 135

the switching frequency, hence, the averaged model may not be accurate at high
frequencies. Therefore, to verify the validity of the averaged model of the
multiphase SC converter, time-domain AC response simulations are conducted,
such that the transfer functions of the continuous part and the switching part can be
investigated separately, and then be considered together to arrive at the total AC
characteristics [22]. Sinusoidal signals with small amplitudes are applied to the
buffer before the VDDCO, and the frequency of the applied small signal is swept for
computing the frequency response of the power stage. The power stage designed in
[22] is employed in this simulation. As shown from the transient waveforms, at light
load condition, for example, RL ¼ 100 Ω, and FOUT is regulated to around 4 MHz.
The small signal of 40 mVPP at 100 kHz injected at VAC is superimposed on VOUT
with a magnitude of 89 mVPP. At heavy load condition, for example, RL ¼ 10 Ω,
and FOUT is regulated to around 33 MHz. A small signal of 40 mVPP at 150 MHz
was injected at VAC, and was attenuated by the power stage to be 1.67 mVPP and
superimposed on VOUT. Similarly, other frequency points were obtained and com-
piled in the Bode plots (the magnitude plot and the phase plot). Obviously, the SC
power stage with the VDDCO has a low-frequency output pole that changes with the
load. Therefore, the answer to the question above is yes: the small signals at the
frequencies higher than FS can pass through the switching power stage with
multiple interleaving phases.
The VCO here (VDDCO) does not contribute any low-frequency pole to the loop,
unlike it does in a phase-locked loop (PLL), because the small-signal information
here is not the phase but the frequency. Nevertheless, the multiphase SC power
stage can be considered as a phase-integrating block that converts both the phase
and the frequency information into VOUT or IOUT (depending on how it is modeled).
Here, VDDC is a low-impedance node and the associated pole pC is located at high
frequency, while the output pole pO becomes the dominant pole. By using the
multiphase topology, the control loop can respond to external variations at every
fraction of the switching period (T ), such that the discrete-time power stage can be
considered as a pseudo-continuous-time power stage. Also, different from the
previously mentioned PWM case for the inductor-based converter, there is no
sampling process for this multiphase SC converter with PFM control. When
VDDC changes, the frequency (or the inverter delay) of every phase will be changed
simultaneously that ensures pseudo-continuous-time operation. Therefore, the
multiphase SC DC-DC converter ring could achieve an UGF a few times higher
than FS, which has been verified on silicon in [22].
136 6 DC-DC Converters for WPT

6.4 Architectures of DC-DC Conversion

6.4.1 Multiple-Output Converters

Many electronic systems have multiple voltage domains to house different func-
tional blocks, and so does a wireless power transfer system. Different, and some-
time isolated, supply voltages are needed for different functional blocks. For
example, micro-electrodes use >10 V for neural stimulation; contactless memory
uses 15 V for writing and erasing data for flash memory; 3–4 V for battery charging;
sub-1 V for low-power microprocessors, etc. Both inductor-based and switched-
capacitor DC-DC converters can be reconfigured to generate multiple output
voltages by sharing the switches and passive components [25–28]. In particular,
by sharing the inductor or capacitor, considerable chip and PCB area could be
saved, and thus reduces the device size and cost.
For an inductor-based converter, multiple outputs can be realized by simply
delivering the energy stored in the inductor to different outputs in a time-
multiplexing fashion [25, 26]. It may also cooperate with a multi-stage rectifier to
achieve multi-level operation for output ripple reduction as demonstrated in
[26]. To minimize the cross-talk between different outputs, the inductor can be
charged once and be discharged to only one of the outputs one at a time [25, 29]. For
a simpler controller design, assume that fast comparators are available, the inductor
can be charged once and be consecutively discharged to every output one by one
[30]. To increase the output current capability, smaller inductance should be used
such that the inductor current could ramp up faster, or FS should be decreased to
allow a longer charging time for the inductor [29].
For a SC DC-DC converter, the flying capacitors can be reused by different
outputs to realize more VCRs, and consequently to achieve higher system efficien-
cies over a wider input and/or output range [27]. It is also good to dynamically
balance the number of power cells for each outputs according to their load current
requirements, such that FS could be minimized and the efficiency optimized [28].

6.4.2 Layout Strategy for Efficient Power Delivery

The goal of the power distribution system is to deliver the required current across
the chip to the load circuits while maintaining the output voltage level for proper
operation of the loads. A large DC current IDC will introduce IR drop due to the
parasitic routing resistance RP of the VDD network, and the power buses and bond
wires will cause VDD variation due to the parasitic inductor LP during fast load
transients. The overall ΔVDD is approximately equal to IDCRP + LP∙di/dt that will
cause clock jitter, affect logic delay of the load, and reduce the sensitivity of the
analog/RF blocks. Note also that asynchronous circuits are highly dependent on the
sequence of logic signals, and are more sensitive to supply variations than synchro-
nous circuits.
6.4 Architectures of DC-DC Conversion 137

Fig. 6.8 Routing parasitic resistance and inductance of on-chip DC-DC converter(s), supplied
from (a) one side, (b) two sides, and (c) all sides

Obviously, as shown in Fig. 6.8a and Fig. 6.8b, by supplying the load current to
the center from opposite edges could reduce the worst case RP and LP to one fourth
of that of supplying the load current from only one edge of the chip. By using
DC-DC converters in parallel and supplying the load current from all edges RP and
LP could further be reduced, as shown in Fig. 6.8c. However, each DC-DC
converter needs a control block that takes up area and power. In [22], a multiphase
DC-DC converter ring that surrounds the load in the square was implemented. The
load can easily get access to the power supply through any point on the edges of the
chip. Meanwhile, the in-rush current is reduced by the distributed multiphase
configuration and also by using a higher VIN that results in a lower IIN. The
converter ring helps reducing the number of power and ground pads while
maintaining good noise performance for both VDD and Gnd nodes.
In designing a multiphase SC converter, the issue of phase mismatch has to be
addressed through careful layout considerations. For example, if one of the phases
is delayed by Δt, then the delay is passed to all subsequent power cells, and a small
phase mismatch may result in a large output ripple [22, 31]. As shown in Fig. 6.9,
the phase mismatch is modeled as disconnecting the input source from the load for
an interval of Δt. When one power cell is not enabled punctually due to phase
mismatch, the switch SO is turned off for the duration of the additional delay. In
other words, the delay in one phase will lengthen the overall frequency.
Suppose the DC-DC converter is a multiphase SC converter with the power cells
controlled by the distributed ring oscillator. There are two possible architectures for
laying out the power cells, as shown in Fig. 6.10: they can either be distributed or
centralized. When the power cells are distributed, the process and temperature
gradients across the chip and the mismatches in IR drop from the supply to each
delay cell may result in larger phase mismatches and larger voltage ripples.
Meanwhile, the overall switching frequency reflects the averaged process and
temperature variations of the entire chip. In addition, with reduced equivalent
parasitic inductors and resistors, small output voltage ripples may still be expected.
Of course, the selection of the layout architecture depends on system considerations
and requires load and power management co-design.
138 6 DC-DC Converters for WPT

Fig. 6.9 Circuit model of the phase mismatch and the output waveforms of IOUT and VOUT

Fig. 6.10 Two possible architectures for the layout of the multi-phase SC converter

6.4.3 Cascade Voltage Regulators

To drive analog/RF loads, the DC-DC switching converter should be cascaded with
an LDO regulator, as shown in Fig. 6.11a, and using a PMOS LDO regulator is the
common choice. As discussed in the previous chapter, a fully-integrated PMOS
LDO regulator may have slow response due to multiple poles, and it is difficult to
achieve good power supply ripple rejection (PSRR) at high frequency, especially
when the dropout voltage is very low such as 50 mV. Moreover, if the power PMOS
has to keep working in the active (saturation) region it has to be very large that
makes it hard to achieve fast response and good stability.
The alternative is to use an NMOS LDO regulator, and Fig. 6.11b shows one
example that demonstrates a dropout voltage of only 50 mV [2]. In this example, the
input VIN is stepped down to VX through a DC-DC converter and then cascaded by
an LDO regulator to generate the output voltage VOUT. The supply voltage of the
EA that drives the NMOS power transistor MN1 is connected to VIN instead of VX.
Therefore, the supply voltage of the EA is high enough such that the EA output can
6.5 Summary 139

Fig. 6.11 Cascaded voltage regulator stages with (a) PMOS LDO regulator of which the EA gets
power from VX, and (b) the NMOS LDO regulated topology with EA getting power from VIN

drive the gate of MN1 without the need of a step-up charge pump. Note that the
output of the DC-DC converter VX does not need to be tightly regulated, and this is
especially favorable for SC converters. Now, only coarse regulation is needed for the
SC converter stage, and fine regulation is delegated to the LDO regulator. As such,
the SC converter may use digital control with discrete output voltage steps as VX.

6.5 Summary

For wireless power transfer, and especially for the wireless power receiver, whether
using an inductor-based or a switched-capacitor DC-DC converter depends on the
power level, device volume, available technology and cost. In general, inductor-
based converters are more suitable for high-power applications, and SC converters
are more suitable for low-power miniaturized devices. However, the boundary of
the preferred power levels shifts with technology, and SC converters are more
promising for full integration in advanced processes.
DC-DC converters can adopt multiphase/interleaving technique to achieve input
current ripple and output voltage ripple reduction. The output voltage ripple can
further be attenuated by cascading a post-stage LDO regulator for noise sensitive
functional blocks, such as a signal recording amplifier or an analog-to-digital
converter. A major issue associated with the multiphase operation is the phase
140 6 DC-DC Converters for WPT

mismatch problem that has been investigated in this chapter. Careful system-level
layout considerations would definitely be helpful to tackle the noise issue.
Multiphase operation can also extend the theoretical limit of the control bandwidth
of switching converters, and is thus favorable for driving fast transient load such as
the power amplifier of a wireless power transmitter.

References

1. Ramadass YK, Fayed AA, Chandrakasan AP (2010) A fully-integrated switched-capacitor

step-down DC-DC converter with digital capacitance modulation in 45 nm CMOS. IEEE J
Solid State Circuits 45:2557–2565. doi:10.1109/JSSC.2010.2076550
2. Lu Y, Ki W, Yue CP (2016) An NMOS-LDO regulated switched-capacitor DC–DC converter
with fast-response adaptive-phase digital control. IEEE Trans Power Electron 31:1294–1303.
doi:10.1109/TPEL.2015.2420572
3. Van Breussegem TM, Steyaert MSJ (2011) Monolithic capacitive DC-DC converter with
single boundary–multiphase control and voltage domain stacking in 90 nm CMOS. IEEE J
Solid State Circuits 46:1715–1727. doi:10.1109/JSSC.2011.2144350
4. Lu Y, Jiang J, Ki W-H, et al (2015) A 123-phase DC-DC converter-ring with fast-DVS for
microprocessors. In: 2015 IEEE international solidstate circuits conference – (ISSCC), pp
364–365. doi:10.1109/ISSCC.2015.7063077
5. Ki W-H, Su F, Tsui C (2005) Charge redistribution loss consideration in optimal charge pump
design. In: IEEE international symposium on circuits and systems, 2005. ISCAS 2005, vol
2, pp 1895–1898
6. Ki W-H, Lu Y, Su F, Tsui C-Y (2012) Analysis and design strategy of on-chip charge pumps
for micro-power energy harvesting applications. In: VLSI-SoC: advanced research for systems
on chip. Springer, Berlin/Heidelberg, pp 158–186. doi:10.1007/978-3-642-32770-4_10
7. Seeman MD, Sanders SR (2008) Analysis and optimization of switched-capacitor DC–DC
converters. IEEE Trans Power Electron 23:841–851. doi:10.1109/TPEL.2007.915182
8. Le H-P, Sanders SR, Alon E (2011) Design techniques for fully integrated switched-capacitor
DC-DC converters. IEEE J Solid State Circuits 46:2120–2131. doi:10.1109/JSSC.2011.
2159054
9. Andersen TM, Krismer F, Kolar JW, et al (2015) A feedforward controlled on-chip switched-
capacitor voltage regulator delivering 10W in 32nm SOI CMOS. In: 2015 IEEE international
solid-state circuits conference – (ISSCC), pp 362–363
10. Le H-P, Crossley J, Sanders SR, Alon E (2013) A sub-ns response fully integrated battery-
connected switched-capacitor voltage regulator delivering 0.19W/mm at 73% efficiency. In:
2013 IEEE international solid-state circuits conference – (ISSCC), pp 372–373
11. Jiang J, Lu Y, Huang C, et al (2015) A 2/3-phase fully integrated switched-capacitor
DC-DC converter in bulk CMOS for energy-efficient digital circuits with 14% efficiency
improvement. In: 2015 IEEE international solid-state circuits conference – (ISSCC),
pp 366–367. doi:10.1109/ISSCC.2015.7063078
12. Butzen N, Steyaert M (2016) A 94.6%-efficiency fully integrated switched-capacitor DC-DC
converter in baseline 40nm CMOS using scalable parasitic charge redistribution. In: 2016
IEEE international solid-state circuits conference – (ISSCC), pp 220–221
13. Pique GV (2012) A 41-phase switched-capacitor power converter with 3.8mV output ripple
and 81% efficiency in baseline 90nm CMOS. In: 2012 IEEE international solid-state circuits
conference – (ISSCC), pp 98–100
14. Villar-Pique G, Bergveld HJ, Alarcon E (2013) Survey and benchmark of fully integrated
switching power converters: switched-capacitor versus inductive approach. IEEE Trans Power
Electron 28:4156–4167. doi:10.1109/TPEL.2013.2242094
References 141

15. Sanders SR, Alon E, Le H-P et al (2013) The road to fully integrated DC–DC conversion via
the switched-capacitor approach. IEEE Trans Power Electron 28:4146–4155. doi:10.1109/
TPEL.2012.2235084
16. Erickson RW, Dragan M (2001) Fundamentals of power electronics, 2nd edn. Kluwer, Norwell
17. Brown AR, Middlebrook RD (1981) Sampled-data modeling of switching regulators. In: 1981
IEEE power electronics specialists conference, pp 349–369
18. Zhou X, Wong P-L, Xu P et al (2000) Investigation of candidate VRM topologies for future
microprocessors. IEEE Trans Power Electron 15:1172–1182. doi:10.1109/63.892832
19. Qiu Y, Yao K, Meng Y, et al (2004) Control-loop bandwidth limitations for multiphase
interleaving buck converters. In: 2004 IEEE applied power electronics conference and expo-
sition APEC ‘04, vol 2, pp 1322–1328
20. Xiao S, Qiu W, Miller G et al (2008) Adaptive modulation control for multiple-phase voltage
regulators. IEEE Trans Power Electron 23:495–499. doi:10.1109/TPEL.2007.912947
21. Magallanes FC, Aguglia D, Martins C de A, Viarouge P (2012) Review of design solutions for
high performance pulsed power converters. In: Power electronics and motion control confer-
ence (EPE/PEMC), 2012, 15th international, pp DS2b.14-1–DS2b.14-6
22. Lu Y, Jiang J, Ki WH (2017) A multiphase switched-capacitor DC-DC converter ring with fast
transient response and small ripple. IEEE J Solid State Circuits. doi:10.1109/JSSC.2016.
2617315
23. Jiang J, Lu Y, Ki WH (2016) A digitally-controlled 2/3-phase 6-ratio switched- capacitor
DC-DC converter with adaptive ripple reduction and efficiency improvements. In: 2016 42nd
European solid-state circuits conference (ESSCIRC), pp 441–444. doi:10.1109/ESSCIRC.
2016.7598336
24. Lu Y, Wang Y, Pan Q, et al (2015) A fully-integrated low-dropout regulator with full-spectrum
power supply rejection. IEEE Trans Circuits Syst I Regul Pap 62:707–716. doi:10.1109/TCSI.
2014.2380644
25. Ma D, Ki W-H, Tsui C, Mok PKT (2003) Single-inductor multiple-output switching con-
verters with time-multiplexing control in discontinuous conduction mode. IEEE J Solid State
Circuits 38:89–100. doi:10.1109/JSSC.2002.806279
26. Lu Y, Huang M, Cheng L et al (2017) A dual-output wireless power transfer system with active
rectifier and three-level operation. IEEE Trans Power Electron 32:927–930. doi:10.1109/
TPEL.2016.2601623
27. Lu Y, Ki W-H, Yue CP (2012) Input-adaptive dual-output power management unit for energy
harvesting devices. In: 2012 I.E. 55th international midwest symposium on circuits and
systems (MWSCAS), pp 1080–1083. doi:10.1109/MWSCAS.2012.6292211
28. Jiang J, Lu Y, Ki WH, et al (2017) A dual-symmetrical-output switched-capacitor converter
with dynamic power cells and minimized cross regulation for application processors in 28nm
CMOS. In: 2017 IEEE international solid-state circuits conference – (ISSCC), pp 344–345.
doi:10.1109/ISSCC.2017.7870402
29. Jing X, Mok PKT, Lee MC (2011) A wide-load-range constant-charge-auto-hopping control
single-inductor-dual-output boost regulator with minimized cross-regulation. IEEE J Solid
State Circuits 46:2350–2362. doi:10.1109/JSSC.2011.2162188
30. Le H-P, Chae C-S, Lee K-C et al (2007) A single-inductor switching DC–DC converter with
five outputs and ordered power-distributive control. IEEE J Solid State Circuits 42:2706–2714.
doi:10.1109/JSSC.2007.908767
31. Somasekhar D, Srinivasan B, Pandya G et al (2010) Multi-Phase 1 GHz voltage doubler charge
pump in 32 nm logic process. IEEE J Solid State Circuits 45:751–758. doi:10.1109/JSSC.
2010.2042253
Chapter 7
Power Amplifiers for WPT

Abstract Two main choices of the power amplifier (PA) for wireless power
transfer (WPT) are Class-D and Class-E PAs. In this chapter, process selection
and power loss analysis for high efficiency PAs are discussed first, followed by the
discussion on zero-voltage (or zero-current) switching techniques for switching loss
reduction. Operation principles and design considerations of both Class-D and
Class-E PAs are then discussed. Finally, comparisons are made between these
two selections.

Keywords Wireless power transfer • Power amplifier • Class-D • Class-E •

Soft-switching • Zero voltage switching (ZVS) • Zero-current switching (ZCS)

7.1 Introduction

DC-AC converters are commonly known as inverters in the power electronics

industry, and they are used to convert a DC voltage source into an AC voltage
source. Functionally, the non-linear power amplifier (PA) used in analog/RF cir-
cuitry resembles a DC-AC converter. It is used to amplify the power of the digitally
modulated input signal to be sent out by the transmitter.
In signal processing applications such as audio amplification and wireless
communication, signal integrity, signal distortion and harmonics, and signal gain
of PA are the main interests. Whereas in wireless power transfer (WPT) applica-
tions, efficiency and output power level are the major concerns.
The key feature of non-linear PAs (Class-D and Class-E) as compared to linear
PAs (Class-A, Class-AB) is the ideal unity efficiency (ηideal ¼ 100%). As men-
tioned in the previous chapter that discusses DC-DC converters, ideal switches have
either zero turn-on voltage or zero turn-off current, and thus do not consume any
power. High efficiency is especially important for high power designs, as power
loss turns into thermal problem by heating up the system. For example, for a 10 W
integrated PA with an efficiency of 90%, 1 W of power loss is converted into heat
within a millimeter-sized chip area, and a heat sink that is bulky and costly may be
required. If the efficiency drops to 80%, the power loss is doubled, and the size of
the heat sink has to be increased accordingly.

© Springer Nature Singapore Pte Ltd. 2018 143

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_7
144 7 Power Amplifiers for WPT

The most commonly used PAs for WPT are Class-D and Class-E PAs [1–9], and
they will be discussed in Sects. 7.2 and 7.3, respectively. In the following
sub-sections issues related to the PA design and optimization such as integration
processes, power loss components and zero-voltage (or zero-current) switching
techniques will be introduced. Finally, a brief conclusion is drawn in Sect. 7.4.

7.1.1 Integration Processes

Direct bandgap processes using III/V semiconductor materials such as the Gallium
Nitride (GaN) process are popular for high-frequency and high-power applications.
The GaN process has high electron mobility, high saturation velocity and high
breakdown voltage. PAs fabricated using such processes can achieve higher effi-
ciency and therefore higher power density, and can even operate at higher temper-
atures [8, 9]. However, the lack of effective oxide layers forbid III/V processes to
implement sophisticated digital control circuits and large-scale digital signal
processing functions. Therefore, power GaN FETs have to be driven by gate-
drivers and controllers implemented in CMOS technologies.
The rightmost drawing of Fig. 7.1 shows the laterally diffused MOSFET
(LDMOS). It is an asymmetric power transistor designed to have low turn-on resis-
tance and high drain-to-source and drain-to-gate breakdown voltages. It only needs a
small VGS (5 V for example) to turn on, while sustaining very high VDS and VGD (100 V
for example). The low doping around the drain terminal results in a diffused depletion
layer, labeled as the N drain extension that can bear a high breakdown voltage. Due
to the short effective channel length, small on-resistance can be obtained as well.
Most of the integrated power amplifiers are implemented using the bulk BCD
process [10] that contains bipolar junction transistors, CMOS and LDMOS transis-
tors. Bipolar transistors are employed for their high speed and high gain, while
CMOS transistors offer high input resistance and low standby power. To increase
the output power, either the supply voltage or the output current or both should be
increased. To deliver a large current a large transistor is needed; but then it will
have large parasitic capacitors at the gate and at the output terminal that result in
slow response and large switching loss. To reduce I2R loss and to attain high
efficiency, the PA usually works with a relatively high supply voltage. In addition,
to improve the robustness of the integrated power circuits, isolation techniques such
as deep-trench isolation (DTI) and silicon-on-insulator (SOI) can be employed, to
prevent supply noise and ground noise from coupling among different voltage
domains, and to prevent the latch-up problem caused by large in-rush current.

7.1.2 Losses in Switching PAs

Although the theoretical efficiency of a non-linear PA is 100%, in practice, high

efficiency is hampered by losses, and the analysis of loss components becomes
7.1 Introduction 145

Fig. 7.1 Diagram of combined bipolar, CMOS, and DMOS devices in a BCD process

more important at higher frequencies [11]. Four kinds of loss can be identified and
are discussed below.

7.1.2.1 Conduction Loss

The conduction loss, or I2R loss, is the resistive loss caused by parasitic resistors
associated with the power transistors, resonant inductors and capacitors. In addi-
tion, the skin effect, which is the phenomenon that high-frequency AC current only
conducts near the surface of the conductor and increases the effective resistance at
high frequencies, adds to the loss of all conductors, especially for inductors, coils
and interconnects.
To reduce conduction loss of interconnects surface mount devices with very low
loss at the frequency of interest should be selected. For the bonding pads that
conduct large current at high frequencies, multiple parallel bond-wires should be
used. Moreover, wide, flat and short connections on chip and circuit board are
highly recommended.

7.1.2.2 Turn-On Switching Loss

Figure 7.2 shows an MOS transistor and its model as an ideal switch with a parasitic
on-resistor, a parallel body-to-drain diode and a parasitic junction capacitor CD.
Every time the switch is turned on, CD is discharged to zero with a switching energy
loss of 0.5  CDVDS2, and the switching power loss is thus 0.5  CDVDS2fs, where fs
is the switching frequency. In a push-pull type PA such as the Class-D PA, there are
146 7 Power Amplifiers for WPT

Fig. 7.2 A simple model of

an NMOS transistor with
parasitics

two junction capacitors at the output node, and there are two switching events in
one period. Hence, the switching loss is a few times higher than a single-switch
topology.

7.1.2.3 Turn-Off Switching Loss

During the switch turn-off process, the capacitor CD will be charged up by the
power inductor in the PA. At the same time, there is current flowing in the parasitic
inductors such as bond-wires and metal traces on the chip and on the board, lumped
as LP, and the amount of energy stored in LP is 0.5  LPI2OFF, where IOFF is the
current flowing at the start of the turn-off process. The power loss is proportional to
the switching frequency.
Parasitic capacitors are by-products of the devices and are proportional to their
sizes that are set by power requirements. Thus, the designer may not have much
control. However, inductive power losses can be much reduced by a good circuit
layout and PCB layout, and by using an advanced packaging technology.

7.1.2.4 Gate-Drive Loss

Power MOS transistors, due to their large sizes set by power requirement, have
large gate capacitances that have to be driven by buffers. The switching power loss
of the gate capacitance Cg is CgVDD2fS. Buffers built from cascading inverters with
increasing sizes result in large shoot-through current (also known as short circuit
current), especially for the later stages. Therefore, non-overlapping logic is also
needed for the buffers, as least for the last stage of the buffer.
Power consumption of the controller may be considered as part of the driver’s
loss. More sophisticated control method can be employed for higher power devices,
because larger power budget is available. For a portable application with an output
power of 100 mW, designing the controller to consume 1 mW (1% of the output
power) is a reasonable starting point. This 1% consumption may be decreased for a
larger output power.
7.2 Class-D PA 147

7.1.3 Zero Voltage (Current) Switching

As discussed in previous chapters, increasing the switching frequency of power

converters can reduce the sizes of capacitors and circuit magnetic, leading to
smaller volume and lower cost. However, increasing switching frequency also
increases switching loss and thus reduces efficiency. Instead of hard switching,
for high-power applications techniques of resonant converters that achieve soft
switching have been studied for DC-AC inverters, DC-DC converters, and WPT
systems [12–17]. Those techniques make use of resonance of inductor and capacitor
to modulate either the voltage or the current waveform across the power switch, so
as to achieve either zero-voltage switching (ZVS) or zero-current switching (ZCS)
that can reduce the switching loss. As shown in Fig. 7.3, during hard switching, the
voltage across and the current through the power transistor are non-zero for the
turn-on and/or turn-off transitions. By inciting resonance, either the voltage or the
current will be a sinusoidal wave with reduced overlapping. Therefore, switching
loss during the turn-on/off transitions can be much reduced.
As discussed in the loss analysis, every time the switch is turned on the voltage
across the parasitic capacitor is discharged to zero with a switching loss of
0.5  CDVDS2. In the case of ZCS, the MOS transistor has to turn on with a high
drain-to-source voltage VDS, and there will be unfavorable switching loss. Conse-
quently, ZCS is not exactly suitable for MOS transistors.
On the other hand, with ZVS the parasitic capacitor discharges its charge and
stores it in the resonant inductor, and hence the depletion of charge is not consid-
ered as switching loss. After the parasitic capacitor is discharged, the MOS power
switch can then be turned on by the gate-drive buffer. Conversely, when the switch
is conducting current, it can easily be turned off by the gate signal, and the turn-off
losses would not be large. Hence, ZVS is very suitable for MOS transistors, and
turning on MOS transistors with a high VDS should be avoided.

7.2 Class-D PA

Figure 7.4 shows a non-linear Class-D push-pull type of power amplifier

[18]. CMOS implementation of the power stage of the Class-D PA consists of
non-overlapping logic, gate-drive buffer and two power switches. Depending on the
choice of process, the two power switches could be a CMOS transistor-pair, or both
are N-type LDMOS transistors. The operation of the Class-D PA is similar to that of
a buck DC-DC converter. The difference is that the Class-D PA controls the output
voltage pulses according to the varying input signal, while the buck converter takes
a constant input signal (the reference voltage) and delivers a constant output
voltage.
The Class-D PA is traditionally used for audio signal amplification [19], as
shown in Fig. 7.4a. The input impedance of a loudspeaker is mainly resistive over
148 7 Power Amplifiers for WPT

Fig. 7.3 Voltage and current waveforms of hard switching and soft switching scenarios

Fig. 7.4 A Class-D type power amplifier driving (a) loudspeaker, (b) piezoelectric transducer,
and (c) wireless power transfer link or resonant DC-DC converter

the frequency range of interest, and the output power of the loudspeaker is specified
by nominal impedance such as 8 Ω for Hi-Fi loudspeakers and 32 Ω for head-
phones, for example.
Figure 7.4b shows the driver of a piezoelectric transducer that finds applications
in sound generation and actuation. The piezoelectric transducer can be electrically
modeled as a capacitive load that requires a high voltage to drive [20], and high-
efficiency Class-D designs have been demonstrated with relatively high peak-to-
average ratio signals [21].
When driving the load for a WPT link or a resonant DC-DC converter, as shown
in Fig. 7.4c, a transformer may be involved. The load along with the resonant tank
on the secondary side can be modeled as an equivalent load impedance ZL,EQ
reflected back to the primary side (with residual inductive or capacitive component)
that will affect the resonant frequency fR of the primary LC tank. It will be difficult
to match the switching frequency fS of the Class-D PA with fR exactly in real
implementations. Refer to Chap. 3 for more detail discussion.
7.2 Class-D PA 149

7.2.1 Operation Conditions

The conceptual voltage and current waveforms of the CMOS Class-D PA driving a
resonant load are shown in Fig. 7.5. There are three operation cases. Case 1: the
equivalent load seen at the PA output is purely resistive, and hence, fS ¼ fR. Case 2:
the secondary circuit presents a capacitive load with fS < fR, and the PA output
current IO leads the voltage signal VX. Case 3: the secondary circuit presents an
inductive load with fS > fR, and the PA output current IO lags behind the voltage
signal VX.
Assume the transistors are ideal and no dead-time is introduced to the power
stage, the node voltage VX is then a square wave with 50% duty ratio. Thus, VX has
a fundamental sinusoidal component at fS with odd harmonics. The series-resonant
LC tank should have a high loaded quality factor QL, and acts like a band-pass filter
attenuating the high-order components. Therefore, IO that flows through the reso-
nant tank can be considered as almost sinusoidal. In Case 1 with fS ¼ fR, the positive
half of IO is sourced from MP and the negative half of IO is provided by MN. Both
ZCS and ZVS are realized in this case. With small dead-times for the on and off
intervals of the power switches, shoot-through current can be eliminated, and high
efficiency can be achieved.
However, when the load and/or coupling conditions change, the operating point
will deviate from the ideal case (Case 1). Extra considerations are needed for Case
2 and Case 3, and are discussed as follows with the help of Fig. 7.6.
When fS < fR, the resonant load appears capacitive and IO leads ahead of the
voltage signal VX. Therefore, IMP goes negative across the zero point before MP is
switched off that defeats zero current switching (ZCS), which is originally sched-
uled for soft turn-off. Before MN is turned on, IO will keep flowing even MP is
already turned off. As a result, IO finds its way through the parasitic diode DP as
indicated (by the shaded area) in the figure. Next, MN is turned on with a non-zero
current and a high VDS (approximately equal to VDD) that is essentially a hard turn-
on. The parasitic capacitors at VX are discharged that results in a large peak current
and thus severe switching loss. In a similar fashion, in the next half cycle, MN will
undergo a soft turn-off and MP a hard turn-on.
When fS > fR, the resonant load appears inductive and IO lags behind VX. After
MP is turned off with a non-zero current, and hence a hard turn-off, IO will firstly
discharge the parasitic capacitors at the node VX, and will keep conducting through
the parasitic diode DN with VX ¼ VD, where VD is the diode forward voltage drop.
The conduction loss in this short dead-time duration is relatively large because of
the large diode voltage drop. Next, after a small dead-time, MN is turned on with a
low VDS. This can be considered as zero-voltage switching (ZVS) that resembles a
soft turn-on with essentially no shoot-through current. Therefore, the switching loss
is much reduced. In a similar fashion, in the next half cycle, MN will undergo a hard
turn-off and MP a soft turn-on. As explained in the previous section, an MOS
transistor has no problem in turning off its current, and thus ZVS is preferred.
150 7 Power Amplifiers for WPT

Fig. 7.5 The voltage and current waveforms of a Class-D PA in a resonant WPT system, with
fS ¼ fR (resistive equivalent load); fS < fR (capacitive equivalent load); fS > fR (inductive
equivalent load)
7.2 Class-D PA 151

Fig. 7.6 The voltage and current waveforms of the power transistors in Class-D PA with soft
switching considerations

The shaded areas in Fig. 7.6 represent the tolerances (acceptable dead-time
margins) of the dead-time between the two power switches [22]. Setting the
dead-time within the margin can guarantee a continuous IO without staying at
zero for a short duration. Conversely, the maximum allowed dead-time increases
as fS deviates more from fR, because the time interval during which the switch
current is negative becomes longer. When fS ¼ fR, the shortest dead-time is
required.
When the Class-D PA is driving an inductive load, larger parasitic capacitance is
allowed at the node VX, because the energy of the parasitic capacitors is simply
transferred to the resonant tank without loss. A conventional Class-D PA generates
electromagnetic interference (EMI) due to switching noise and high-frequency
ringing at the switching nodes, but one may intentionally add a capacitor between
VX and ground to smooth out the switching at VX [23]. In so doing, the VX
waveform is smoothen and contains a smaller amount of harmonics than the square
wave of a conventional Class-D PA. Consequently, EMI and noise level are
reduced. However, a longer switch dead-time is needed to guarantee that ZVS is
realized, and the maximum output power will thus be reduced.
152 7 Power Amplifiers for WPT

7.2.2 ZVS Class-D PA

As mentioned above, the conventional Class-D PA incurs high losses due to the
parasitic capacitances at the VX node, and therefore must be operating at fS > fR
with the load tuned to be slightly inductive. However, such an operating point of
shifting away from the resonant frequency will increase the circulating energy
between the coil and the PA, and consequently reduces the transmission efficiency.
Figure 7.7 shows a variation of the conventional Class-D PA with additional
ZVS inductor LZVS and capacitor CZVS for the WPT system by EPC Corporation
using enhancement-mode GaN devices [8, 9]. In this configuration, the ZVS tank
circuit does not operate at resonance, but rather as a no-load buck converter. Let us
refer to Fig. 7.7b. The peak of IZVS occurs at the ZVS point of VX ¼ 0, and it
provides the necessary charging/discharging current for the VX node. The value of
LZVS depends on the supply voltage VDD, parasitic capacitance at the VX node, the
slew rate at VX and the immunity margin for shifts in the load impedance.
This scheme has two main drawbacks. The first is the extra cost brought by the
bulky additional ZVS inductor and capacitor, making it not suitable for miniature
applications. The second is that IZVS introduces extra conduction loss through the
power transistors, limiting the light-load efficiency and the maximum output
capability.

Fig. 7.7 (a) A ZVS variation to the conventional Class-D PA, and (b) its voltage and current
waveforms
7.3 Class-E PA 153

7.3 Class-E PA

The high-efficiency Class-E PA was invented by N. O. Sokal (the father) and A. D.

Sokal (the son) in 1975 [12]. Figure 7.8a shows a simple diagram of the Class-E PA,
and Fig. 7.8b shows the conceptual voltage and current waveforms operating in the
steady-state. The Class-E PA of a WPT transmitter consists of a single switch MN,
an RF choke LC, a shunt capacitor CP, and an LC series resonant tank that contains
CS and the coupling coils L1 and L2. The inductance value of LC is usually set to be
sufficiently high such that its AC current is small compared to the DC current, but
that is not a must for the design [24]. The parasitic junction capacitor of MN is now
part of CP. The load network CP, CS and L1 is a combined series-parallel resonant
circuit, which is also known as a multi-frequency network.
The Class-E operation principle discussed in [12] covers a variety of circuit
topologies that contain a switch and a load network, as long as they satisfy all three
specific objectives for the collector voltage (drain voltage for MOSFET) and
current waveforms: (1) the rise of the voltage across the transistor at turn-off should
be delayed until after the transistor is off; (2) the drain voltage should go back to
zero when the transistor starts to turn on; and (3) the slope of the drain voltage
should be zero when the transistor starts to turn on. Therefore, the Class-E PA can
achieve high power-conversion efficiency at high frequencies. In the past four
decades, it finds various high-power and/or high-efficiency applications in

Fig. 7.8 (a) A simple diagram of Class-E PA in a resonant WPT system, and (b) the voltage and
current waveforms in the steady-state
154 7 Power Amplifiers for WPT

communication transceivers, electronic ballasts for fluorescent lighting, heat induc-

tion, electrosurgical generator and wireless power transfer systems [17, 25–27].
When the PA is driving a series-resonant tank, as in the conventional Class-D
case, increasing the coil current by simply lowering the equivalent series resistances
(ESRs) would require significant reduction of the switch on-resistance and the coil
parasitic resistance. Therefore, large transistors should be used, which would
increase the gate drive loss and add stray capacitance to the VX node.
When the PA is driving a parallel-resonant tank, the reactances cancel each other
at resonance. The large AC current required in the primary coil for large magnetic
field is mainly provided by the resonant capacitor in parallel, which relaxes the
current handling capability of the active device(s). However, the parallel-resonant
tank induces high voltage stress to the driver device(s), and high-voltage devices
such as LDMOS should be used, but such devices would occupy large area and may
degrade the high-frequency performance.
To deal with the above cases, a compromised solution is to use a combined
series-parallel resonant tank, which has been employed in the Class-E configura-
tion. In this case, the active device deals with both low current and low voltage
while delivering a large coil current. The impedance curve of the multi-frequency
load network is plotted in Fig. 7.9. The lower peak of the frequency response is
caused by the series resonance of L1 and CS. As the frequency increases, the
reactance of the series-resonant tank increases, and with CP, forms the parallel
resonance frequency peak. The Class-E point is just located between the series
resonance and parallel resonance frequency peaks, at where the power loss of the
driver is minimized [1]. In this case, the voltage and current waveforms are 180 out
of phase. For a set of component values of CP, CS and L1, the Class-E frequency
point depends on the Q of the load network, while the minimum-loss operation
occurs at a critical Q.
The design parameters of a Class-E PA are correlated, and therefore a priori
determination of the exact Class-E point (the critical Q) is difficult [1]. When the Q
of the load network is too high, the ringing of the switching voltage VX is under-
damped, which would cause VX to swing well below ground and turns on the
parasitic diode of MN, causing more conduction loss. If the Q is too low, the ringing

Fig. 7.9 Impedance of the

load network of the Class-E
PA
7.4 Summary and Discussion 155

of VX is over-damped, and VX may not return to zero voltage fast enough and results
in unfavorable non-zero voltage switching that introduces extra switching loss.
The above two cases can be referred as sub-optimum Class-E operation [14], and
a critical Q is required for the minimum-loss operation. However, the required
condition is sensitive to frequency and component variations, and may require a
closed-loop tracking compensation scheme [1, 2]. Effects of parameter variations,
including load impedance variation, shunt reactance variation, frequency variation
and the duty cycle variation were discussed in [24, 28]. It is also suggested that
modulating the Class-E PA output power with pulse-width modulation (PWM)
would degrade the efficiency but would not be excessive. In addition, the load
resistance and the supply voltage VDD are related by the requirement of delivering a
specified output power to the load from VDD [12]. Therefore, the output power can
be tuned by modulating the supply voltage of the Class-E PA.

7.4 Summary and Discussion

This chapter discussed two popular types of DC-AC converters, known as power
amplifiers in the context of WPT transmitters, which are the Class-D and Class-E
amplifiers. Some essential knowledge on integration processes, power loss compo-
nents, as well as soft switching mechanisms are introduced.
Both Class-D and Class-E PAs have an ideal efficiency of 100%, but in practice,
Class-E PAs can be more efficient than Class-D PAs. Class-D PAs suffer from the
possibility of turning on and off both high-side and low-side transistors simulta-
neously, leading to efficiency loss at high frequencies; and the gate-drive circuits have
to have long enough dead-times. Long dead-times run the risk of turning on the
parasitic diodes that introduce additional conduction loss. A CMOS Class-D PA
should operate at fS > fR, that is, it should drive an inductive load to achieve zero-
voltage switching that reduces switching loss and EMI. To achieve high efficiency, a
Class-D PA should work with a duty ratio of 50%, while this is not necessary for a
Class-E PA. The Class-E PA can be designed to drive a combined series-parallel
resonant load network. The single power switch only needs to provide part of the total
resonant current and thus results in lower conduction loss. Moreover, the Class-E
switching condition ensures zero-voltage switching at zero voltage-slope and reduces
the switching loss to zero during the turn-on transition.
The output power capability of Class-D and Class-E PAs was analyzed in [14],
and the calculation method has been used in [29] for the Class-DE PA. Their output
power capabilities PMAX have been normalized to the product of the peak current
stress IP and the peak voltage stress VP imposed on the switches as given below:

POUT
PMAX ¼ ð7:1Þ
V P IP
156 7 Power Amplifiers for WPT

For Class-D and Class DE PAs, the peak voltage is VDD only, while the peak
voltage for Class-E PAs is 3.56VDD [14]. Therefore, the normalized output power
capability of the Class-D PA is higher than that of the Class-E PA, which may limit
the application of the Class-E PA in high-power applications such as fast wireless
charging systems.
Employing the Class-E PA for WPT requires detailed knowledge of the coupling
coils and how the load would affect the impedance seen by the PA. The design is
further complicated by coupling-variation between the coils and power-variation
due to the changing load. A dedicated closed-loop control for the Class-E PA is
needed to achieve high efficiency over component variations and a wide range of
conditions. Therefore, the Class-D PA may still be a more robust selection for WPT
systems.

References

1. Troyk PR, Schwan MAK (1992) Closed-loop class E transcutaneous power and data link for
microImplants. IEEE Trans Biomed Eng 39:589–599. doi:10.1109/10.141197
2. Kendir G, Liu W, Wang G et al (2005) An optimal design methodology for inductive power
link with class-E amplifier. IEEE Trans Circuits Syst I Regul Pap 52:857–866. doi:10.1109/
TCSI.2005.846208
3. Tomita K, Shinoda R, Kuroda T, Ishikuro H (2012) 1-W 3.3–16.3-V boosting wireless power
transfer circuits with vector summing power controller. IEEE J Solid State Circuits
47:2576–2585. doi:10.1109/JSSC.2012.2211698
4. Choi J-H, Yeo S-K, Park S, Lee J-S, Cho G-H (2013) Resonant regulating rectifiers
(3R) operating for 6.78 MHz resonant wireless power transfer (RWPT). IEEE J Solid State
Circuits 48:2989–3001. doi:10.1109/JSSC.2013.2287592
5. Li X, Lu Y, Tsui C-Y, Ki W-H (2014) An adaptive wireless powering and data telemetry
system for optic nerve stimulation. In: 2014 IEEE international symposium on circuits and
systems (ISCAS), pp 1404–1407. doi:10.1109/ISCAS.2014.6865407
6. Li X, Meng X, Tsui C-Y, Ki W-H (2016) Reconfigurable resonant regulating rectifier with
primary equalization for extended coupling- and loading-range in bio-implant wireless power
transfer. IEEE Trans Biomed Circuits Syst:1–1. doi:10.1109/TBCAS.2015.2503418
7. Kosuge A, Hashiba J, Kawajiri T et al (2016) An inductively powered wireless solid-state
drive system with merged error correction of high-speed wireless data links and NAND flash
memories. IEEE J Solid State Circuits 51:1041–1050. doi:10.1109/JSSC.2015.2512959
8. Lidow A, de Rooij M (2014, May) Performance evaluation of enhancement-mode GaN
transistors in Class-D and Class-E wireless power transfer systems. Bodo Magaz: 56–60
9. de Rooij MA (2015) The ZVS voltage-mode class-D amplifier, an eGaN® FET-enabled
topology for highly resonant wireless energy transfer. In: 2015 IEEE applied power electronics
conference and exposition (APEC), pp 1608–1613
10. Rose M, Bergveld HJ (2016) Integration trends in monolithic power ICs: application and
technology challenges. IEEE J Solid-State Circuits:1–10. doi:10.1109/JSSC.2016.2566612
11. El-Hamamsy S-A (1994) Design of high-efficiency RF Class-D power amplifier. IEEE Trans
Power Electron 9:297–308. doi:10.1109/63.311263
12. Sokal NO, Sokal A (1975) Class E-A new class of high-efficiency tuned single-ended
switching power amplifiers. IEEE J Solid State Circuits 10:168–176. doi:10.1109/JSSC.
1975.1050582
References 157

13. Sokal NO (1981) Class E high-efficiency switching-mode tuned power amplifier with only one
inductor and one capacitor in load network-approximate analysis. IEEE J Solid State Circuits
16:380–384. doi:10.1109/JSSC.1981.1051605
14. Raab FH (1977) Idealized operation of the class E tuned power amplifier. IEEE Trans Circuits
Syst 24:725–735. doi:10.1109/TCS.1977.1084296
15. Redl R, Molnar B, Sokal NO (1986) Class E resonant regulated DC/DC power converters:
analysis of operations, and experimental results at 1.5 MHz. IEEE Trans Power Electron PE
1:111–120. doi:10.1109/TPEL.1986.4766289
16. Liu KH, Lee FCY (1990) Zero-voltage switching technique in DC/DC converters. IEEE Trans
Power Electron 5:293–304. doi:10.1109/63.56520
17. Erickson RW, Dragan M (2001) Fundamentals of power electronics, 2nd edn. Norwell, Kluwer
18. Baxandall PJ (1959) Transistor sine-wave LC oscillators. Some general considerations and
new developments. Proc IEE Part B Electron Commun Eng 106:748–758. doi:10.1049/pi-b-2.
1959.0141
19. Berkhout M (2003) An integrated 200-W class-D audio amplifier. IEEE J Solid State Circuits
38:1198–1206. doi:10.1109/JSSC.2003.813238
20. Ma H, van der Zee R, Nauta B (2015) A high-voltage Class-D power amplifier with switching
frequency regulation for improved high-efficiency output power range. IEEE J Solid State
Circuits 50:1451–1462. doi:10.1109/JSSC.2015.2421994
21. Amir S, van der Zee R, Nauta B (2015) An improved modeling and analysis technique for peak
current-mode control-based boost converters. IEEE Trans Power Electron 30:5309–5317.
doi:10.1109/TPEL.2014.2368176
22. Kazimierczuk MK (1991) Class D voltage-switching MOSFET power amplifier. IEE Proc B
Electr Power Appl 138:285–296. doi:10.1049/ip-b.1991.0035
23. Kazimierczuk MK, Szaraniev W (1992) Class-D zero-voltage-switching inverter with only
one shunt capacitor. IEE Proc B Elect Power Appl 139:449–456. doi:10.1049/ip-b.1992.0055
24. Kazimierczuk M, Puczko K (1987) Exact analysis of class E tuned power amplifier at any Q
and switch duty cycle. IEEE Trans Circuits Syst 34:149–159. doi:10.1109/TCS.1987.1086114
25. Tsai K-C, Gray PR (1999) A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless
communications. IEEE J Solid State Circuits 34:962–970. doi:10.1109/4.772411
26. Wang G, Liu W, Sivaprakasam M, Kendir G (2005) Design and analysis of an adaptive
transcutaneous power telemetry for biomedical implants. IEEE Trans Circuits Syst I Regul
Pap 52:2109–2117. doi:10.1109/TCSI.2005.852923
27. Low ZN, Chinga R, Tseng R, Lin J (2009) Design and test of a high-power high-efficiency
loosely coupled planar wireless power transfer system. IEEE Trans Ind Electron
56:1801–1812. doi:10.1109/TIE.2008.2010110
28. Raab FH (1978) Effects of circuit variations on the class E tuned power amplifier. IEEE J Solid
State Circuits 13:239–247. doi:10.1109/JSSC.1978.1051026
29. Koizumi H, Suetsugu T, Fujii M et al (1996) Class DE high-efficiency tuned power amplifier.
IEEE Trans Circuits Syst I Fundam Theory Appl 43:51–60. doi:10.1109/81.481461
Chapter 8
Conclusions and Future Works

Abstract In this chapter, we summarize the contents of the book and make a few
remarks on the design perspectives of each building block of the wireless power
transfer system. Potential research and development directions are suggested for the
consideration of research students and engineers who are working on or going to
work on this promising area.

Keywords Wireless power transfer • Inductive coupling • Wireless charging •

DC-DC converter • Voltage regulator • Power management IC

8.1 Concluding Remarks of the Book

Wireless power transfer (WPT) for a broad range of applications is projected to

have an exponential growth in demand, with an enormous number of new devices
and products to be enabled by this powerful technology. A WPT system involves
almost all kinds of power converters such as AC-DC, DC-AC and DC-DC con-
verters, and a circuit designer should have deep understandings of the fundamentals
and operation principles of each type of power converters. To design an efficient
wireless power transfer system, an engineer needs to know both power processing
and signal processing, and also coil design. These requirements impose technical
challenges to both the circuit and the system designers.
In this book, we started in Chap. 1 with the motivations and background of
wireless power transfer. Then, in Chap. 2, we reviewed the system architectures for
WPT receivers, and focused on output voltage regulation and passive component
reduction. We also analyzed the characteristics of inductive coil coupling in
Chap. 3. Subsequently, we discussed the CMOS integrated-circuit design that
focused on low-power wireless power transfer systems in Chaps. 4, 5, 6 and 7.
Design examples were studied in details in individual chapters, and are summarized
as follows.
In Chap. 2, a three-level single-inductor dual-output DC-DC converter in coop-
eration with an active voltage doubler was designed for a wireless power receiver of
which the load needs multiple step-up/ down supply rails. Small output voltage
ripples were obtained at all output voltages, while small size passive components

© Springer Nature Singapore Pte Ltd. 2018 159

Y. Lu, W.-H. Ki, CMOS Integrated Circuit Design for Wireless Power Transfer,
Analog Circuits and Signal Processing, DOI 10.1007/978-981-10-2615-7_8
160 8 Conclusions and Future Works

could be used due to high switching frequency and discontinuous-current mode

operation.
A couple of active rectifiers for near-field WPT receivers were designed and
analyzed in Chap. 4. Reverse current control schemes were reviewed and summa-
rized, while a competent and advantageous scheme with additional analog auto-
adjust loops for active rectifiers was introduced. Delay-locked-loop (DLL) based
active rectifiers, which were found to be more suitable for the series-resonant
receiving tank and/or high WPT frequency cases, were studied as well.
Chapters 5 and 6 introduced linear regulator and switching converter designs,
respectively. Two fully-integrated low-dropout regulators with full-spectrum
power supply ripple rejection were designed for suppressing high-frequency supply
ripples at the WPT frequency and its harmonics. Circuit and architectural tech-
niques for fast transient response and small output ripples were discussed as well.
Chapter 7 compared the Class-D and Class-E power amplifiers (PAs) for wire-
less power transmitters. It is suggested that the knowledge on power electronics and
especially on resonant converters can be very helpful for optimizing the PA
efficiency.

8.2 Suggested Future Works

The following research directions are of interest to the authors of this book.
Device-to-device wireless power transfer is an emerging direction for
consumer electronics and internet-of-things, and is creating a new eco-system for
wireless charging [1]. For wireless power transfer among devices (for example,
mobile phones), both source energy and output power level are limited, and
therefore, the battery-to-battery power transfer efficiency is one of the key
specifications.
Ultrasound WPT could be a good alternative to electromagnetic (EM) wave
WPT for implantable medical devices [2]. It is known that the propagation loss in
water of acoustic waves is much lower than that of the EM waves, and it is
relatively safe for the tissue to absorb ultrasound energy at higher power density
[3]. Meanwhile, the relatively low operation frequency compared to the EM waves
would result in higher conversion efficiency for the power converters.
Wireless charging technology using the Wi-Fi frequency bands (2.45 or
5.8 GHz) for longer WPT distance (up to the 10-m range) and for better spatial
freedom [4] is attractive especially for in-office and in-car power transmission. To
increase the received power, a complex antenna phased array could be designed to
precisely send power to the device-under-charging with multiple energy beams.
We hope the readers enjoy reading this book, and continue or start their research
in this interesting and promising area.
References 161

References

1. Huang M, Lu Y, et al (2017) A reconfigurable bidirectional wireless power transceiver with

maximum current charging mode and 58.6% battery-to-battery efficiency. In: 2017 IEEE
international solid- state circuits conference – (ISSCC), pp 376–377. doi:10.1109/ISSCC.
2017.7870418
2. Meng M, Kiani M (2016) Design and optimization of ultrasonic wireless power transmission
links for millimeter-sized biomedical implants. IEEE Transac Biomed Circuits Syst:1–10.
doi:10.1109/TBCAS.2016.2583783
3. van Schuylenbergh K, Puers R (2009) Inductive powering. Springer, Dordrecht
4. Branscombe M (2013) Wireless power: could Cota make it long-distance and mainstream?
http://www.qiwireless.com/wireless-power-cota-make-long-distance-mainstream. Accessed
19 Oct 2016