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Assignment 2

1. This document provides instructions for Assignment 2 on analog and digital VLSI design. Students are asked to draw the layout of a CMOS inverter in Electric CAD tool using specified transistor width-to-length ratios based on their student ID number. 2. Students then need to verify the layout through design rule checks, layout versus schematic checks, and electrical rule checks. 3. The completed Electric library file and a PDF image of the layout must be submitted in a ZIP file named according to the specified format.

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EDWIN DOMINIC
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62 views

Assignment 2

1. This document provides instructions for Assignment 2 on analog and digital VLSI design. Students are asked to draw the layout of a CMOS inverter in Electric CAD tool using specified transistor width-to-length ratios based on their student ID number. 2. Students then need to verify the layout through design rule checks, layout versus schematic checks, and electrical rule checks. 3. The completed Electric library file and a PDF image of the layout must be submitted in a ZIP file named according to the specified format.

Uploaded by

EDWIN DOMINIC
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE - PILANI, HYDERABAD CAMPUS

First Semester 2015-2016


Assignment 2
Analog and Digital VLSI Design

Assignment Due Date: 29th October 2015 11:59 PM Max Marks: 15M
Tools and files you need:

• Java
• Electric CAD tool “jar” file
• LTSPICE “scad.exe” file
• Technology ‘model’ file
Before starting the assignment, refer to the following link for better understanding on how to draw layout in
Electric tool.
http://www.cmosedu.com/videos/electric/Electric_video_3/Electric_video_3.wmv
Perform the following:
The W of the transistors should be in the following pattern with respect to your ID number.
If ID number: 20XXXXXXX23H, then Wp = 2*L and Wn =3*L
If your ID number contains ‘0’ in the last two digits then consider ‘0’ as ‘10’. For example, If ID number:
20XXXXXXX03H, then Wp = 10*L and Wn = 3*L. If ID number: 20XXXXXXX30H, then Wp = 3*L and Wn =
10*L
If the last two digits of your ID number are same, then consider Wp = 10*L and Wn as your last digit. For
example, If ID number: 20XXXXXXX55H, then Wp = 10*L and Wn = 5*L
1. Draw the layout for CMOS inverter in Electric CAD tool with the above W/L ratios of MOS transistors.
2. Verify the layout with Design rule checks (DRC).
3. In the assignment 1, schematic of CMOS inverter was designed in Electric with the above W/L ratios. Use that
schematic for layout verses schematic (LVS) checks. (In Electric LVS is under tools->NCC menu)
4. Verify the layout for ERC well checks.
Your design must pass all checks without any error.
Submission Procedure:
 Upload the “.zip” file containing Electric design library file “.jelib” of this assignment and a PDF(name it as
IDNO_NAME.pdf) file containing image of layout.
 The ZIP file name should be in the format “IDNO_NAME.zip”. Don’t place any passwords for the zip file.
Note:

• If you have any queries please attend the doubt clearing session (which will be scheduled on Monday 26/10/2015)
• Please visit http://cmosedu.com/cmos1/electric/electric.htm for Electric tool reference and
http://cmosedu.com/videos/electric/tutorial3/electric_tutorial_3.htm for layout design and
http://www.cmosedu.com/videos/electric/Electric_video_3/Electric_video_3.wmv for DRC, LVS and ERC
checks.

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