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2.4a Synchronous Buck-Boost DC DC Converter Ic Datasheet

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0% found this document useful (0 votes)
99 views21 pages

2.4a Synchronous Buck-Boost DC DC Converter Ic Datasheet

Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

Please note that Cypress is an Infineon Technologies Company.

The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.

Continuity of document content


The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.

Continuity of ordering part numbers


Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.

www.infineon.com

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S6BP202A
ASSP, 42V, 2.4A, Synchronous
Buck-boost DC/DC Converter IC
S6BP202A is a 1-Ch Buck-boost DC/DC converter IC with four built-in switching FETs. This IC is able to supply up to 2.4A of load
current within the very wide range from 2.5V to 42V in the input voltage. This IC has an operation mode that is automatically changed
to PFM operation during low load, which can achieve super-high efficiency with a very low quiescent current 20 µA. It is possible to
provide stable output voltage from an automotive cold cranking and load dump, up to 42V, conditions within 1 ms transition time. As a
result, this IC is suitable for power supply solutions of automotive and Industrial applications. This IC has the SYNC function, which is
capable of selecting the SYNC_IN that is able to inputs an external clock signal or the SYNC_OUT that is able to output an internal
clock. When selecting the SYNC_IN and an external clock signal in the range from 200 kHz to 400 kHz is inputted, the FETs perform
the switching operation with synchronizing signal from an external clock. When selecting the SYNC_IN and an external clock signal is
not inputted, the FETs perform the switching operation from an internal clock. When selecting the SYNC_OUT, this IC provides a clock
signal generated inside to external devices. The internal clock signal in the range from 200 kHz to 2.1 MHz can be set by an external
resistor. Since external voltage setting resistors and phase compensation capacitors are not required with this IC, it can reduce the
number of parts and a part mounting area. This IC has five protection functions, input under voltage lockout (input UVLO), output
under voltage protection (output UVP), output over voltage protection (output OVP), output over current protection (output OCP), and
thermal shutdown (TSD). Moreover, this IC has the power good (PG) function that indicates the state of the output voltage (VOUT
pin). When the output voltage reaches the PG voltage, the PG signal is outputted. Also, the power-on reset time for the PG signal is
selectable. The VOUT output voltage, SYNC function, VOUT UVP threshold, VOUT OVP threshold, power-on reset time of this
product are selectable from the product lineup (refer to the "1. Product Lineup").
Features
Applications
 Wide input voltage range: 2.5V to 42V
 Instrument cluster
 Selectable output voltage (factory settable):
5.000V/5.050V/5.075V/5.100V/5.125V/5.150V/5.200V  Advanced driver assistance systems (ADAS)
 Wide operating frequency range: 200 kHz to 2.1 MHz  Gateway module
 External synchronized clock range: 200 kHz to 400 kHz  Automotive applications
 SYNC function (factory settable)  Industrial applications
 SYNC_IN: External clock input
(Unless inputting clock, this IC operates by internal clock)
 SYNC_OUT: Internal clock output
Block Diagram
 Super-high efficiency by PFM operation
(When setting MODE pin to a low level)
S6BP202A
 Automatic PWM/PFM switching operation and fixed PWM Battery 2.5-42V
operation are selectable by MODE pin
 Built-in switching FET
 Synchronous current mode architecture Enable
5V LDO,
Enable
 Shutdown current: Lower than 1 µA 5V

Buck-
 Quiescent current: 20 µA
PWM/PFM Boost
 Power Good Monitor Switch DC/DC 5V / 2.4A

 Outputvoltage monitoring by window comparator OSC, Converter


External
 Power-on reset time (factory settable): 7 µs, 14 ms Clock for External 2.1 MHz
Synchronization /
SYNC
 Soft start time without load dependence: 0.9 ms Internal Clock Output
(When switching frequency = 2.1 MHz)
Frequency Setting
 Enhanced protection functions
 InputUVLO
Power Power Good
 Output UVP (factory settable): 92.0%, 95.5% Protection
Good
 Output OVP (factory settable): 108.0%, 104.5% GND
 Output OVC
 Thermal shutdown
 Small ETSSOP16 package (exposed PAD): 5 mm × 6.4 mm
 AEC-Q100 compliant (Grade-1)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-08496 Rev. *E Revised December 13, 2018

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S6BP202A

More Information
Cypress provides a wealth of data at www.cypress.com/pmic to help you to select the right PMIC device for your design, and to
help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for S6BP202A.

 Overview: Automotive PMIC Portfolio, Automotive PMIC  Evaluation Kit Operation Manual:
Roadmap  S6SBP202A1FVA1001:

 Product Selector: Power block of automotive instrument cluster


 S6BP202A:  Related Products:
1-Ch Buck-Boost Automotive PMIC  S6BP201A, S6BP203A:
 Application Notes: Cypress offers S6BP202A application 1-Ch Buck-Boost Automotive PMIC
notes. Recommended application notes for getting started  S6BP401A:
with S6BP202A are: 6-Ch Automotive PMIC for ADAS
 AN99497: Designing a Power Management System  S6BP501A, S6BP502A:
with S6BP201A, S6BP202A, and S6BP203A 3-Ch Automotive PMIC for Instrument Cluster
 AN201006: Thermal Considerations and Parameters

Document Number: 002-08496 Rev. *E Page 2 of 20

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S6BP202A

Contents
Features ................................................................................................................................................................................... 1
Applications ............................................................................................................................................................................ 1
Block Diagram......................................................................................................................................................................... 1
More Information .................................................................................................................................................................... 2
1. Product Lineup ............................................................................................................................................................... 4
2. Pin Assignment .............................................................................................................................................................. 5
3. Pin Descriptions ............................................................................................................................................................. 5
4. Architecture Block Diagram .......................................................................................................................................... 7
5. Absolute Maximum Ratings .......................................................................................................................................... 8
6. Recommended Operating Conditions .......................................................................................................................... 8
7. Electrical Characteristics .............................................................................................................................................. 9
8. Functional Description ................................................................................................................................................ 10
8.1 Block Description ......................................................................................................................................................... 10
8.2 Protection Function Table............................................................................................................................................ 11
9. Application Circuit Example and Parts list ................................................................................................................ 12
10. Application Note ........................................................................................................................................................... 13
10.1 Setting the Operation Conditions ................................................................................................................................. 13
11. Reference Data ............................................................................................................................................................. 15
12. Usage Precaution ......................................................................................................................................................... 17
13. RoHS Compliance Information ................................................................................................................................... 17
14. Ordering Information ................................................................................................................................................... 17
15. Package Dimensions ................................................................................................................................................... 18
16. Major Changes ............................................................................................................................................................. 19
Document History ................................................................................................................................................................. 19
Sales, Solutions, and Legal Information ............................................................................................................................. 20

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S6BP202A

1. Product Lineup
The VOUT output voltage, SYNC function, VOUT UVP threshold, VOUT OVP threshold, power-on reset time of this product are
set at the factory shipment. To order a product, select an item from the product lineup blow.

VOUT VOUT UVP Threshold [%] VOUT OVP Threshold [%] Power-on
Order SYNC
Part Number (MPN) Output Reset
Code Function Falling (Typ) Rising(Typ) Rising (Typ) Falling (Typ)
Voltage [V] Time[s]
S6BP202A1BST2B00A 1B SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A1CST2B00A 1C SYNC_OUT
7.0µ
S6BP202A1DST2B00A 1D SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A1EST2B00A 1E SYNC_OUT
5.000
S6BP202A1FST2B00A 1F SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A1GST2B00A 1G SYNC_OUT
14.0m
S6BP202A1HST2B00A 1H SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A1JST2B00A 1J SYNC_OUT
S6BP202A2BST2B00A 2B SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A2CST2B00A 2C SYNC_OUT
7.0µ
S6BP202A2DST2B00A 2D SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A2EST2B00A 2E SYNC_OUT
5.050
S6BP202A2FST2B00A 2F SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A2GST2B00A 2G SYNC_OUT
14.0m
S6BP202A2HST2B00A 2H SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A2JST2B00A 2J SYNC_OUT
S6BP202A3BST2B00A 3B SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A3CST2B00A 3C SYNC_OUT
7.0µ
S6BP202A3DST2B00A 3D SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A3EST2B00A 3E 5.075 SYNC_OUT
S6BP202A3FST2B00A 3F SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A3GST2B00A 3G SYNC_OUT
14.0m
S6BP202A3HST2B00A 3H SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A3JST2B00A 3J SYNC_OUT
S6BP202A4BST2B00A 4B SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A4CST2B00A 4C SYNC_OUT
7.0µ
S6BP202A4DST2B00A 4D SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A4EST2B00A 4E SYNC_OUT
5.100
S6BP202A4FST2B00A 4F SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A4GST2B00A 4G SYNC_OUT
14.0m
S6BP202A4HST2B00A 4H SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A4JST2B00A 4J SYNC_OUT
S6BP202A5BST2B00A 5B SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A5CST2B00A 5C SYNC_OUT
7.0µ
S6BP202A5DST2B00A 5D SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A5EST2B00A 5E SYNC_OUT
5.125
S6BP202A5FST2B00A 5F SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A5GST2B00A 5G SYNC_OUT
14.0m
S6BP202A5HST2B00A 5H SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A5JST2B00A 5J SYNC_OUT
S6BP202A6BST2B00A 6B SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A6CST2B00A 6C SYNC_OUT
7.0µ
S6BP202A6DST2B00A 6D SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A6EST2B00A 6E SYNC_OUT
5.150
S6BP202A6FST2B00A 6F SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A6GST2B00A 6G SYNC_OUT
14.0m
S6BP202A6HST2B00A 6H SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A6JST2B00A 6J SYNC_OUT

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S6BP202A

VOUT VOUT UVP Threshold [%] VOUT OVP Threshold [%] Power-on
Order SYNC
Part Number (MPN) Output Reset
Code Function Falling (Typ) Rising(Typ) Rising (Typ) Falling (Typ)
Voltage [V] Time[s]
S6BP202A7BST2B00A 7B SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A7CST2B00A 7C SYNC_OUT
7.0µ
S6BP202A7DST2B00A 7D SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A7EST2B00A 7E SYNC_OUT
5.200
S6BP202A7FST2B00A 7F SYNC_IN
92.0 93.0 108.0 107.0
S6BP202A7GST2B00A 7G SYNC_OUT
14.0m
S6BP202A7HST2B00A 7H SYNC_IN
95.5 96.5 104.5 103.5
S6BP202A7JST2B00A 7J SYNC_OUT
MPN: Marketing Part Number

2. Pin Assignment
Figure 2-1 Pin Assignment

(Top view)

PGND1 1 16 PGND2

LX1 2 15 LX2

PVIN 3 14 VOUT

BST 4 13 FB
EP: GND
VIN 5 12 RT

ENA 6 11 SYNC

MODE 7 10 PG

VCC 8 9 GND

(SEC016)

3. Pin Descriptions
Table 3-1 Pin Descriptions
Pin No. Pin Name I/O Description
1 PGND1 − GND pin for built-in switching FET
2 LX1 O Inductor connection pin
3 PVIN I Power supply pin for PWM controller and switching FETs
4 BST I BST(Boost) capacitor connection pin
5 VIN I Power supply pin
6 ENA I DC/DC converter enable pin
7 MODE I PWM/PFM operation control pin
8 VCC O VCC capacitor connection pin. LDO output pin of Internal reference voltage
9 GND − GND pin
Open drain output pin for power good. When being used, connect PG pin to VCC pin or VOUT
10 PG O
pin. When not being used, leave PG pin open.
External clock input pin / Internal clock output pin
11 SYNC I/O
For the SYNC pin setting, refer to "10.1 Setting the Operation Conditions"
Timing resistor connection pin for internal clock (switching frequency)
12 RT O
For the resistance, refer to "10.1 Setting the Operation Conditions"
13 FB I Output voltage feedback pin
14 VOUT O DC/DC converter output pin
15 LX2 O Inductor connection output pin.
16 PGND2 − GND pin for built-in switching FET
EP GND − GND pin

Document Number: 002-08496 Rev. *E Page 5 of 20

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S6BP202A

Figure 3-1 I/O Pin Equivalent Circuit Diagram

<VIN pin, PVIN pin> <LX1 pin, BST pin> <VOUT pin, LX2 pin>

VIN 5 PVIN 3 14 VOUT


PVIN 3 VCC 8

4 BST
GND 9 15 LX2

2 LX1

PGND1 1
PGND2 16 PGND1 1 PGND2 16

<VCC pin> <FB pin> <PG pin>

VIN 5 FB 13 10 PG

13 FB

8 VCC

GND 9 GND 9 GND 9

<ENA pin> <MODE pin> <SYNC pin>

VIN 5 VCC 8 VCC 8

ENA 6 MODE 7 SYNC 11

GND 9 GND 9 GND 9

<RT pin>

VCC 8

12 RT

GND 9

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S6BP202A

4. Architecture Block Diagram


Figure 4-1 Architecture Block Diagram

VIN
VIN 5
VCC
8

ENA 5V VIN RT
6 BGR OSC 12
LDO UVLO

SYNC
TSD 11 SYNC
VCC
SYNC
GND UVLO MODE
9 7 MODE
Bypass
SW

ck
Buck-Boost DC/DC Converter
VCC

PG
10
PG
FB
13
BST
4
VIN
FB

PVIN VOUT
3 14 VOUT
ErrAMP

High Side High Side


FET1
LS LS FET2

Slope Boost
PFMCMP

LX1 LX2
2 15
Mode
ICMP
ck

Pulse

PWM
Low Side Logic Low Side
FET1 FET2

PGND1 PGND2
1 16

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S6BP202A

5. Absolute Maximum Ratings


Rating
Parameter Symbol Condition Unit
Min Max
VVIN VIN pin −0.3 +48.0 V
Power supply voltage (*1)
VPVIN PVIN pin −0.3 +48.0 V
VVCC VCC pin −0.3 +6.9 V
VBST BST pin −0.3 +48.0 V
VLX1 LX1 pin −2.0 +48.0 V
VLX2 LX2 pin −2.0 +6.9 V
VFB FB pin −0.3 VVCC V
Terminal voltage(*1) VRT RT pin −0.3 VVCC V
VMODE MODE pin −0.3 VVCC V
VSYNC SYNC pin −0.3 VVCC V
VENA ENA pin −0.3 +48.0 V
VPG PG pin −0.3 +6.9 V
VBST-LX Between BST–LX1 pins −0.3 +6.9 V
Difference voltage(*1)
VGND Between GND–PGND1 pins, Between GND–PGND2 pins −0.3 +0.3 V
PG output current IPG PG pin −3 0 mA
Power dissipation (*1) PD Ta ≤ ±25°C 0 3324 (*2) mW
Storage temperature TSTG − −55 +150 °C
*1: When PGND1 = PGND2 = GND = 0V
*2: When the product is mounted on 76.2 mm × 114.3 mm, four-layer FR-4 board
Warning:
1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

6. Recommended Operating Conditions


Value
Parameter Symbol Condition Unit
Min Typ Max
At start-up 5.0 12.0 42.0 V
Power supply voltage (*1) VVIN VIN pin
After start-up 2.5 12.0 42.0 V
VBST BST pin 0.0 − 47.5 V
VLX1 LX1 pin −1.0 +12.0 +42.0 V
VLX2 LX2 pin −1.0 − +5.5 V
VFB FB pin 0.0 − 5.5 V
Terminal voltage (*1)
VMODE MODE pin 0.0 − 5.5 V
VSYNC SYNC pin 0.0 − 5.5 V
VENA ENA pin 0.0 12.0 42.0 V
VPG PG pin 0.0 − 5.5 V
VBST-LX1 Between BST−LX1 pins 0.0 − 5.5 V
Difference voltage(*1)
VGND Between GND−PGND1 pins,Between GND−PGND2 pins −0.05 0.00 +0.05 V
PG output current IPG PG pin (sink current) 0 − 1 mA
BST capacitance CBST Between BST−LX1 pins 0.068 0.100 0.470 µF
VCC capacitance CVCC Between VCC−GND pins 2.2 4.7 10.0 µF
Timing resistance RRT Between RT−GND pins. When using internal clock 22 − 270 kΩ
Operating ambient
Ta − −40 +25 +125 °C
Temperature
*1: When PGND1 = PGND2 = GND = 0V
Warning:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are
considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 002-08496 Rev. *E Page 8 of 20

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S6BP202A

7. Electrical Characteristics
VIN=PVIN=12V, ENA=5V
(Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.)
Value
Parameter Symbol Condition Unit
Min Typ Max
IVOUT = 0A, When VVOUT = 5.000 (*1) 4.925 5.000 5.075 V
IVOUT = 0A, When VVOUT = 5.050 (*1) 4.975 5.050 5.125 V
IVOUT = 0A, When VVOUT = 5.075 (*1) 4.999 5.075 5.151 V
VOUT output voltage VVOUT IVOUT = 0A, When VVOUT = 5.100 (*1) 5.024 5.100 5.176 V
IVOUT = 0A, When VVOUT = 5.125 (*1) 5.048 5.125 5.201 V
IVOUT = 0A, When VVOUT = 5.150 (*1) 5.073 5.150 5.227 V
IVOUT = 0A, When VVOUT = 5.200 (*1) 5.122 5.200 5.278 V
Buck-boost FB input resistance RFB EN = 0V, Ta = +25°C 3.84 4.80 5.76 MΩ
DC/DC RHSIDEFET1 LX1 = −30 mA (Between PVIN−LX1) − 150 − mΩ
converter Switching FET RLSIDEFET1 LX1 = 30 mA (Between LX1−PGND1) − 150 − mΩ
Block on-resistance RHSIDEFET2 LX2 = −30 mA (Between VOUT−LX2) − 150 − mΩ
RLSIDEFET2 LX2 = 30 mA (Between LX2−PGND2) − 150 − mΩ
switching FET
ILEAK − − − 5 µA
leakage current
Soft-start time TSS RRT = 22 kΩ 0.855 0.9 0.945 ms
PVIN ≥ 7.5V, Ta = 25 °C 2.4 (*2) − − A
Maximum output current IVOUT
PVIN = 4.5V, Ta = 25 °C 1.0 (*2) − − A
Current limit ILIMT PVIN = 12V, L = 2.2 µH 2.4 (*2) − − A
5V LDO block VCC output voltage VVCC VIN = 12V 4.9 5.0 5.1 V
VIN UVLO VIN UVLO falling threshold VUVLOVINHL VIN input voltage when falling 2.30 2.40 2.50 V
block VIN UVLO rising threshold VUVLOVINLH VIN input voltage when rising 4.55 4.75 4.95 V
VCC UVLO VCC UVLO falling threshold VUVLOVCCHL VCC input voltage when falling 2.30 2.40 2.50 V
block VCC UVLO rising threshold VUVLOVCCLH VCC input voltage when rising 4.55 4.75 4.95 V
VENA Enable voltage range 1.10 − VVIN V
Enable condition
ENA pin VDSB Disable voltage range 0.0 − 0.2 V
ENA input current IENA VENA = 12V − 1 3 µA
VMODE_L Automatic PWM/PFM switching 0.0 − 0.4 V
MODE input voltage
MODE pin VMODE_H Fixed PWM operation 2.0 − VVOUT V
MODE Input current IMODE MODE = 5.0V − 5 10 µA
Switching frequency RRT = 22kΩ 2.0 2.1 2.2 MHz
OSC block FOSC
(SYNC output frequency) RRT = 270kΩ 180 200 220 kHz
VSYNC_L When selecting SYNC_IN (*1) 0.0 − 0.4 V
SYNC input threshold
VSYNC_H When selecting SYNC_IN (*1) 2.0 − VVOUT V
SYNC input frequency VSYNC_L When selecting SYNC_IN (*1) 200 − 400 kHz
SYNC block
SYNC input duty ratio VSYNC_H When selecting SYNC_IN (*1) +20 +50 +80 %
(SYNC_IN/
SYNC_OUT) SYNC output frequency FOUTPUT When selecting SYNC_OUT (*1) − FOSC − Hz
SYNC output duty ratio FOUTDUTY When selecting SYNC_OUT (*1) +40 +50 +60 %
VSYNC = 5.0V, When selecting
SYNC leakage current ILKSYNC − 5 10 µA
SYNC_IN (*1)
Falling threshold for VOUT output 90.5 92.0 93.5 %
VOUT UVP falling threshold PGUVPHL
voltage setting (*1) 94.0 95.5 97.0 %
Rising threshold for VOUT output 91.5 93.0 94.5 %
VOUT UVP rising threshold PGUVPLH
voltage setting (*1) 95.0 96.5 98.0 %
Rising threshold for VOUT output 106.5 108.0 109.5 %
VOUT OVP rising threshold PGOVPLH
voltage setting (*1) 103.0 104.5 106.0 %
PG block Falling threshold for VOUT output 105.5 107.0 108.5 %
(UVP, OVP) VOUT OVP falling threshold PGOVPHL
voltage setting (*1) 102.0 103.5 105.0 %
Leak current ILKPG VPWRGD = 5.0V, VENA = 0V 0 − 1 µA
Low level output voltage VOLPG IPGSINK = 1 mA 0.025 0.05 0.15 V
Delay time
TPPG At power shutdown − 7(*2) 12(*2) µs
at abnormal detection
− 7(*2) 12(*2) µs
Power-on reset time (*1) TRPG At power good
9.1 14.0 18.9 ms

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S6BP202A

Value
Parameter Symbol Condition Unit
Min Typ Max
Thermal TTSDH − − 165 (*2) − °C
shutdown Shutdown temperature
TTSDL Hysteresis − 10 (*2) − °C
block (TSD)
Shutdown current IVINSDN VIN input current, VENA = 0V − 1 5 µA
VIN input current, VENA = 12V,
Supply current
Quiescent current IVINQ IVOUT = 0A, − 20 40 µA
MODE/SYNC/PG Pins = OPEN
*1: Refer to "1. Product Lineup"
*2: The electrical characteristic is ensured by statistical characterization and indirect tests.

8. Functional Description
8.1 Block Description

Input Under Voltage Lockout (Input UVLO)


The input UVLO is the function that prevents a malfunction of this IC from the following status, and protects poststage devices.
 Transitional state at start-up
 Momentary drop of power supply voltage
To prevent such a malfunction, this protection monitors the VIN input voltage and VCC voltage. When either VIN or VCC voltage falls
to the UVLO falling threshold, 2.4V (Typ), or lower, the IC stops the VOUT voltage output and becomes UVLO status. When both VIN
and VCC voltages reach the UVLO rising threshold, 4.75V (Typ), or higher, the IC is released from the UVLO state and returns to the
normal operation.

Output Under Voltage Protection (Output UVP)


The output UVP is the function that monitors the voltage drop of the VOUT pin and notifies by the PG pin.
When the output voltage falls to the UVP falling threshold (PGUVPHL) for the output voltage setting or lower, the PG voltage is fixed to
the low level. The IC becomes the UVP status, but the switching operation is maintained under the UVP status.
When the output voltage once again reaches the UVP rising threshold (PGUVPLH) for the output voltage setting or higher, the IC is
released from the UVP state and the PG voltage is fixed to the high level.

Output Over Voltage Protection (Output OVP)


The output OVP is the function that monitors the voltage rise of the VOUT pin and stops the switching operations, which protects
poststage devices from overvoltage. Also, the VOUT state is notified by the PG pin.
When the output voltage rises to the OVP falling threshold (PGOVPLH) for the output voltage setting or higher, the PG voltage is fixed to
the low level. The IC becomes the OVP status, and the switching operations of the high-Side FETs are stopped. When the output
voltage once again falls to the OVP falling threshold (PGOVPHL) for the output voltage setting or lower, the IC is released from the OVP
state and resumes the switching operations. The PG voltage is fixed to the high level again.

Output Over Current Protection (Output OCP)


The output OCP is the function that limits the excessive current load and protects poststage devices.

Thermal Shutdown (TSD)


The TSD is the function that protects the IC from heat-destruction. When the junction temperature reaches +165°C (Typ), the
high-side and low-side switching FET are turned off and the IC becomes the TSD status. When the junction temperature once again
falls to +155°C (Typ) or lower, the IC is released from the TSD state and restarts the power supply.

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S6BP202A

8.2 Protection Function Table


The following table shows the state of each pin when each protection function operates.
Table 8-1 Protection Function Table
DC/DC
ENA Pin PG Pin
Function Converter Remarks
Setting Output Operation
It is recommended to connect PG pin to VCC pin or VOUT
pin via a pull-up resistor.
Shutdown operation L Hi-Z (*1) Shutdown
When setting ENA pin to a low level, Both VCC pin and
VOUT pin voltages drop to 0V. Therefore, PG pin outputs 0V.
Nominal operation H Hi-Z (*1) Switching −
Input under voltage protection After releasing UVLO state, this IC is automatically reset with
H L Shutdown
(Input UVLO) soft start.
Output under voltage protection
H L Switching −
(Output UVP)
Output over voltage protection
H L Shutdown −
(Output OVP)
Output over current protection
H L Switching OCP operates to drop the output voltage.
(Output OCP)
Thermal shutdown After releasing TSD state, this IC is automatically reset with
H L Shutdown
(TSD) soft start.
*1: PG pin is formed as an open drain structure. The internal MOSFET is in the OFF state.

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S6BP202A

9. Application Circuit Example and Parts list


Figure 9-1 Application Circuit Example

VIN VIN
VIN 5 S6BP202A
3 PVIN
CVIN VCC CPVIN
0.1 μF VCC 8 10 μF
4 BST
CVCC CBST
4.7 μF
VOUT
FB 13 0.1 μF
2 LX1
LLX
MODE MODE 7 2.2 μH
15 LX2
VOUT
SYNC SYNC 11 VOUT
14 VOUT
CVOUT_1 CVOUT_2
ENA ENA 6 22 μF 22 μF

RT 12 1 PGND1
RRT
22 kΩ GND 9 16 PGND2 RPG VCC or VOUT
1 MΩ
GND EP 10 PG
PG

FOSC = 2.1 MHz


When selecting “VOUT output voltage = 5.0V”

Table 9-1 Parts List


Package Size
Symbol Item Value Part Number Vendor Remarks
(W×L×H[mm])
CVIN,
Ceramic capacitor 0.1 μF CGA2B3X7R1H104K050BB TDK 1.0×0.5×0.5 X7R, Rated voltage: 50 Vdc
CBST
CPVIN Ceramic capacitor 10 μF CGA9N3X7R1H106K230KB TDK 5.7×5.0×2.3 X7R, Rated voltage: 50 Vdc
CVCC Ceramic capacitor 4.7 μF CGA4J3X7R1C475K125AB TDK 2.0×1.25×1.25 X7R, Rated voltage: 16 Vdc
CVOUT_1,
Ceramic capacitor 22 μF CGA6P1X7R1C226M250AC TDK 3.2×2.5×2.5 X7R, Rated voltage: 16 Vdc
CVOUT_2
LLX Inductor 2.2 μH CLF7045T-2R2N-D TDK 7.2×6.9×4.5 DCR: 14.6 mΩ, IDC_MAX: 5.5A
RRT Resistor 22 kΩ RK73H1JTTD2202F KOA 0.8×1.6×0.45 −
RPG Resistor 1 MΩ RK73H1JTTD1004F KOA 0.8×1.6×0.45 −
TDK: TDK Corporation
KOA: KOA Corporation

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S6BP202A

10. Application Note


10.1 Setting the Operation Conditions

Operation State of DC/DC Convertor When Selecting SYNC_IN


The operation stage of DC/CD converter is set by both MODE pin and SYNC pin.
Table 10-1 Operation State of DC/DC Convertor When Selecting SYNC_IN
MODE Pin SYNC Pin (Signal Input) Operation State of DC/DC Convertor
L (*3) Automatic PWM/PFM switching operation from an internal clock
L (*3) External clock input (*5) Fixed PWM operation with synchronizing signal from an external clock (*2)
H (*4) Prohibition of use (*1)
L (*3) Fixed PWM operation from an internal clock
H (*4) External clock input (*5) Fixed PWM operation with synchronizing signal from an external clock (*2)
H (*4) Prohibition of use (*1)
*1: When selecting SYNC_IN and setting SYNC pin to a high level, the quiescent current (IVINQ) is increased.
*2: Set the timing resistance (RRT) to 330 kΩ.
*3: Apply the GND1 or GND2 voltage.
*4: Apply the VOUT voltage.
*5: Apply the VOUT voltage at a high level. Apply the GND1 or GND2 voltage at a low level

Operation State of DC/DC Convertor When Selecting SYNC_OUT


When selecting SYNC_OUT, the phase of SYNC clock output is shifted from an internal clock.
Table 10-2 Operation State of DC/DC Convertor When Selecting SYNC_OUT
MODE Pin SYNC Pin Operation State of DC/DC Convertor
L (*1)
Internal clock output Fixed PWM operation from an internal clock
H (*2)
*1: Apply the GND1 or GND2 voltage.
*2: Apply the VOUT voltage.

Setting of Switching Frequency (Internal Clock)


The switching frequency (internal clock) can be set by RT resistor, which value is the timing resistance (RRT), connected to RT pin.
Set the timing resistance in a range within the following graph
Figure 10-1 FOSC vs RRT Measured Characteristic

FOSC vs RRT Measured Characteristic


2.5

2.0

1.5
FOSC [MHz]

1.0

0.5

0.0
0 100 200 300 400
RRT [kΩ]
S6BP202AGraph001

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S6BP202A

The reference value can be calculated by the following formula.


1
FOSC [Hz] ≈
R RT × 21.7 × 10−12
FOSC : Switching frequency [Hz]
RRT : Timing resistance [Ω]

Setting of Soft-start Time


The Soft-start time is determined by the timing resistance (RRT), the value of the resistor connected to RT pin.
1
TSS [s] = × 2 × 1024
FOSC
TSS : Soft-start time [s]
FOSC : Switching frequency [Hz]

Consideration of VOUT Maximum Output Current


Make sure the VOUT maximum output current in a range within the following graph.
Figure 10-2 IVOUT vs VVIN

IVOUT vs VVIN
3.0
Ta=+25oC, FOSC=2.1MHz
Ta=+125oC, FOSC=2.1MHz
2.5

2.0
IVOUT [A]

1.5

1.0

0.5

0.0
0 1 2 3 4 5 6 7 8 9 10 11 12
VVIN [V]
S6BP202AGraph002

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S6BP202A

11. Reference Data


The followings are the reference data measured under the conditions shown in ”9. Application Circuit Example and Parts list”.

Efficiency (Fixed PWM) Efficiency (Automatic PWM/PFM)


VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC, VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC,
LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF
100 100
VVIN = 12 V
VVIN = 2.5 V
90 90
VVIN = 4.5 V
80 80

70 70
VVIN = 2.5 V
Efficiency [%]

Efficiency [%]
60 60
VVIN = 4.5 V
50 50 VVIN = 12 V
VVIN = 42 V VVIN = 42 V
40 40

30 30

20 20

10 10
0 0
0.001 0.01 0.1 1 3 0.001 0.01 0.1 1 3
Load Current [A] Load Current [A]
S6BP202AGraph004-1 S6BP202AGraph004-2

Load Regulation (Fixed PWM) Line Regulation (Fixed PWM) IVINQ vs VVIN (Automatic PWM/PFM)
VVIN = 12V, VVOUT = 5 V, FOSC = 2.1 MHz set, VVOUT = 5 V, FOSC = 2.1 MHz set, VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set,
LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF
5.08 5.08 140

5.06 5.06 120

5.04 5.04
100
5.02 o 5.02
TA = +125 C TA = +125 oC,
IVINQ [µA]
VVOUT [V]

VVOUT [V]

80
TA = +25 oC Load Current = 1.5 A
5.00 5.00
o
TA = +25 C, 60
4.98 4.98 Load Current = 2.4 A

40 TA = +125oC
4.96 TA = -40 oC 4.96
o TA = +25oC
TA = -40 C,
4.94 4.94 Load Current = 2.4 A 20
TA = -40oC
4.92 4.92 0
0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45
Load Current [A] VVIN [V] VVIN [V]
S6BP202AGraph005 S6BP202AGraph006 S6BP202AGraph008-1

Turn On Response Turn Off Response


VVIN = 12 V, VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set, VVIN = 12 V, VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set,
TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF
Automatic PWM/PFM Automatic PWM/PFM
ENA ENA
5 V/div 5 V/div

VOUT VOUT
5 V/div 5 V/div

LX1 LX1
2 A/div 2 A/div

PG PG
5 V/div 5 V/div

VCC VCC
5 V/div 5 V/div

2 ms/div 2 ms/div
S6BP202AGraph009-1 S6BP202AGraph009-2

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S6BP202A

Load Transient Response Load Transient Response


VVIN = 12 V, VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC, VVIN = 12 V, VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC,
LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF
Automatic PWM/PFM Automatic PWM/PFM

VOUT VOUT
200 mV/div 200 mV/div
AC-Coupled AC-Coupled

Load Load
Current 0A 2.4 A Current 2.4 A 0A
1 A/div / 10 µs 1 A/div / 10 µs

PG PG
5 V/div 5 V/div

200 µs/div 200 µs/div


S6BP202AGraph010-1 S6BP202AGraph010-2

Cold Crank Line Transient Response Load Dump Line Transient Response
VVOUT = 5 V, Load Current = 0.2 A, FOSC = 2.1 MHz set, TA = +25oC, VVOUT = 5 V, Load Current = 2.4 A, FOSC = 2.1 MHz set, TA = +25oC,
LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF
Automatic PWM/PFM Automatic PWM/PFM

40 V 11 V
/ 1 ms
11 V 2.5 V VIN
/ 1 ms 10 V/div 11 V 40 V
VIN / 1 ms
2 V/div 2.5 V 6V
/ 1 ms

VOUT
VOUT 200 mV/div
AC-Coupled
200 mV/div
AC-Coupled

PG PG
5 V/div 5 V/div

4 ms/div 1 ms/div
S6BP202AGraph011-1 S6BP202AGraph011-2

Switching Waveform Ripple Waveform


VVIN = 12 V, VVOUT = 5 V, Load Current = 2.4 A, FOSC = 2.1 MHz set, VVIN = 12 V, VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set,
TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF
Automatic PWM/PFM Automatic PWM/PFM

LX1 VOUT
2 V/div 50 mV/div
AC-Coupled

1 µs/div 10 ms/div
S6BP202AGraph012-1 S6BP202AGraph012-2

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S6BP202A

12. Usage Precaution


Printed circuit board ground lines should be set up with consideration for common impedance.

Take appropriate measures against static electricity.


 Containers for semiconductor materials should have anti−static protection or be made of conductive material.
 Aftermounting, printed circuit boards should be stored and shipped in conductive bags or containers.
 Work platforms, tools, and instruments should be properly grounded.
 Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground.

Do not apply negative voltages.


The use of negative voltages below −0.3 V may make the parasitic transistor activated to the LSI, and can cause malfunctions.

13. RoHS Compliance Information


This product has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and
polybrominated diphenyl ethers (PBDE).

14. Ordering Information


Table 14-1 Ordering Information
Order Code Part Number (MPN) (*1) Package
1F S6BP202A1FST2B00A
1G S6BP202A1GST2B00A Plastic ETSSOP16 (0.65 mm pitch), 16-pin
4F S6BP202A4FST2B00A (Package Code: SEC016)
7F S6BP202A7FST2B00A
MPN: Marketing Part Number
*1: Please contact our sales division for the part numbers (refer to "1. Product Lineup") not mentioned in this table.

Figure 14-1 Ordering Part Number Definitions

S 6B P 2 0 2 A XX S T 2 B 0 0A
Fixed on 00A
Packing: B = 13 inch Tape and Reel
Package: T2 = ETSSOP, Pure Sn / Low-Halogen
Reliability Grade: S = 10 ppm
Preset Condition (Order Code): See “Product Lineup”
Revision: A = 1st Revision
Product ID: 02
Topology: 2 = Switch-Mode Power Supply (Integrated FET)
Product Type: P = Power Management IC
Product Class: 6B = Automotive Analog
Company ID: S = Cypress

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S6BP202A

15. Package Dimensions

Package Code: SEC016

002-10769 Rev. **

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16. Major Changes


Spansion Publication Number: S6BP202A_DS405-00027

Page Section Change Results


Preliminary 0.1
− − Initial release
Preliminary 0.2
The sentences of the "Notice to Readers" were changed from "the contents of Full Production"
1 Cover page
to "the contents of Preliminary".
10. Electrical
13 "(TSD)" was added in the table of "10. Electrical Characteristics".
Characteristics
NOTE: Please see “Document History” about later revised information.

Document History
Document Title: S6BP202A, ASSP, 42V, 2.4A, Synchronous Buck-boost DC/DC Converter IC
Document Number: 002-08496

Orig. of Submission
Revision ECN Description of Change
Change Date

** − HIXT 09/04/2015 New Spec.

Added Block Diagram


*A 5056149 HIXT 12/18/2015 Added Figure 15-1
Updated 16. Package Dimensions
Added “AEC-Q100 compliant (Grade-1)” in Features
Added Figure 3-1 I/O Pin Equivalent Circuit Diagram
The followings in 7. Electrical Characteristics were updated.
The parameter name of IVOUT was changed from ”VOUT output voltage” to
*B 5164343 HIXT 03/08/2016 “Maximum output current”
The max values of IVOUT were moved to the min column.
Added 11. Development Support
Added 12. Reference Data
Deleted the ES part number from Table 15-1

*C 5839054 MASG 07/31/2017 Adapted Cypress new logo.

Updated to the Cypress naming and format


Updated “TSSOP”  “ETSSOP” in Features, Table 14-1 and Figure 14-1
Updated 15 Package Dimensions
*D 5909405 HIXT 10/13/2017 Added More Information
Deleted “11. Development Support” (Moved to More Information)
Changed the suffix of the Part Number from “000” to “00A” in 1. Product Lineup
Table 14-1 and Figure 14-1

*E 6409930 SSAS 12/13/2018 No change; sunset review.

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S6BP202A

Sales, Solutions, and Legal Information


Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.

Products PSoC® Solutions


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Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC
(“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual
property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as
specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied
by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary
code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those
claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with
Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress
hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume
any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample
design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and
test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for
use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other
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failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or
system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in
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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or
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brands may be claimed as property of their respective owners.

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