WT tye \ a 2020! Uttar Pradesh Public Service Commission Combined State Engineering Services Examination Assistant Engineer Electrical Engineering Digital Electronics Well Illustrated Theory with Solved Examples and Practice Questions MADE EASY Publications Note: This book contains copyright subject mater MADE EASY Publications, New Deh. No part ofthis book may be reproduced, "More in avetrewlaitem or transnted in any fom or byanytneane. laters ae able tobe legally prosecutedDigital Electronics Contents ‘UNIT TOPIC 1, Boolean Algebraand Logic Gates 2. Combinational Circuit 3. Sequential Circuits. 4, Convertorsand Samplers 5. Semiconductor Memory... 6. Logic Families 7. ActiveFiltersand Multivibrators 9000 PAGE NO. 31-51 52°79, 80-94 95-105 106 - 130, 131-149zmaAuS mA 11 1.2 1.241 1.2.2 Boolean Algebra and Logic Gates Introduction + The binary operations performed by any digital circuit with the set of elements 0 and 1, are called logical operations or logic functions. The algebra used to symbolically represent the logic function is called Boolean algebra. Itis a two state algebra invented by George Boole in 1854 + Thus, a Boolean algebra is a system of mathematics logic for the analysis and designing of digital systems. ‘+ Avariable or function of variables in Boolean algebra can assume only two values, either a’0' or a 1’, Hence, (unlike another algebra) there are no fractions, no negative numbers, no square roots, no cube roots, no logarithms ete. Logic Operations + InBoolean algebra, all the algebraic functions performed is logical. These actually represent logical operations. The AND, OR and NOT are the basic operations that are performed in Boolean algebra. ‘* In addition to these operations, there are some derived operation such as NAND, NOR, EX-OR, EX-NOR thal are also performed in Boolean algebra ‘AND Operation The AND operation in Boolean algebra is similar to the multiplication in ordinary algebra. Itis a logical operation performed by AND gate. Le Nutiaw Le teeny tow OR Operation ‘The OR operation in Boolean algebra is performed by OR-gate AtA=A A+0=A += Nullew A+1=1 te tdontty iow A+A1.2.3 124 12.5 1.2.6 13 1.3.1 1.3.2 1.3.3 Electrical Engineering UPPSC-AE MADE EASY NOT Operation ‘* The NOT operation in Boolean algebra is similar to the complementation or inversion in ordinary algebra, The NOT operation is indicated by a bar () or (") over the variable. © AF, Aor At (complementation law) and A = double complementation law. NAND Operation The NAND operation in Boolean algebra is performed by AND operation with NOT operation ie. the negation of AND gate operation is performed by the NAND gate. NOR Operation ‘The NOR operation in Boolean algebra is performed by OR operation with NOT operation, ie. the negation of OR gate operation is performed by the NOR gate EX-OR Operation Unlike basic operations of logic gates, this used for special purpose and is represented by symbol where A@B= AB+AB Laws of Boolean Algebra ‘The Boolean algebra is governed by certain well developed rules and laws. Commutative Laws ‘+The commutative law allows change in position of AND or OR variables. There are two commutative laws, @) A+B=B+A Thus, the order in which the variables are ORed is immaterial (i) A-B=B-A Thus, the order in which the variables are ANDed is immaterial + This law can be extended to any number of variables Associative Laws ©The associative law allows grouping of variables. There are two associative laws () (A+B) +C=A+(8+Q) Thus, the way the variables are grouped and ORed is immaterial (i) (A-B)C=A-(B-O) Thus, the way the variables are grouped and ANDed is immaterial + This law can be extended to any number of variables, Distributive Laws + The distributive law allows factoring or multiplying out of expressions. There are two distributive laws () AB+0)=AB+AC (ii) A+ BC=(A+B)(A+C) * This lawis applicable for single variable as well as a combination of variables.MADE EASY Digital Electronics Boolean Algebra and Logic Gates 5 1.34 1.3.5 1.3.6 14 1.41 1.4.2 1.4.3 Idempotence Laws clempotence means the same value. There are two Idempotence laws @ AAA i.e. ANDing of a variable with itself is equal to that variable only (i) AvA=A ie. ORing ofa variable with itself is equal to that variable only. Absorption Laws There are two absorption laws () A+ AB= AG +B)=A (i) AASB) =A Involutionary Law This law states thal, for any variable ‘A’ y=A Boolean Algebraic Theorems De Morgan’s Theorem + Those are very useful in simplifying expressions in which a product or sum of variables is inverted + DeMorgan’s theorem represents two of the most important rules of Boolean algebra () AB=A+8 hus, the complement of the product of variables is equal to the sum of their individual complements. (i) AvB=A6 hus, the complement of a sum of variables is equal to the product of their individual complements. The above two laws can be extend for'n’ variables as AA Anh = Ath +A, and ReAerot hy = Ae Ay AyAy Transposition Theorem ‘The transposition theorem states that (AB + AC) = (A+C)(A+B) Consensus Theorem/Redundancy Theorem * This theorem is used to eliminate redundant term, + Avariable is associated with some variable and its compliment is associated with some other variable and the next term is formed by the left over variables, then the term becomes redundant, + Itis applicable only if a Boolean function, () Contains 3-variabies. (ii) Each variable used two times, (iii) Only one variables in complemented or uncomplemented form.6 Electrical Engineering UPPSC-AE MADE EASY Publieatone ‘Then, the related terms to that complemented and uncomplemented variable is the answer. * Consensus theorem can be extended to any number of variables. eg. AB+AC+BC = AB+AC ma [7 Example-1.1 The Boolean expression (A + B) (B + C)(C + A) = (A+B) (B+C) canbe simplified as (a) (A+B)(B+C) (b) (A+8)(B+C) (c) (A+8)(B+C) (a) (A+B)(B+C) Solution : (a) Proof: LHS = (A+B)(B+C)(C+A) = (AB+AC+BO)(C+A) = ABC + AC+BC+AB+ AC+ ABC = AC+BC+AB RHS = (A+B)(B+C) AB 4+ AC + BC =LHS Mi U7 bane ABC is equal to (a) A+B+E (b) ABC (c) A+B+C (a) A-B-C [UPPsc] Solution: (¢) =A+B+0 1.4.4 Duality Theorem itis one of the elegant theorems proved in advance mathematics. “Dual expression” is equivalent to write a negative logic of the given Boolean relation. For this we have to (change each OR sign by an AND sign and vice-versa (i) complement any 0" or 1” appearing in expression (ii) keep lterals/variables as itis. mus [7 Example-1.3 The self dual expression of boolean relation, ABC+ABC+ABC is (a) (A+B+0)(A+B+0)(A+B+0) (o) (A+B+C)(A+B+C)(A+B+C) (0) (A+B+0)(A+B+0)(A+B+0) (d) (A+ B+ 0)(A+B+0)(A+B+0) Solution: (¢) ABC+ABC+ABC ItsDUAL u (A+B+0)(A+B+0)(A+B+C)MADE EASY Digital Electronics Boolean Algebra and Logic Gates 7 tea '* For any logical expression, if we take two times Dual, we get same given expression as previous. ‘+ For 1-time Dual, ifwe get same function or expression itis called "Self Dual Expression’. 4 * With N-variables, maximum possible Self-Dual Funetion = (2) * = 2"!# ‘+ Remember that with \-variables, maximum possible distinct logic functions = 2" 1.4.5 Complementary Theorem For obtaining complement expression we have to (change each OR sign by AND sign and vice-versa. (i) complement any 0" or 1” appearing in expression (ii) complement the individual iterals/variables. mus [7 Example- 1.4 The compliment of the function '= ABC + ABC + ABC is equal to (a) (A+8+0)(A+B+C)(A+B+C) (bt) (A+B+C)(A+B+0)(A+B+C) (c) (A+B+0)(A+B+C)(A+B+C) (d) (A+B+C)(A+B+C)(A+B+C) Solution : (a) F = Complement off 7 = AsB+O(A+B+O(A+B+Q) mas [7 Example- 1.5 The Boolean expression A(A + B) is equal to (a) 1 (b) B () A (d) A+B [UPPSC} Solution: (e) Y= AA+B) = AALAB = A+ AB = All +8) =A mus [7 Example- 1,6 The Boolean function (x + y) (¥ + 2) (y+ 2) is equal to which one of the following expressions? (a) (&+y) +2) (b) (¥ +2) (y +2) (c) (+ y)(¥ +2) (d) (&+y) e+ 2) Solution: (€) By using consensus theorem, (xt y)(B+Z)(y +2) = (ety) (R +2)8 Electrical Engineering UPPSC-AE MADE EASY mus [7 Example- 1.7. The minimized form of the logical expression (, (a) AC+8C+ AB (b) AC +BC + AB () AC+ BC+ AB (d) AC+BC+AB + ABC + ABC + ABC) is Y= ABC+ ABC+ ABC+ ABC +ABC+ ABC = AC(8+B)+AB(C+0)+BC(A+A) = AC+AB+ BC ms [7 Example- 1.8 IfX and Y are Boolean variables, which one of the following is the equivalent of X®Y@XY? (a) X+¥ (b) X+¥ (c) 0 (d) 1 Solution: (b) Let Z=X@YOXY Z= X@[%XY)+YRV)] XO[V(K+¥)] = XO[KY)] X (XY) + X(XY) = XV+X(X+Y¥) RY 4X4 XY = RY 4X +7) = XV4X = (X+X)(X+N=(X+ YY) 1.5 Representation of Boolean Functions ‘+ A function of 'n! Boolean variables denoted by 4, A,,--A,) is another variable of algebra and takes one of the two possible values either 0 or 1. The various ways of representing a given function are discussed below: Boolean Function Representation ‘Canonical form Minimal form + {Allthe terms contain all the variables Minimum numbers of Iteral ‘ther in complementary on uncomplantary form Example. Example: FiA, 5, C)= ABC + ABC + ABC FIA.B, C)=A+ABC+ ABC= A +The term tera’ means a binary variable either in complementary or in uncomplimentary form, 1.5.1 Minterms and Maxterms: + mbinary variables have 2° possible combinations, ‘+ Minterm is a product term, it contains all the variables either complementary or uncomplimentary form for that combination the function output must be ‘t Maxtermis a sum term, it contains allthe variables either complementary or uncomplimentary form for that combination the function output must be ‘0MADE EASY Digital Electronics Boolean Algebra and Logic Gates 9 Nea ‘+ In "Minterms” we assign to each uncomplemented variable and ‘0’ to each complemented, variable. ‘+ In"Maxterms" we assign ‘0'to each uncomplemented variable and 't'o each complemented, variable. 1.5.2 Sum of Product (SOP) Form * The SOP expression usually takes the form of two or more variables ANDed together. Each product term may be minterm or implicant, = ABC+AB+ AC Y= aB+BE * This formis also called the “disjunctive normal form" + The SOP expression is used most often because it tends itself nicely to the development of truth tables and timing diagrams. + SOP circuits can also be constructed easily by using a special combinational logic gates called the ‘AND-OR-INVERTER’ gate. * SOP forms are used to write logical expression for the output becoming Logic ‘1 Input (3-Variables) | Output (Y) aleltec y o |o o [0 o [4 o|4 1 [0 1 [0 1 [4 0 ri 0 4 0 4 0 5 1 [4 Notation of SOP expression is, (A, B, C) = Em(3, 5.6, 7) my +m, +m, +m, also, Y= ABC+ ABC+ ABC + ABC 1.5.3, Product of Sum (POS) Form + The POS expression usually takes the form of two or more order variables within parentheses, ANDed with two or more such terms. Y=(A+B+0)-(BC+D) * This form is also called the “Conjunctive normal form”. + Each individual term in standard POS forms called Maxterm. * POS forms are used to write logical expression for output be coming Logic ‘0’ From the above truth table, we get FIA, B, C) = TIM(O, 1, 2, 4) Y= Myx M, x M, x My also Y= (A+ B+ Q(At B+ O)(A+ B+ (A+ B+ O)10 | Electrical Engineering UPPSC-AE MADE EASY Publieatone © Wealso conclude that From the above truth table, and {rom above equations it, Y= Em(3, 5, 6,7) then, Y= TIM, 1, 2,4) 1.5.4 Standard Sum of Product Form © _Inthis form the function is the sum of number of product terms where each product term contains all the variables of the function, either in complemented or uncomplemented form. * Itis also called canonical SOP form or expanded SOP form. + Thefunction [Y = A+ BG] canbe represented in canonical form as: Y= Ase = AB+B)(C+C)+ BCAA) = ABC + ABC + ABC + ABC + ABC + ABC Y= ABC + ABC + ABC + ABC + ABC 1.5.5 Standard Product of Sum Form * This form is also called canonical POS form or expanded POS form. ¥ =(8+0)-(A+B) Then, the canonical form of the given function Y= (B+C4 AA) (A+ B+ CC) = (B+C+A)(B+C+A)(A+B+C)(A+B+C) 1.5.6 Truth Table Form A tuth table is a tabular form representation of all possible combinations of given function Y =AB+BC Then, AlB[ClY ofofojojo tfolo 11 2fo[1ol4 spoltt|4 4[t[ojo/0 B(t[0/114 6[1[1/0/0 7{1]111/0 mus [7 Example-1.8 Simplify the expression for the following truth table. A Bly oj;o 1 oj;1io +[o|7 Lil tie} is equal to (a) A (b) A+B (ce) B (d) A+BMADE EASY Digital Electronics Boolean Algebra and Logic Gates 11 Publestions Solution :(e) = Y= AB+AB +Y-8 ms Example 1.10 Simplify the expression (A, 8) = TIM(1, 3) (a) A ) 6 (c) A+B () A+B Solution :(b) (yp = (01), = AB (SOP) = A+B (POS) Glo = (11)p= AB-(SOP)= A+B (POS) A,B) = (A+B)(A+B) = AB+AB-B 1.5.7 Dual Form © Dual form is used to convert positive logic to the negative logic and vice-versa * In positive logic system, higher voltage is taken as logic ‘1’ and in negative logic system, higher voltage is taken as logic ‘0’, For example. ()) For (positive) logie Logic't’ = ov, Logic '0' =-5 V (ii) For (negative) logic Logic't’ = -0.8V; Logic 0 =-1.7V 1.5.8 Venn Diagram Form ‘+ ABoolean algebra can be represented by a Venn diagram in which each vatiable is considered as a set ‘+ The AND operations considered as an intersection and the OR operation is considered as a union LAs (yet @y=o [EMI [77 Exampie-1.11 For the given Venn diagram the minimize the expression for the shade area is represented (a) AB+ BC+ AC (b) AB+BC+ AC (c) AB+BC+ AC (d) AB+BC+AC12 Electrical Engineering UPPSC-AE MADE EASY Publications Solution : (d) The shaded area includes ABC, ABC, ABC, ABC Y = ABC + ABC + ABC + ABC AB + AC(B +B) + BO(A+ A) = AB+ BC+ AC 1.6 Karnaugh Map ‘The *Karnaugh map' is a graphical method which provides a systematic method for simplifying and manipulating the Boolean expressions or to convert a truth table to its corresponding logic circuit in a simple, orderly process In this technique, the information contained in a truth table or available in SOP or POS form is represented on K-map. ‘Although this technique may be used for any number of variables, it is generally used up to 6-variables beyond which it becomes very cumbersome. Inn-variable K-map there are 2° cells, ‘Gray code” has been used for the identification of cells. 1.6.1 Two-variable K-Map 1.6.2 Three-variable K-map Four colls Four minterms (maxterms) 5 8 B B a + f e ¢ t . ° > 3 1 Amo) om | om anol % ast] om | om a1] m | om (For 50°) (For POS) Eight cells Eight minterms (maxterms) (ec (8c) (BC) (Bc) (8+0) (640) B+e) Bre) ac HS OS ecb R'E Soo at 10 Xoo or ss Rao] m | m | m | m amo] m | om | im | om Amt) ™ ms ™ ™ aw Ms, Me ‘For Som) (ForPos) 1.6.3 Four-variable K-map Sixteen cells Sixteen minterms (maxterms)MADE EASY Digital Electronics Boolean Algebra and Logic Gates Publications 13 GD) GD) co) cd) (c+D) (C40) G+d) +0) coe of Uf FE go i 000 10 p00 or ttt B= 00) m m | om tareye—o0] | m | me | me Foor) m | im | om | my (a+Bye— 01 mlm) om aB<— tt} ma] ma | ms | me vBye tt! Ma | Ms | Ma | Me x10; ™ | om | om | mo reo) Me | Mm | My | Me (FersoP) (For POS) 1.6.4 Complete Simplification Rules * Construct the K-map and place 1's in those cells corresponding to the 1's in the truth table, Place 0's in the other cells, * Examine the map for adjacent 1's and loop those 1’s which are not adjacentto any other 1's. These are called isolated 1's, * Next, look for those 1's which are adjacent to only one other 1, Loop any pair containing such a1 * Loop any octet even it contains some 1's that have already been looped. * Loop any quad that contains one or more 1's which have not already been looped, making sure to use the minimum number of loops. + Loop any pairs necessary to include any 1's that have not yet been looped, making sure to use the minimum number of loops. ‘+ Form the OR sum of all the terms generated by each loop. 1.6.5 Don’t Care Condition * Some logic circuits can be designed so that there are certain input combinations for which there are no specified output levels, usually because these input combinations will never occur. * So, acircuit designer is free to make the output for any “don't care" condition either a0 or 1 in order to produce the simplest output expression. ‘* The two conditions can be better understood by constructing the K:map for the given two conditions. (i) Interms of SOP and don't care conditions. MA, B, ©, D) = Em(1, 3,7, 11, 15) + (0, 2, 5) (ii) _Interms of POS and don't care conditions. HA, B, C, D) = TIM(4, 5, 6, 7, 8, 12). (1, 2,3, 9, 11,14) io a0 a © Be o\ or 0 fi) 38 00 Bro+0) o| x oo 0 ote x a " MB) x o x14 1.6.6 17 Electrical Engineering UPPSC-AE MADE EASY Implicants, Prime Implicants and Essential Prime Implicants Implicant: implicant is a product term on the given function for that combination the function output must bet Prime implicant: Prime implicants a smallest possible product term of the given function, removing any one of the literal from which is not possible. Essential Prime Implicant: Essential prime implicant is a prime implicant it must cover atleast one minterm, which is not covered by any other prime implicant. For the given K-map, find implicant, Prime Implicant and Essential Prime Implicant can be represented as 1c Py Here total number of 1 [err=a| implicant = 5 : implicant = (ABC), (ABO), (ABC), (ABC), (ABC) and Prime implicant = AB, AC, AB, BC and BAB Logic Gates Logic gates are the fundamental building blocks of any digital system. They are usually constructed in LSI and VLSI circuits along with other devices, he name logic gate is derived from the ability of such a device to make decisions, in the sense at, it produces outputs for different combinations of applied inputs. The inputs and outputs of logic gates can occur only in two levels as HIGH and LOW, MARK and SPACE, TRUE and FALSE, ON and OFF, or simply 1 and 0 he function of each logic gate will be represented by Boolean expression. Logic gates are classified as — Basic Gates NOT, AND, OR Universal Gate NAND, NOR Special purpose Gate EX-OR, EX-NOR A “truth table” is a means for describing how a logic citout's output depends on the logic levels present at circuit's input. The number of output combinations will be 2% for “N-input” truth tableMADE EASY Digital Electronics Boolean Algebra and Logic Gates 15 1.7.1 Basic Gates 1. The NOT Gate + The NOT gate has a single input variable and a single output variable + The NOT operation is also referred to as ‘INVERSION’ or ‘COMPLEMENTATION’ ‘© Thus, its output logic level is always opposite to the logic level of its input Input > (output = Aor A’ " r. np ; ‘Input (A) | Input (¥) Input (A) o | 4 The smal pbb atnays denotes the inversion i 2 Le Satna (1) ‘+The symbol of NOT operation is represented by — (bar) or (). Therefore, for input A the output of Ww the NOT gate is [Y ©The switching circuit and transistor circuit for a NOT gate are shown below. = When switch Ais open i.e. logic 0’ then, the bulb glows (shows logic 1’), = When switch is closed i.e. logic ‘1’ then, the bulb does not glow (shows logic 0’) ‘GND Similarly for transistor circuit when, A=0;T=08 o A=1;T=ONand ¥=GND * When even number of NOT gates/inverters are connected in feedback, it acts like a bistable multivibrator (basic memory element) as shown below. o 1 o * Even number of NOT gatesfinverters without feedback act like a butter as shown below. ° > 1 > ° ° ° Note: Buffers are used to increase the driving capacity of a gate.16 | Electrical Engineering UPPSC-AE MADE EASY + Odd number of NOT gatesiinverters connected in feedback act like an astable multivibrator or, a square wave generator, or a clock pulse generator ora free running oscillator. ° 1 o es 2 + Iftime taken by each gate to respond to the input ist, (propagation delay), hen, for astable muttivibrator, [T= 2% Nlpa where Propagation delay time of inverter = Time period of a square wave generator N= Number of inverters 7 Frequency of oscillation = and ‘quency 2Ning [EINE [77 txampie-1.12 For the given ring oscilator, the propagation delay of each inverters 100 pico sec. The fundamental frequency of the oscillator output is be pe bebe Perey, (a) 1GH2 (b) 2GHz (c) 3GHz (a) 4GHz Solution : (a) Here, N=5 (00 x 10" sec, fet et 2Ntpg 28x 100 x 10% =1GHz 2. The AND Gate +The AND gate can have two or more inputs but only one output. * The logic symbol and the truth table of a two input AND gate are, Taput | Output Ale| ¥ oo) a ° a 2e-D)-ev o| 0 Be ta] 4 + The logical expression is [Y= AB + tis clear from the truth table that, if all the inputs or any of the input is LOW (logic ‘0’) the output is also at logic ‘0’. However the output is 1 only when all the inputs are 1MADE EASY Digital Electronics Boolean Algebra and Logic Gates Publiestions + AND gate follows both commutative and associative law as aD 2 () Commutative law: AB= BA (i) Associative law: ABC = (AB)C = A(BC) o y- + Enable and disable inputs: For AND operations oy If control = 0, No change in the output, hence loy If control ‘0'is considered as disable input for AND gate. A | Control | ¥ 0 1 0 1 7 7 Due to change in the input output also changes therefore logie '1" is enable input for AND gate. ‘+The switching circuit diagram of AND gate is shown in the figure below. | ye ae ey=A8 v ‘Som | he bulb will glow only when both the switches A and Bare closed or at logic "1 + The AND operation is performed exactly ike ordinary multiplication of 1's and O's ‘+ In mult input AND gate, the unused input can be connected to (9 Logie 1’ or pull up (enable) (ii) One of the used input (iii) Leftopen tor TTL logic circuit ut of these three procedure the best way is to connec! the logic “1” or pul up. mes [7 Example- 1.13. Consider the logical functions given below. 1A. B,C) = B(2, 3, 4) > 1A, B, ©) = (0, 1, 3, 6,7) 6 If fis logic zero, then maximum number of possible minterms in function f, are (a) 3 (b) 4 (c) § () 618 Electrical Engineering UPPSC-AE MADE EASY Publleaons Solution : (d) 22,3, 4) n(0, 1,3, 6, 7) = 2(2, 4, 5); f,- f, = Zm(2, 4) Forfunction ftobe zero, (A, B.C) = [A BC) 0 HA BO] = 210. 1,3,5.6,7) Maximum minterms possible are 6. The OR Gate ‘+ The OR gate can have two or more inputs but only one output. The logic symbol and the truth table for OR gate are, Input [ Output] alel_y ofa] o ofa, 4 apo 4 wala * Thus, the logical expression is [Y=A+B ‘+ tis clear from the truth table that, if all the inputs or any of the input is high the output Yis HIGH. Where as if al the inputs are LOW then the output Yis low. = OR gate follows both commutative and associative laws as’ Ao @ Commutative law: A+ B= B+ A a (ii) Associative law: (A + B+ C) = (A+ B)+ C= A+ (B+ Q) o —T>-ev + Enable and disable inputs: For an OR gate 15 v 4 cof A | Control | ¥ o{ o [0 i 0 1 he change in the input causes the change in the output hence, for OR gate logic '0' Is an enable input For control = A | Control | ¥ 0 7 1 1 7 Due lo change in the input, oulput remains the same therefore for OR gate logic ‘1’ is a disable input