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Model VLSI Question Paper

This document appears to be an exam for a course on VLSI design. It contains 17 multiple choice questions testing various concepts related to latches, flip-flops, timing analysis, domino logic, sequential circuits, and power analysis. The questions reference different circuit diagrams and include calculations related to minimum output capacitance, clock frequency, timing violations, test patterns, power savings from voltage scaling, and leakage power.

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kumar_eee
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© Attribution Non-Commercial (BY-NC)
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307 views

Model VLSI Question Paper

This document appears to be an exam for a course on VLSI design. It contains 17 multiple choice questions testing various concepts related to latches, flip-flops, timing analysis, domino logic, sequential circuits, and power analysis. The questions reference different circuit diagrams and include calculations related to minimum output capacitance, clock frequency, timing violations, test patterns, power savings from voltage scaling, and leakage power.

Uploaded by

kumar_eee
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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1

EE82M, VLSI I J. Abraham


Fall 2009 Exam. II November 24, 2009

Name: Exam, Test

Check for 7 pages in the exam. Time limit: 80 minutes

Mark exactly one choice for each answer; multiple choices will be counted as an incorrect answer.

1. (2 points) Which of the following statements is not true?


a Latches generally consume more power than flip-flops.
b A D Flip-flop is made with two latches.
c Latches are level sensitive.
d Flip-flops are edge sensitive.
e Latches are transparent to either the 0 or 1 value of the clock (or enable signal).

2. (2 points) Mark one of the following statements which is not true?


a The hold time for a flip-flop can be a negative value.
b The clock-to-Q for a flip-flop can be a negative value.
c The setup time will be increased by delaying the D input to a flip-flop.
d The hold time will be decreased by delaying the D input to a flip-flop.
e The setup time for a flip-flop can be a negative value.

3. (2 points) what is the best solution to fix a hold time violation?


A. Use a different flop
B. Modify clock frequency
C. Increase supply voltage
D. Insert delay elements in the offending path
E. Replace logic gates in the offending path with those in Low-VT H library
a B, C
b A, D
c B, D
d D, E
e A, B
2

The following two questions are based on Figure 1 and the following parameters.
All intermediate node capacitances, CP =0.3pF.
For the static inverter, Vth =1V.
For all supply voltages, VDD =4V.

Figure 1: Domino circuit

4. (8 points) Find the minimum output capacitance, COU T , such that the domino circuit will
work correctly for all input combinations.
a 0.2pF
b 0.3pF
c 0.4pF
d 0.5pF
e 0.1pF

5. (8 points) With what input sequence would the worst case charge sharing happen?
(A,B,C,D) → (A,B,C,D)
a (0,1,1,0) → (1,1,1,1)
b (0,1,1,0) → (1,1,0,0)
c (1,1,1,1) → (1,1,0,0)
d (1,1,1,1) → (1,0,1,1)
e (0,1,1,0) → (1,1,0,1)
3

The following three questions are based on Figure 2; the delays of the gates are indicated on
the schematic.

Figure 2: D Flip-flop

6. (8 points) What is the setup time?


a 50 ps
b 75 ps
c 100 ps
d 125 ps
e 0 ps

7. (8 points) In the above circuit, what is the hold time?


a 25 ps
b 50 ps
c 100 ps
d 125 ps
e 0 ps

8. (8 points) In the above circuit, what is the clock-to-Q delay?


a 125 ps
b 150 ps
c 200 ps
d 250 ps
e 75 ps
4

9. (8 points) What is the highest frequency at which the following circuit (Figure 3) will operate
correctly? The parameters of the components are as follows.
Inverter: tpd = 100ps, tcd = 50ps
NAND gate: tpd = 160ps, tcd = 140ps
DFF: tpd = 150ps, tcd = 100ps, Setup time = 100ps

Figure 3: Sequential circuit 1.

a 1.96 GHz
b 2.00 GHz
c 2.27 GHz
d 2.50 GHz
e 1.82 GHz

10. (8 points) What is the limit on the hold time of the flops at the frequency of the circuit in
Figure 3? Hold time should be less than
a 250 ps
b 290 ps
c 340 ps
d 400 ps
e 230 ps
5

11. (8 points) The sequential circuit in Figure 4 has a timing violation. Find the solution to fix the
timing violation based on the following information. Initially, there is no delay for the blocks
“a”,“b”,“c”.
tc (clock period) = 700ps
tpcq (CLK to Q) = 150ps
tpd (LogicA) = 500ps
tpd (LogicB) = 300ps
tsetup = 150ps
tpd (inverter) = 50ps

Figure 4: Sequential circuit 2

a Insert four inverters in “b”


b Insert four inverters in “c”
c Insert two inverters in “a”
d Insert two inverters in “b”
e Insert four inverters in “a”

12. (2 points) Which of the following techniques is true for reducing charge sharing in a domino
circuit? Select the best answer.
a Precharge the internal nodes of the n-channel stack
b Arrange the transistors in the n-channel stack to reduce the diffusion capacitance
c Only (b) and (c)
d All of the above
e Size down keeper device
6

13. (8 points) What is a test for the line labeled H stuck-at 0 in Figure 5?

Figure 5: Circuit under test

a None of the above


b ABCDEF = 011010
c ABCDEF = 000010
d ABCDEF = 000111
e ABCDEF = 000011

14. (2 points) In a DSP system, assume that dynamic voltage scaling is employed to reduce power
of the system; the supply voltage is decreased from 5V to 4V. What percentage of dynamic
power can we save? (Assume all other parameters are kept constant.)
a 36%
b 20%
c 10%
d Power is unchanged
e 18%

15. (2 points) In the above question, What percentage of energy can we save?
a 36%
b 20%
c 10%
d Energy is unchanged
e 18%
7

The following description is pertinent to the next two questions.


An embedded hardware accelerator in a system-on-chip is designed in a 1V, 65nm process
with a gate capacitance of 2f F/µm. The logic functions require 1 million logic gates with an
average width of 0.5µm. The gates have an activity factor of 0.1. The embedded memory has
transistors with a total width of 6µm/byte, and the memory has an activity factor of 0.05.
The unit needs to be clocked at 100MHz to keep up with the input data rate.

16. (8 points) What is the maximum embedded memory (in MBytes) that can be included in the
design if the total dynamic power is to be kept at or below 100mW?
a 1.6 MBytes
b 1.3 MBytes
c 1.2 MBytes
d 1.5 MBytes
e 1.4 MBytes

17. (8 points) If the subthreshold leakage is 20nA/µm, the gate leakage is 2nA/µm, and if half
the transistors are on (on average), what is the leakage power for a design with 1 MByte of
memory?
a 82 mW
b 72 mW
c 78 mW
d 75 mW
e 80 mW

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