Microelectronics and Microsystems - BMEVIEED071

Lecturer:
Dr. Zólomy Imre

Prepared by:
Ahmad Halal Ftesah Alshahmani
&
Salam Abd Al-Ameer Waheed AL-abassi
&
Ahmed I. M. Alnahhal
&
Mustafa Safaa Hussein Shubbar

Department of Electron Devices

Faculty of Electrical Engineering and Informatics Budapest
University of Technology and Economics
 Solution of Exam questions 2020/21 2. Semester

1. Structures of the resistors in the integrated circuits realized by

base and emitter diffusions and their properties.
Ans: Diffused Resistor: The diffused resistor is formed in any one of the isolated regions of
epitaxial layer during base or emitter diffusion processes. This type of resistor fabrication is very
economical because it is obtained by diffusing thin layer of p- or n-type impurity into a substrate
of the opposite type of material.
Structures: The N-type emitter diffusion and P-type base diffusion.
limitation of diffused resistor: only small valued resistors can be fabricated and the surface
geometry such as the length, width and the diffused impurity profile determine the resistance
value. For higher values of resistance, the diffusion region can be formed in a zig-zag fashion
resulting in larger effective length.

2. Definition of the sheet resistance and its determination in the case

of inhomogeneous doping concentration.
Ans: Sheet resistance: (also known as surface resistance or surface resistivity) is a common
electrical property used to characterize thin films of conducting and semiconducting materials. It
is a measure of the lateral resistance through a thin square of material, i.e. the resistance between
opposite sides of a square. 

Sheet resistance (RS) is commonly defined as the resistivity (ρ) of a material divided by its
thickness (t). The units of this equation resolve to ohms (Ω); however, it represents the resistance
between opposite sides of a square of a material. As such the units Ω/□ (ohms per square) are
commonly used. The quantity ρ/t has units of resistance. It noticed that it is a property of the
layer (doping and thickness).
In case of inhomogeneous doping profile Things become a bit more complicated when the
doping is not uniform. Since doping depends on depth, then resistivity depends on depth.
since mobility depends on doping concentration, then mobility is also an implicit function of x.
When current flows through this non-uniform layer, the carriers distribute themselves according
to the local resistivity, with the effects being averaged over the thickness of the layer. More
current flows in heavily doped regions; less current in lightly doped areas. As a first step in
seeing how to handle non-uniform doping, consider simple two-layer structure. Each layer is
uniformly doped.
The two resistors are in parallel.

We now have a path to finding the sheet resistance of a non-uniform doping profile. By
conceptually breaking the profile into many small slices of thickness ∆x, and treating each slice
as having uniform doping. This is just a discrete representation of a “sheet-resistance integral”:

This is not an easy computation because of the mobility variation. Generally, it requires
numerical integration.

3. Lay-out of long resistors, the meander. Determination of the

resistance of the curve.
Ans: Depending on this formula , it is possible to design long resistors as
following:

1- The quantity L/W is the number of "squares" that a resistor has, and total resistance
is proportional to number of squares. In the figure below, we see a resistor with six
squares (the light blue represents resistor material). If the sheet resistivity of the thin-
film resistor is 50 ohms/square, we are looking at a 300-ohm resistor.
 2- Meandering resistor, the squares at each bend should be counted about 1/2
square. In the figure below.
Example: if it is counted all the resistor squares, it is 43. But when measure the
resistor, it will behave like it has only 40 squares. That is because you need to
reduce the corner squares by 56%.

corner = 0.56 squares

4. The effect of stray capacitances, the cut-off frequency of the

integrated resistors.
Ans: Stray capacitance is unintended and unwanted capacitance in a circuit.
Capacitance doesn't exist only within capacitors. In fact, any two surfaces at different
electric potential, and that are close enough together to generate an electric field have
capacitance. This unintended capacitance is referred to as stray capacitance, and it can
result in a disruption of normal current flow within a circuit.
Designers of circuits try to minimize stray capacitance as much as possible. They do
this by keeping the leads of electronic components very short and grouping components
in such a way to eliminate capacitive coupling.
In Integrated circuit many different types of stray capacitance appear for example: there
are two types of parasitic capacitances, the MOS overlap and the junction depletion
capacitance. The first one (gate to drain and gate to source), can couple a signal from
one terminal to the other causing large problems regarding signal distortion as well as
speed losses. The second one (well to well or well to substrate), can result in speed
reduction of a circuit.
Although diffused resistors were historically widely used for IC design, poly resistors are
often commonly used today. Figure below shows the basic structure of a poly resistor.
Because the resistor body is not formed in a well or substrate region of the silicon, there
is no junction depletion effect. This makes poly resistors generally more linear than
diffused resistors. In addition, because they are formed on top of a thick oxide layer the
parasitic capacitance is lower than for diffused resistors, and multiple implants can be
used not just to tailor the sheet resistance of the poly film but also to adjust its
temperature coefficient; poly resistors can therefore have much lower variation over
temperature than diffused resistors

the actual number of sections needed to ensure a specified accuracy up to a given

frequency for small-signal modeling depends on the length of the resistor. The models
are therefore implemented using a single element for the body of the resistor and the
contact and end resistances, which are depicted as separate elements. For accurate
modeling up to a frequency f

sections are needed, where CA is the parasitic capacitance per unit area. The internal
end-plus-contact resistances are then set to zero when the NS sections are connected
in series.
5. Design of the resistors at low and at high dissipations.
Ans: the power dissipation is the process by which an electronic or electrical device
produces heat (energy loss or waste) due to the drop voltage on the resistors. To
control this dissipation, it must be controlled the value of resistors:
To calculate the power dissipated by the resistor, the formulas are as follows:
P (power dissipated) = I2 (current) × R (resistance)
or
P (power dissipated) = V2 (voltage) ÷ R (resistance)

In integrated circuit, it is possible to increase the value of the resistor causes decreasing
in value of current and the resistor’s power dissipation will decrease as well and vice
versa.
6. Band diagram of the polysilicon layer. Dependance of the potential
barrier at the grain boundaries upon the doping concentration.
(Qualitatively).
Ans: The band gap of polysilicon is the same of the normal silicon, but the Fermi level
is close to conductive level while the Fermi level is near to valence level in silicon as
shown in figure below:
The grain boundary energy states located higher than the intrinsic Fermi level give
greater values of grain boundary potential barrier height for a p-type semiconductor and
the reverse applies to an n-type semiconductor. Further a wider energy distribution of
these states gives rise to a towering of the potential barrier height at the grain boundary.

7. Dependance of the resistivity of the polysilicon layer upon the

doping concentration. (Qualitatively)

Ans: The electrical resistivity of polycrystalline silicon films has been studied as a
function of doping concentration and heat treatment. The films were grown by the
chemical vapor decomposition of silane on oxidized silicon wafers. The resistivity of the
as-deposited films was widely scattered but independent of dopant atom concentration
at the lightly doped levels and was strong function of dopant level in the more heavily
doped regions. Postdeposition heat treatments in an oxidizing atmosphere remove
scatter in the data. The resultant resistivity for dopant levels less than 10 16 atoms/cm3
was approximately equal to that of intrinsic silicon. In the next 2 orders of magnitude
increase in dopant level, the resistivity dropped 6 orders of magnitude.
8. Integrated capacitances. Depletion layer and oxide capacitances
and their properties.
Ans: There are different kind of capacitors that could be integrated on-chip:
 MIM Capacitor (Metal-Insulator-Metal)
 MOM-Capacitors (Metal-Oxide-Metal)
 MOS Capacitor
 Metal Fringe Capacitors
 Trench Capacitors
 Junction Capacitance
The MOS structure is treated as consisting of a series connection of two capacitors: the
capacitance of the oxide and the capacitance of the depletion layer. There are three cases in this
structure which are:
 In accumulation there is no depletion layer. The remaining capacitor is the oxide
capacitance, so that the capacitance equals:

 In depletion the MOS capacitance is obtained from the series connection of the oxide
capacitance and the capacitance of the depletion layer:

 In inversion the capacitance becomes independent of the gate voltage. The low
frequency capacitance equals the oxide capacitance since charge is added to and from
the inversion layer in a low frequency measurement. The high frequency capacitance is
obtained from the series connection of the oxide capacitance and the capacitance of the
depletion layer having its maximum width, xd, max. The capacitances are given by:

 Capacitance varies inversely as thickness

9. Cut-off frequencies of the capacitances. Methods for reducing the
series resistance of the capacitances.
Ans:

10. Capacitances of the DRAMs. Stacked and trench capacitances.

Ans: DRAM: is a type of random-access semiconductor memory that
stores each bit of data in a memory cell consisting of a tiny capacitor and
a transistor, both typically based on metal-oxide-semiconductor (MOS)
technology. The capacitor can either be charged or discharged; these
two states are taken to represent the two values of a bit, conventionally
called 0 and 1.

Types of capacitances used in DRAM:

 the capacitors in DRAM cells were co-planar with the access
transistor (they were constructed on the surface of the substrate); thus, they were
referred to as planar capacitors.
 DRAM cells featuring capacitors above the substrate are referred to as stacked or folded
plate capacitors
 capacitors buried beneath the substrate surface are referred to as trench capacitors.
In trench cell, the storage node is in a trench etched in the substrate. Its most important
advantages come upon the possibility to use conventional contacts, interconnections and active
device processing, because the storage capacitor is formed before these elements. But, they pose
great challenges, as well: the etching in silicon of deep trenches with high aspect ratio and the
formation of an uniform and reliable dielectric film (inside the trench). Consequently, in the
development of this cells accurate etching and deposition tools are necessary.
•Si area reduction of trench vs. planar capacitor ~ factor of 18
•4um deep trench, surface 0.87um x 2.4um, capacitance of 40fF
•trench like STI except:
•thin ox required •polysilicon fill
•sidewall doping
•Issues
•corner rounding, bottom uniformity
The other mainstream DRAM family is the stacked capacitor cell. In this cell the storage
capacitor is above the read/write transistor, which reduces the area available for interconnect
routing. This and the large height difference between the memory cell array and the
surrounding peripheral circuits make wiring delineation difficult and unreliable. To reduce these
problems, high-  dielectrics (e.g., Ta2O5, BST) and exotic topographies (to increase the effective
plate area) are necessary to reduce the storage capacitor's volume to a minimum.
11. Integrated inductors. Cut-off frequency, structures.
Ans:

12. Interconnections in integrated circuits. Diffused interconnections,

polysilicon, and metal interconnections.
Ans: Diffused interconnections: Diffused conductors with low sheet resistances
represent the second available interconnect medium in basic IC technology. The minimum
resistivity is approximately 1,000u ohm-cm. For shallow structures measuring about 1 um, the
minimum obtainable sheet resistance is typically between 10 and 20 ohms per square. Such
sheet resistances are obviously much higher than that of metal, and one must be selective in
the use of diffusions for signal or power distribution. The diffused line must really be modeled
as a distributed RC structure, as illustrated in Figure below, when signal propagation is
considered. The resistance, R, of diffused regions and C represents capacitance of the reverse-
biased pn junction formed between the diffused region and the substrate Heavily doped
diffusions are normally used for interconnection purposes and can be approximated by a one-
sided step junction in which the depletion layer extends pre- dominantly into the substrate. The
capacitance per unit area is given by:

POLYSILICON INTERCONNECTIONS: Heavily doped n-type polysilicon is the primary

MOS transistor gate material in use today, and it provides an additional layer of interconnection
that is easily insulated from other layers by thermal oxidation or insulator deposition. This extra
level of interconnection greatly facilitates the layout of compact digital integrated circuits. Thin,
heavily doped polysilicon layers have a minimum resistivity of approximately 300u ohm-cm, and
they suffer from the same sheet-resistance problems associated with shallow diffused
interconnections (typically 20 to 30 ohms per square). Polysilicon lines have substantial
capacitance to the substrate and exhibit RC delay problems similar to those of diffused
interconnections.
Metal interconnections: The requirement for low-resistivity materials leads one
immediately to consider metals for use as interconnections, and the resistivities of common
metals are compared in Table 7.1. Historically, aluminum and gold have been used with silicon
IC processing. Gold requires the use of a multilayer sandwich involving other metals such as
titanium or tungsten. Gold can be troublesome because it is a rapid diffuser in silicon and
produces deep-level recombination centers in silicon that tend to significantly reduce the
lifetime of free carriers. In addition, gold forms many problematic intermetallic compounds.
Because of these various problems, the use of gold is most often restricted to chip packaging
technologies. Aluminum is compatible with silicon IC processing and is the most common
material in use today. It is relatively inexpensive, adheres well to silicon dioxide, and has a bulk
resistivity of 2.7u ohm-cm. However, care must be exercised to avoid several problems
associated with the formation of good aluminum contacts to silicon. Advanced multilevel
metallization systems employ copper, because of its improved resistivity relative to aluminum.
Copper has an even larger diffusion coefficient in silicon than gold and causes lifetime reduction
and leakage in silicon. Therefore, copper is generally not introduced into the fabrication
sequence until one or two levels of aluminum metallization and interlevel dielectric levels have
been formed above the semiconductor devices. These metallization and dielectric layers act as
passivation layers to protect the active devices below.

13. Calculation of the delay time caused by the interconnection.

Ans: To calculate the wire delay or interconnect delay different models are available. The
different delay models available are:
• Lumped RC Model
• Distributed RC Model
• Elmore Model
Lumped RC Model: When the physical dimension of an interconnect is much smaller
than the wavelength of the signal passing through the interconnect, the
interconnect can be treated as a lumped element and represented by a low-pass RC
network,

The output voltage to a step voltage input of amplitude Vm is given by

vo(t) = Vm[1 − e-t/τ],where τ = 1/RC

Propagation delay (tp) - the time delay from vo = 0 to vo(tp) = 1/2Vm.

0.5 = 1 − e−tp/τ we arrive at tp = 0.69τ.

Distributed RC Model: When the physical dimension of an interconnect is

comparable to the wavelength of the signal passing through the interconnect, the
interconnect cannot be treated as a lumper element. Instead, it must be treated as a
distributed element, as shown in Figure below where R is the resistance per unit
length and C is the capacitance per unit length. Note that the number of distributed
elements N should be such that Δ L =L/N is sufficiently small as compared with
the
wavelength of the signal
Applying KCL at node i,
(vi − vi−1)/R(ΔL) + (vi − vi+1)/R(ΔL) + C(ΔL)dvi/dt= 0
from which we obtain
RCdvi/dt ={ (vi+1 − vi) − (vi − vi−1)}/(ΔL)2 .

Elmore Model: Interconnects are represented by distributed RC networks, where R

and C are resistance and capacitance per unit length, respectively.

τN =1/2RCL2(1 +N).
14. Effect of the scaling on the delay time caused by the
interconnections.
Ans: It is obvious that the rise time τL is heavily dependent upon various dimensions involved
in a chip, i.e., L, W, H, XOX, and Ls.

Therefore, to obtain more information about τ L, first we have to relate the above dimensions to
various elements of the VLSI technology.
The area occupied by an MOS transistor can be made smaller by shortening its channel width
and length leading to a faster device. Substrate doping plus the junction built-in potential
determine the minimum depletion-region thickness of an operable device which, in turn,
establishes the minimum device size.
the average feature size drops by a scaling factor of 1/S, device performance is enhanced; as
gate delay is reduced by a factor of 1/S, and power dissipation/device by a factor of 1/S 2, more
devices can be packed on a chip. Increasing these components raises the number of
connections required for signal transmission. To clarify the problem of interconnections, the
following terms are defined. A “block graph” is a structure consisting of interconnected blocks;
a logic design is an example. A “block” is an undefined primitive. In a logic design, for example,
it can be a NOR circuit, a storage element, register, or an IC chip.
After scaling, the line response time remains constant and the line voltage drop stays the same;
however, current density increases which can introduce severe device-performance problems,
such as electromigration. The total delay time of a scaled block graph is a function of gate delay
only because the scaling rule dictates the gate-delay reduction (by a factor of 1/S) with a
constant line response time. Because of the short lines in a scaled block graph, gate delay is
typically one order of magnitude higher than the local line response

15. Multi-layer interconnection. The Damascene interconnection

scheme.
Ans: The damascene multilayer interconnect integration technology is an important
interconnect technology for achieving large-scale integration and high speed in ultra-large-scale
integrated circuits (ULSI) at low cost.

16. Isolators with low permittivity.

Ans: Future integrated circuits and packages will require extraordinary dielectric materials
for interconnects to allow transistor advances to be translated into system-level advances.
Exceedingly low-permittivity and low-loss materials are required at every level of the
electronic system, from chip-level insulators to packages and printed wiring boards.
The future advancement in speed and performance of ICs is critically dependent on
improvements in dielectric materials. The high data rate for future electronic systems
requires that the dielectric constant (both permittivity and loss) be reduced to levels not
possible today. Reduction in the permittivity is required for on-chip and short, off-chip wires.
The dielectric loss is becoming increasingly important because the aggregate bandwidth for
chip-to-chip communications depends on low-loss pathways. The interconnect, like all
electronic functions, has entered a power limited regime. That is, signals must be transmitted
at ever lower voltage to conserve energy. This places even greater demands on the quality of
interconnect pathways and increases the need to reduce the capacitive charging of wires.
Advancements in dielectric materials have not kept up with needs and expectations because
of the difficulty in producing and integrating advanced materials. The required drop in
dielectric constant for chips and packages does not appear achievable with materials
manufactured today. Polymeric materials offer many advantages, but their mechanical
properties are so dissimilar to those of silicon and copper that their use is constrained. The
lack of obvious answers may cause further delays in the scheduled implementation of low-k
solutions. In the long term, only air (or another gas) by itself or as part of highly porous
composites can meet ultralow dielectric constant needs. The integration of revolutionary
dielectrics, such as polymers or highly porous insulators, has been most difficult. In sum,
many challenges exist in discovering, manufacturing, and integrating next-generation
dielectric solutions.