Scribd
Upload
100 views

Lab 12 BCD Adder & Sequential Circuit Using SR, D and JK Flip-Flop

This document describes a lab experiment on binary coded decimal (BCD) adders and sequential circuits using SR, D, and JK flip-flops. The objectives are to study flip-flop concepts and implement various flip-flop circuits using NOR and NAND gates. Tasks include designing a 4-bit BCD adder, developing SR latches, and drawing circuit diagrams and characteristic tables for SR, D, JK, and T flip-flops to analyze their behavior. Circuit simulations will verify the flip-flop designs match their characteristic tables.

Uploaded by

Faseeh Mazhar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
100 views

Lab 12 BCD Adder & Sequential Circuit Using SR, D and JK Flip-Flop

This document describes a lab experiment on binary coded decimal (BCD) adders and sequential circuits using SR, D, and JK flip-flops. The objectives are to study flip-flop concepts and implement various flip-flop circuits using NOR and NAND gates. Tasks include designing a 4-bit BCD adder, developing SR latches, and drawing circuit diagrams and characteristic tables for SR, D, JK, and T flip-flops to analyze their behavior. Circuit simulations will verify the flip-flop designs match their characteristic tables.

Uploaded by

Faseeh Mazhar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Lab 12

BCD Adder & Sequential Circuit using SR, D and JK


Flip-Flop
Name.
Reg. No.

Description:

BCD adder using parallel adder


BCD adder can be designed using parallel adders or full adders. Four bit BCD adder is
shown in figure below.
Combinational circuits and systems produce an output based on input variables only.
Sequential circuits use current input variables and previous input variables by storing the
information and putting back into the circuit on the next clock (activation) cycle. A sequential
circuit is illustrated in Fig. 1.

Input Output
Combinational
circuit

Memory
Element

Figure 1. Sequential circuit

The block diagram demonstrates that the outputs in a sequential circuit are a function not only of
the inputs, but also of the present state of the storage elements. The next state of the storage
elements is also a function of external inputs and the present state. Thus, a sequential circuit is
specified by a time sequence of inputs, outputs, and internal states. In contrast, the outputs of
combinational logic depend only on the present values of the inputs.

Flip flop (combinational component) is a synchronous bi-stable device. The functionality of the
flip flops are similar to latches. However, the main difference between them is in the method
used for changing their state. The output of the flip flop changes only at a specified point on a
triggering input called clock (CLK) which is designated as a control input, C. This momentary
change in the control input C is called a trigger and the transition it causes is said to trigger the
flip-flop.

Objectives:
 To study the concept of flip flop SR, D and JK
 To develop flip flop using NOR and NAND gate
 To understand and verify the behavior of the flip flop
 To implement SR, D and JK Flip-Flop on Circuit Maker as well as on Explorer Board

LAB TASK#1:

Design Truth Table for BCD Adder

Decimal Binary Sum BCD Sum


K Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Design a BCD adder using 4-bit binary adder.

Circuit Maker Implementation

LAB TASK#2:
a) Develop circuit diagram of SR latch using NOR gates on circuit maker.
b) Fill a truth table below for developed SR latch in part (a)

S R Q Q́

LAB TASK#3:
a) Develop circuit diagram of SR latch using NAND gates on circuit maker.
b) Fill a truth table below for developed SR latch in part (a)
S R Q Q́
0 0
0 1
1 0
1 1

LAB TASK#4:
a) Draw the graphic symbol (block diagram) of SR Flip Flop on page. Mention/label all
inputs and output clearly.
b) Draw the characteristic table.
c) Draw circuit diagram of SR Flip-flop on circuit maker and verify from Characteristic
Table.
d) Find Q(t+1) equation by using K-Map and Grouping Technique.

LAB TASK#5:
a) Draw the graphic symbol (block diagram) of D Flip Flop on page. Mention/label all
inputs and output clearly.
b) Draw the characteristic table.
c) Draw circuit diagram of D Flip-flop on circuit maker and verify from Characteristic
Table.
d) Find Q(t+1) equation by using K-Map and Grouping Technique.

LAB TASK#6:
a) Draw the graphic symbol (block diagram) of JK Flip Flop on page. Mention/label all
inputs and output clearly.
b) Draw the characteristic table.
c) Draw circuit diagram of JK Flip-flop on circuit maker and verify from Characteristic
Table.
d) Find Q(t+1) equation by using K-Map and Grouping Technique.

LAB TASK#7:
a) Draw the graphic symbol (block diagram) of T Flip Flop on page. Mention/label all
inputs and output clearly.
b) Draw the characteristic table.
c) Draw circuit diagram of T Flip-flop on circuit maker and verify from Characteristic
Table.
d) Find Q(t+1) equation by using K-Map and Grouping Technique.

You might also like