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Long-Channel I-V Characteristics: Chapter 2 MOS Transistor Theory

The document summarizes the operation modes of nMOS and pMOS transistors. It explains that nMOS transistors have three operation modes - cutoff, linear, and saturation depending on the gate-source voltage Vgs and drain-source voltage Vds. It also explains that pMOS transistors operate in the opposite way, with holes as the majority carriers instead of electrons. The document then discusses transistor capacitances and introduces models to understand transistor behavior both qualitatively and quantitatively.

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Carlos Saavedra
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513 views

Long-Channel I-V Characteristics: Chapter 2 MOS Transistor Theory

The document summarizes the operation modes of nMOS and pMOS transistors. It explains that nMOS transistors have three operation modes - cutoff, linear, and saturation depending on the gate-source voltage Vgs and drain-source voltage Vds. It also explains that pMOS transistors operate in the opposite way, with holes as the majority carriers instead of electrons. The document then discusses transistor capacitances and introduces models to understand transistor behavior both qualitatively and quantitatively.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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64 Chapter 2 MOS Transistor Theory

Gate In summary, the nMOS transistor has three modes of operation. If


Vgs < Vt , the transistor is cutoff (OFF). If Vgs > Vt , the transistor turns ON. If Vds
Source Drain is small, the transistor acts as a linear resistor in which the current flow is pro-
portional to Vds. If Vgs > Vt and Vds is large, the transistor acts as a current source
p+ p+ in which the current flow becomes independent of Vds .
The pMOS transistor in Figure 2.4 operates in just the opposite fashion.
n-type Body
The n-type body is tied to a high potential so the junctions with the p-type
source and drain are normally reverse-biased. When the gate is also at a high
Body (usually VDD) potential, no current flows between drain and source. When the gate voltage is
FIGURE 2.4 pMOS transistor lowered by a threshold Vt , holes are attracted to form a p-type channel imme-
diately beneath the gate, allowing current to flow between drain and source.
The threshold voltages of the two types of transistors are not necessarily equal, so we use
the terms Vtn and Vtp to distinguish the nMOS and pMOS thresholds.
Although MOS transistors are symmetrical, by convention we say that majority carri-
ers flow from their source to their drain. Because electrons are negatively charged, the
source of an nMOS transistor is the more negative of the two terminals. Holes are posi-
tively charged so the source of a pMOS transistor is the more positive of the two termi-
nals. In static CMOS gates, the source is the terminal closer to the supply rail and the
drain is the terminal closer to the output.
We begin in Section 2.2 by deriving an ideal model relating current and voltage (I-V)
for a transistor. The delay of MOS circuits is determined by the time required for this cur-
rent to charge or discharge the capacitance of the circuits. Section 2.3 investigates transis-
tor capacitances. The gate of an MOS transistor is inherently a good capacitor with a thin
dielectric; indeed, its capacitance is responsible for attracting carriers to the channel and
thus for the operation of the device. The p–n junctions from source or drain to the body
contribute additional parasitic capacitance. The capacitance of wires interconnecting the
transistors is also important and will be explored in Section 6.2.2.
This idealized I-V model provides a general qualitative understanding of transistor
behavior but is of limited quantitative value. On the one hand, it neglects too many effects
that are important in transistors with short channel lengths L. Therefore, the model is not
sufficient to calculate current accurately. Circuit simulators based on SPICE [Nagel75]
use models such as BSIM that capture transistor behavior quite thoroughly but require
entire books to fully describe [Cheng99]. Chapter 8 discusses simulation with SPICE.
The most important effects seen in these simulations that impact digital circuit designers
are examined in Section 2.4. On the other hand, the idealized I-V model is still too com-
plicated to use in back-of-the-envelope calculations tuning the performance of large cir-
cuits. Therefore, we will develop even simpler models for performance estimation in
Chapter 4.
Section 2.5 wraps up this chapter by applying the I-V models to understand the DC
transfer characteristics of CMOS gates and pass transistors.

2.2 Long-Channel I-V Characteristics


As stated previously, MOS transistors have three regions of operation:
 Cutoff or subthreshold region
 Linear region
 Saturation region

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