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Cmos Vlsi Design 185

This document discusses delay in logic gates and ring oscillators. It provides examples of estimating delay for a fanout-of-4 inverter and calculating the frequency of a ring oscillator. Specifically, it estimates the delay of a FO4 inverter in a 65nm process to be 15ps. It also notes that FO4 delay can be used to estimate delay across different processes and is typically quoted under worst-case conditions. Finally, it sets up calculating the frequency of a ring oscillator by noting each inverter has a delay of 2 in a simple model.

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Carlos Saavedra
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42 views

Cmos Vlsi Design 185

This document discusses delay in logic gates and ring oscillators. It provides examples of estimating delay for a fanout-of-4 inverter and calculating the frequency of a ring oscillator. Specifically, it estimates the delay of a FO4 inverter in a 65nm process to be 15ps. It also notes that FO4 delay can be used to estimate delay across different processes and is typically quoted under worst-case conditions. Finally, it sets up calculating the frequency of a ring oscillator by noting each inverter has a delay of 2 in a simple model.

Uploaded by

Carlos Saavedra
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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158 Chapter 4 Delay

This delay grows quadratically with the number of series transistors n, indicating that
beyond a certain point it is faster to split a large gate into a cascade of two smaller gates.
We will see in Section 4.4.6.5 that the coefficient of the n2 term tends to be even larger in
real circuits than in this simple model because of gate-source capacitance. In practice, it is
rarely advisable to construct a gate with more than four or possibly five series transistors.
When building large fan-in gates, trees of NAND gates are better than NOR gates
because the NANDs have lower logical effort.

4.4.3 Delay in a Logic Gate


Consider two examples of applying the linear delay model to logic gates.

Example 4.10
Use the linear delay model to estimate the delay of the fanout-of-4 (FO4) inverter from
Example 4.6. Assume the inverter is constructed in a 65 nm process with Y = 3 ps.
SOLUTION: The logical effort of the inverter is g = 1, by definition. The electrical effort is
4 because the load is four gates of equal size. The parasitic delay of an inverter is
pinv ~ 1. The total delay is d = gh + p = 1 × 4 + 1 = 5 in normalized terms, or tpd = 15 ps
in absolute terms.
Often path delays are expressed in terms of FO4 inverter delays. While not all
designers are familiar with the Y notation, most experienced designers do know the
delay of a fanout-of-4 inverter in the process in which they are working. Y can be esti-
mated as 0.2 FO4 inverter delays. Even if the ratio of diffusion capacitance to gate
capacitance changes so pinv = 0.8 or 1.2 rather than 1, the FO4 inverter delay only var-
ies from 4.8 to 5.2. Hence, the delay of a gate-dominated logic block expressed in terms
of FO4 inverters remains relatively constant from one process to another even if the
diffusion capacitance does not.

As a rough rule of thumb, the FO4 delay for a process (in picoseconds) is 1/3 to 1/2 of
the drawn channel length (in nanometers). For example, a 65 nm process with a 50 nm
channel length may have an FO4 delay of 16–25 ps. Delay is highly sensitive to process,
voltage, and temperature variations, as will be examined in Section 7.2. The FO4 delay is
usually quoted assuming typical process parameters and worst-case environment (low
power supply voltage and high temperature).

Example 4.11
A ring oscillator is constructed from an odd number of inverters, as shown in Figure
4.24. Estimate the frequency of an N-stage ring oscillator.

FIGURE 4.24 Ring oscillator

SOLUTION: The logical effort of the inverter is g = 1, by definition. The electrical effort
of each inverter is also 1 because it drives a single identical load. The parasitic delay is
also 1. The delay of each stage is d = gh + p = 1 × 1 + 1 = 2. An N-stage ring oscillator

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