Systematic Design for a Successive

Approximation ADC
Mootaz M. ALLAM

M.Sc– Cairo University - Egypt

Supervisors
Prof. Amr Badawi
Dr. Mohamed Dessouky
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Outline

• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
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The Successive Approximation ADC

« The Return»

Moderate Low Minimum

Resolution Reconfigurable
Power Active blocs

• Emerging new Applications

▫ MEMS Sensor Interface:
Resolution: 7-8 bits, BW=50kHz [Scott 2003]
▫ Multi-standards RF receiver
Resolution: 8 bits, BW = 20 MHz [Montaudon 2008]
▫ Ultra Wide Band (wireless UWB):
Resolution: 5-6 bits, BW=300MHz [Chen 2006]
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Figure of Merit

P
FOM  Resolution
2 *2* BW
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Objectives
▫ Develop a systematic design method for successive approximation ADC
from system to layout level .

▫ Develop a general simulation environment with different levels of

abstraction and programmed performance analysis.

▫ Emphasis on analog design automation and reuse techniques:

 Automatic sizing
 Layout generation

▫ Optimizing Layout for best matching

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Principle of Operation
Comp 0
LSB0
1 1
MSB

V REF V V V
Vin  b1  b2 REF  b3 REF  b4 REF
2 4 8 16
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Outline

• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
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Single Ended SAR-ADC.

V REF
sample
V REF

8C 4C 2C C C Clock

sample v in

V REF V REF
2
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Sampling Mode
V REF Clock
sample VDAC
V REF sample
invert
8C 4C 2C C C Clock

sample vVInin VDAC V REF

VIn

V REF V Ref
2
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Inversion Mode
V REF Clock
VDAC =
sample
V REF v IN
invert
8C 4C 2C C C Clock

invert VDAC
V REF
gnd v IN

V REF vin
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Charge redistribution mode (MSB)

V REF Clock
VDAC=
V sample
V REF vin  REF
2 invert
8C 4C 2C C C Clock

VDAC
V REF
V REF
V REF 8C V INITIAL
V REF 2 V REF
8C
2
1
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Charge redistribution mode (MSB-1)

V REF Clock
VDAC =
V REF V REF sample
V REF vin  
2 4 invert
8C 4C 2C C C Clock

VDAC
V REF V REF
4C V REF 4
V REF V INITIAL
V REF 4
12C

1 0
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Mode Redistribution de la charge (MSB-2)

V REF Clock
VDAC =
V V sample
V REF vin  REF  REF
2 8 invert
8C 4C 2C C C Clock

VDAC V REF
V REF
8
V REF V REF

V REF V V V
Vin  b1  b2 REF  b3 REF  b4 REF
2 4 8 16 1 0 1
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Mode Redistribution de la charge (LSB)

VREF Clock
VDAC =
V V V sample
V REF v IN  REF  REF  REF invert
2 8 16
8C 4C 2C C C Clock

VDAC V REF
V REF
16
V REF V REF

V REF V V V
Vin  b1  b2 REF  b3 REF  b4 REF
2 4 8 16 1 0 1 0
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Problem
Selecting V REF V dd To increase the dynamic range
Leakage when using
V dd normal PMOS switch.
V dd
Sometimes V DAC V dd
V dd

8C 4C 2C C C Clock

V dd
V dd
V dd
VDAC V dd

Possible Solution: Switched charge-pump [scott03] or Bootstrap [dessouky01]

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Possible solutions - Leakage

Bootstrap Switch Charge pump Switch
VDD

VDAC

VDAC Reliability problem

0 < VDAC < 1.5 VDD

Since sometimes VDAC value=1.5 VDD

While VG1 = 0 when M1 is ON, VGD,M1 exceeds VDD
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Possible solutions - Reliability

0 < VDAC < 1.5 VDD

Max OFF = VDD - Vtn

Shielding Switch
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Possible solutions - Circuitry

Bootstrap [dessouky01] Modified Shielding

Bootstrap
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Differential SAR-ADC
V dd V dd
2
v in
4C 2C C C 2
V ddsample
2
Triple Reference
V dd
2 4C C
Clock
2C C

v in
sample
2 V dd V dd
2
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Differential SAR-ADC
V dd V dd
2 Clock
sample
4C 2C C C
invert
V dd vin V dd V dd V dd
    V dd
2 2 4 8 16
V dd vin V dd V dd V dd In1
   
2 2 4 8 16
Clock
4C 2C C C DAC2
V dd
2
DAC1
V dd
V dd V dd 2
In2 0
1 0 1
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Operation – Summary
Single Ended Double reference Differential Triple reference
2 times the numbers of capacitors
6 times the numbers of switches
Special Switch No need for special switch
(charge-pump - bootstrap)
Differential architectures advantages :
- Suppressing even harmonics
-Common mode rejection
-Offset removal
Lower power consumption Better performance at high frequencies
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Outline

• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
 23

Design - Architecture Clock

In Capacitor
array
Comp
Control
Switches
SAR

Switches Control
Sample invert
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Capacitor array design issues - Noise

kT
1- Thermal noise [ ], due to Sampling
CTOT
V dd
sample R Switch
v in
V dd

8C 4C 2C C C Clock CTOT  16C

sample v in
V dd

CUnit increases, thermal noise decreases

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Capacitor array design issues - Mismatch

2  Capacitor Mismatch (Introduced in fabr ication)

- Affects Generated comparison levels of the capacitve DAC

V dd
8(C  C ) 
V dd 2
8C

CUnit increases, mismatch effect decreases

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Capacitor array design issues - f Sampling

R Switch
3- Sampling Frequency v in

CTOT  16C

Clock   R SwitchCTotal

sample
V dd
TClock
t sampling    For an accurate sampling
2

CUnit decreases, bandwidth increases

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Switches
1) Switches selection
• NMOS to switch Vgnd and Vcm
• PMOS to switch Vdd
• CMOS to switch Vin
• Bootstrap to force deep off-state of critical switches

2) Sizing switches (compromise)


• Increasing W/L reduces Rswitch and so , on the account of
increasing switch parasitcs.
• In the used DAC, this will be of minor importance if operating in
low frequency because the switches are all connected to the
bottom plates
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Design - Architecture Clock

In Capacitor
array
Comp
Control
Switches
SAR

Switches Control
Sample invert
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Comparator Circuit
Reset to Vdd h MP11
h
MP9 MP7 MP8

Qm
Qp

Cuts the current path h MN5 MN6 h

in the RESET phase

ep MN1 MN3 MN4 MN2

Input Signal em

Latch
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Comparator – Operation phases

Reset phase to Vdd Comparison phase

Inputs Latch starts

V LSB
Resolution >
2
Response time < 0.5 TH
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Comparator – Design tradeoff

Sizing input pair and latch

 latch  init I Total V offset

Improve with Improve with

decreasing L increasing L

Tradeoff
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Design - Architecture Clock

In Capacitor
array
Comp
Control
Switches
SAR

Switches Control
Sample invert
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SAR algorithm - Implementation

LFSR: Linear Feedback Shift Register

DAC outputs C
0 0 0 0 0 0 0 0 0 X
1 1 0 0 0 0 0 0 0 a8
2 a8 1 0 0 0 0 0 0 a7
3 a8 a7 1 0 0 0 0 0 a6
4 a8 a7 a6 1 0 0 0 0 a5
5 a8 a7 a6 a5 1 0 0 0 a4
6 a8 a7 a6 a5 a4 1 0 0 a3
7 a8 a7 a6 a5 a4 a3 1 0 a2
8 a8 a7 a6 a5 a4 a3 a2 1 a1
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Systematic design for SA-ADC

Resolution – BW – Power - Techno

Non idealities and noise Comparator specs System architecture

Clock frequency DAC topology,
Thermal noise, mismatch, … Settling, resolution, kickback….
SAR algorithm,
Sampling technique
Switches Select number of
Sizing stages

Cmin Sizing procedure

Cmax

No Cmax >Cmin No No Check Specs

No

Yes Yes
Finalize design
C unity = C min

Layout
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Outline

• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
 36

Case Study
• Case Study
▫ Differential Architecture
▫ Resolution: 8bit
▫ BW: 50 KHz
▫ Fclock: 1MHz
▫ Technology: 0.13u ST, MIM Capacitors

• Verification
▫ VHDL AMS used for verification with simulation
▫ Different levels of abstraction (Behavioral , gates, transistor, …)
▫ Mixed blocs simulation (Analog / Digital)
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Multiple abstractions
Macro Transistor VHDL
Macro Macro model
model Transistor MIM model

Capacitor
array Comp
Control
In +
Latch
Switches

Transistor
Clock gen VHDL
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Verification Environment
Abstraction level
Ideal, mismatched, techno, … Type of analysis

Component sizes Resolution – BW

Verification Environment presets

DAC topology,
SAR algorithm,
Sampling technique

Sketch output Sketch Transient

spectrum response at each node
Sketch INL and
Calculate SNDR
DNL
Sketch SNDR v.s. Sketch SNDR v.s.
fin Ain
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Transiant – Single Ended - Output

Transistor level simulations
Vdd 1.2V

Fin 1.4KHz

Fclk 1MHz

Vinp-p 1.2V
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Transiant – Differential - Output

Transistor level simulations
Vdd 1.2V

Fin 1.4KHz

Fclk 1MHz

Vinp-p 1.2V
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Transiant – Differential - DACs

Differential DACs output
Transistor level simulations
Vdd 1.2V

Fin 1.4KHz

Fclk 1MHz

Vinp-p 1.2V
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Transiant – Differential - Comparator

Full conversion: Differential DACs output – Comparator output
Transistor level simulations
Vdd 1.2V

Fin 1.4KHz

Fclk 1MHz

Vinp-p 1.2V
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Transient – SAR control

Control block turning ON and OFF DAC switches [case of 0 input]
VHDL Description
Vdd 1.2V

Fin 1.4KHz

Fclk 1MHz

Vinp-p 1.2V
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Transient – Full Scale Ramp

Full Scale Slow ramp excitation Zoom - in

Vinp-p 1.2V
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Static Performance - Transistor Level

Static performance Evaluation in (LSB): DNL and INL [16 sample / bin]
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Dynamic Performance – Ideal Models

Ideal models simulation
Vdd 1.2V

Fin 1.4KHz

Fclk 1MHz

Vinp-p 1.2V

4096 point FFT

SNDR = 47.47 dB
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Dynamic Performance – Mixed Models

Ideal MOS
Vdd 1.2V switches
Fin 1.4KHz

Fclk 1MHz
SNDR = 47.47 dB SNDR = 47.44 dB
Vinp-p 1.2V

4096 point FFT 0.01

MOS
mismatch
comparator
in Cu

SNDR = 46.78 dB SNDR = 46.69 dB

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Dynamic Performance – Transistor Level

Transistor level simulations
Vdd 1.2V

Fin 1.4KHz Power Specral Density (dB)

Fclk 1MHz

1024 point FFT

SNDR = 46.2 dB

Frequency (Hz)
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Dynamic Performance
Vdd 1.2V Signal to noise and distortion ratio SNDR(dB) Transistor level simulations

Fin 1.4KHz SNDR max

Fclk 1MHz Ideal =47.47 dB
Transistor Level = 46.2

4096 point FFT

Amplitude of input signal(dB)

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Dynamic Performance
Transistor level simulations
Signal to noise and distortion ratio SNDR(dB)
Vdd 1.2V
Fclk 1MHz
Vinp-p 1.2V

4096 point FFT

BW =55 KHz

Frequency of input signal (Hz)

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Mismatch analysis
Vdd 1.2V
0.05
Fin 1.4KHz mismatch 0.1
in Cu mismatch
Fclk 1MHz in Cu

Vinp-p 1.2V
SNDR = 46.36 dB SNDR = 44.13 dB

4096 point FFT

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Layout generation for SA-ADC

Design phase
Number of
capacitors and
sizes
Desired layout Unit
Comparator
shape capacitance
transistor sizes
Common centroid
placement algorithm

Layout template s
-Component connectivity
-Relative place and route

CAIRO Layout generation Target technology

DRC – LVS

Parasitics Ext.

Verification Fabrication
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Layout – Comparator - Floorplan

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Layout – Comparator - Generated

Area 22 x 39 µm2 Dummies Removed for Layout verification

 55

Layout – Differential DACs - Floorplan

Common centroid placement for 16 capacitor
 56

Layout – Differential DACs - Generated

Layout 1 - 256 Cu – Placed and Routed – Area
1.26 x 0.26 mm2 and Huge routing parasitics
 57

Layout – Differential DACs - Manual

Layout 2 - 256 Cu – Placed
and Routed – 2/3 less
routing parasitics
Area 0.1056 mm2

ZOOM
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Performance
[Hong07] This work* [scott03]
Technology 0.18 µm 0.13 µm 0.25 µm
Supply 0.83 V 1.2 V 1.0 V
Input range Rail to Rail Rail to Rail Rail to Rail
Sampling rate 111 KHz 111 KHz 100 KHz
Unit Cap. 24 fF 30fF 12f
Power (Analog) 1.16 µW 0.72µW 2.2 µW
Area 0.062 mm2 0.122 mm2 0.053 mm2
SNDR@BW 47.40 dB 46.2dB 43.8 dB
Architecture Single Ended Differential Single Ended
FOM 65 fJ/bit 64fJ/bit 2163 fJ/bit
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Outline

• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
 60

Summary and Conclusion

▫ Systematic design methodology for SA-ADC from
system to layout.
▫ General simulation environment
▫ Different abstraction levels.
▫ Different verification tests.
▫ Emphasis on analog design automation and reuse
▫ Optimizing Layout for best component matching
▫ Verification with case study for WSN specs
 61

Perspectives
▫ Targeting high frequency specs (>500 Msample/S)
 Redundant system error correction code [Kuttner02]
 Digital calibration [Promitzer01]
 Asynchronous operation [Chen06]
 Time interleaving [Chen06]

▫ Full Automation
 Sizing procedure with layout parasitics awareness
 Layout generation for the full ADC
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Thank You