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Vlsi Design MCQ

The document discusses key concepts in CMOS VLSI design including logic conventions, CMOS gate circuits like NOT and NAND gates, the roles of n-MOS and p-MOS transistors, switching behavior, output states, and the CMOS fabrication process. Some key points covered are: - In positive logic, 1 represents true state and in negative logic, 0V represents 1. - A CMOS NOT gate has a p-MOS pull-up and n-MOS pull-down transistor. - In a CMOS gate, the n-MOS acts as a pull-down network and p-MOS acts as a pull-up network. Switching occurs when one transistor is on and the other is off

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Akanksha Dixit
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835 views

Vlsi Design MCQ

The document discusses key concepts in CMOS VLSI design including logic conventions, CMOS gate circuits like NOT and NAND gates, the roles of n-MOS and p-MOS transistors, switching behavior, output states, and the CMOS fabrication process. Some key points covered are: - In positive logic, 1 represents true state and in negative logic, 0V represents 1. - A CMOS NOT gate has a p-MOS pull-up and n-MOS pull-down transistor. - In a CMOS gate, the n-MOS acts as a pull-down network and p-MOS acts as a pull-up network. Switching occurs when one transistor is on and the other is off

Uploaded by

Akanksha Dixit
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Important MCQ VLSI DESIgn:

.
In negative logic convention, the Boolean Logic [1] is equivalent to:
a) +VDD
b) 0 V
c) -VDD
d) None of the mentioned
Answer: b
Explanation: In negative logic convention, the Boolean Logic [1] is equivalent to 0
V and Logic �0� is equivalent to +VDD

In positive logic convention, the true state is represented as:


a) 1
b) 0
c) -1
d) -0
Answer: a
Explanation: In positive logic convention, the Boolean logic �1� is known to be
representing true state.

The CMOS gate circuit of NOT gate is:


a)
b)
c)
d)
Answer: d
Explanation: The CMOS logic circuit for NOT gate has a p-MOS as a pull up
transistor and n-MOS as driver transistor which is represented accurately in figure
(d)

The truth table which accurately explains the operation of CMOS not gate is:
a)
b)
c)
d)
Answer: d
Explanation: The output of CMOS depends on the state of nMOS and pMOS
transistor.The correct truth table is:

The CMOS logic circuit for NAND gate is:


a)
b)
c)
d) None of the mentioned
Answer: a
Explanation: The accurate cmos logic circuit for NAND gate is:

In CMOS logic circuit the n-MOS transistor acts as:


a) Load
b) Pull up network
c) Pull down network
d) Not used in CMOS circuits
Answer: c
Explanation: A static CMOS gate has an nMOS pull-down network to
connect the output to 0 (GND)

In CMOS logic circuit the p-MOS transistor acts as:


a) Pull down network
b) Pull up network
c) Load
d) Short to ground
Answer: b
Explanation: A static CMOS gate has an pMOS pull-up network to
connect the output to VDD (1)

In CMOS logic circuit, the switching operation occurs because:


a) Both n-MOSFET and p-MOSFET turns OFF simultaneously for input �0� and turns ON
simultaneously for input �1�
b) Both n-MOSFET and p-MOSFET turns ON simultaneously for input �0� and turns OFF
simultaneously for input �1�
c) N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input �1�
and N-MOS transistor turns OFF, and p-MOS transistor turns ON for input �0�
d) None of the mentioned
Answer: c
Explanation: In CMOS logic circuit, the switching operation occurs because N-MOS
transistor turns ON, and p-MOS transistor turns OFF for input �1� and N-MOS
transistor turns OFF, and p-MOS transistor turns ON for input �0�. The networks are
arranged such that one is ON and the other OFF for any input pattern.

When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the
output is :
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) High impedance or floating(Z)
d) None of the mentioned
Answer: c
Explanation: When both pull up and pull down transistors are OFF, the high
impedance for floating Z output state results.

When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is :
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) Crowbarred or Contention(X)
d) None of the mentioned
Answer: c
Explanation: The crowbarred (or contention) X level exists when both pull up and
pull down transistors are simultaneously turned ON. Contention between the two
networks results in an indeterminate output level and dissipates static power.

CMOS technology is used in developing


a) microprocessors
b) microcontrollers
c) digital logic circuits
d) all of the mentioned
Answer: d
Explanation: CMOS technology is used in developing microcontrollers,
microprocessors, digital logic circuits and other integrated circuits.

CMOS has
a) high noise margin
b) high packing density
c) high power dissipation
d) high complexity
Answer: b
Explanation: Some of the properties of CMOS are that it has low power dissipation,
high packing density and low noise margin.

In CMOS fabrication, nMOS and pMOS are integrated in same substrate.


a) true
b) false
Answer: a
Explanation: In CMOS fabrication, nMOS and pMOS are integrated in the same chip
substrate. n-type and p-type devices are formed in the same structure.

15 P-well is created on
a) p subtrate
b) n substrate
c) p & n substrate
d) none of the mentioned
Answer: b
Explanation: P-well is created on n substrate to accommodate n-type devices whereas
p-type devices are formed in the ntype substrate.

Oxidation process is carried out using


a) hydrogen
b) low purity oxygen
c) sulphur
d) nitrogen
Answer: a
Explanation: Oxidation process is carried out using high purity oxygen and
hydrogen. Oxidation is a process of oxidizing or being oxidised.

Photoresist layer is formed using


a) high sensitive polymer
b) light sensitive polymer
c) polysilicon
d) silicon di oxide
Answer: b
Explanation: Light sensitive polymer is used to form the photoresist layer.
Photoresist is a light sensitive material used to form patterned coating on a
surface.

In CMOS fabrication,the photoresist layer is exposed to


a) visible light
b) ultraviolet light
c) infra red light
d) fluorescent
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the
regions where diffusion is to take place.

Few parts of photoresist layer is removed by using


a) acidic solution
b) neutral solution
c) pure water
d) diluted water
Answer: a
Explanation: Few parts of photoresist layer is removed by treating the wafer with
basic or acidic solution. Acidic solutions are those which have pH less than 7 and
basic solutions have greater than

P-well doping concentration and depth will affect the


a) threshold voltage
b) Vss
c) Vdd
d) Vgs
View Answer
Answer: a
Explanation: Diffusion should be carried out very carefully, as doping
concentration and depth will affect both threshold voltage and breakdown voltage.

Which type of CMOS circuits are good and better?


a) p well
b) n well
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of
lower substrate bias effect.

N-well is formed by
a) decomposition
b) diffusion
c) dispersion
d) filtering
Answer: b
Explanation: N-well is formed by using ion implatation or diffusion. Ion
implantation is a process by which ions of a material are accelerated in an
electrical field and impacted into a solid. Diffusion is a process in which net
movement of ions or molecules play a major role.

_______ is sputtered on the whole wafer


a) silicon
b) calcium
c) potassium
d) aluminium
Answer: d
Explanation: Aluminium is sputtered on the whole waffer before removing the excess
metal from the wafer.

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