Important MCQ VLSI DESIgn:-

1. In negative logic convention, the Boolean Logic [1] is equivalent to:

a) +VDD
b) 0 V
c) -VDD
d) None of the mentioned
Answer: b
Explanation: In negative logic convention, the Boolean Logic [1] is equivalent to 0 V and Logic ‘0’ is
equivalent to +VDD

2. In positive logic convention, the true state is represented as:

a) 1
b) 0
c) -1
d) -0
Answer: a
Explanation: In positive logic convention, the Boolean logic ‘1’ is known to be representing true state.

3. The CMOS gate circuit of NOT gate is:

a)

b)

c)
d)
Answer: d
Explanation: The CMOS logic circuit for NOT gate has a p-MOS as a pull up transistor and n-MOS as

driver transistor which is represented accurately in figure (d)

4. The truth table which accurately explains the operation of CMOS not gate is:
a)

b)

c)

d)

Answer: d
Explanation: The output of CMOS depends on the state of nMOS and pMOS transistor.The correct truth
table is:
5. The CMOS logic circuit for NAND gate is:

a)

b)

c)
d) None of the mentioned
Answer: a

Explanation: The accurate cmos logic circuit for NAND gate is:

6. In CMOS logic circuit the n-MOS transistor acts as:

a) Load
b) Pull up network
c) Pull down network
d) Not used in CMOS circuits

Answer: c
Explanation: A static CMOS gate has an nMOS pull-down network to
connect the output to 0 (GND)
7. In CMOS logic circuit the p-MOS transistor acts as:
a) Pull down network
b) Pull up network
c) Load
d) Short to ground
Answer: b
Explanation: A static CMOS gate has an pMOS pull-up network to
connect the output to VDD (1)

8. In CMOS logic circuit, the switching operation occurs because:

a) Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’ and turns ON simultaneously
for input ‘1’
b) Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’ and turns OFF simultaneously
for input ‘1’
c) N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-MOS transistor
turns OFF, and p-MOS transistor turns ON for input ‘0’
d) None of the mentioned
Answer: c
Explanation: In CMOS logic circuit, the switching operation occurs because N-MOS transistor turns ON,
and p-MOS transistor turns OFF for input ‘1’ and N-MOS transistor turns OFF, and p-MOS transistor
turns ON for input ‘0’. The networks are arranged such that one is ON and the other OFF for any input
pattern.

9. The CMOS logic circuit for NOR gate is:

a)

b)
c)

d)
Answer: a

10. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is :
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) High impedance or floating(Z)
d) None of the mentioned
Answer: c
Explanation: When both pull up and pull down transistors are OFF, the high impedance for floating Z
output state results.
11. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is :
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) Crowbarred or Contention(X)
d) None of the mentioned

Answer: c
Explanation: The crowbarred (or contention) X level exists when both pull up and pull down transistors
are simultaneously turned ON. Contention between the two networks results in an indeterminate
output level and dissipates static power.
12. CMOS technology is used in developing
a) microprocessors
b) microcontrollers
c) digital logic circuits
d) all of the mentioned
Answer: d
Explanation: CMOS technology is used in developing microcontrollers, microprocessors, digital logic
circuits and other integrated circuits.
13. CMOS has
a) high noise margin
b) high packing density
c) high power dissipation
d) high complexity
Answer: b
Explanation: Some of the properties of CMOS are that it has low power dissipation, high packing
density and low noise margin.
14. In CMOS fabrication, nMOS and pMOS are integrated in same substrate.
a) true
b) false
Answer: a
Explanation: In CMOS fabrication, nMOS and pMOS are integrated in the same chip substrate. n-
type and p-type devices are formed in the same structure.
15 P-well is created on
a) p subtrate
b) n substrate
c) p & n substrate
d) none of the mentioned
Answer: b
Explanation: P-well is created on n substrate to accommodate n-type devices whereas p-type
devices are formed in the ntype substrate.
16 Oxidation process is carried out using
a) hydrogen
b) low purity oxygen
c) sulphur
d) nitrogen
Answer: a
Explanation: Oxidation process is carried out using high purity oxygen and hydrogen. Oxidation is a
process of oxidizing or being oxidised.
17. Photoresist layer is formed using
a) high sensitive polymer
b) light sensitive polymer
c) polysilicon
d) silicon di oxide
Answer: b
Explanation: Light sensitive polymer is used to form the photoresist layer. Photoresist is a light
sensitive material used to form patterned coating on a surface.
18. In CMOS fabrication,the photoresist layer is exposed to
a) visible light
b) ultraviolet light
c) infra red light
d) fluorescent
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion
is to take place.
19. Few parts of photoresist layer is removed by using
a) acidic solution
b) neutral solution
c) pure water
d) diluted water
Answer: a
Explanation: Few parts of photoresist layer is removed by treating the wafer with basic or acidic
solution. Acidic solutions are those which have pH less than 7 and basic solutions have greater than
20. P-well doping concentration and depth will affect the
a) threshold voltage
b) Vss
c) Vdd
d) Vgs
View Answer
Answer: a
Explanation: Diffusion should be carried out very carefully, as doping concentration and depth will
affect both threshold voltage and breakdown voltage.
21. Which type of CMOS circuits are good and better?
a) p well
b) n well
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of lower substrate
bias effect.
23. N-well is formed by
a) decomposition
b) diffusion
c) dispersion
d) filtering
Answer: b
Explanation: N-well is formed by using ion implatation or diffusion. Ion implantation is a process by
which ions of a material are accelerated in an electrical field and impacted into a solid. Diffusion is a
process in which net movement of ions or molecules play a major role.
24. _______ is sputtered on the whole wafer
a) silicon
b) calcium
c) potassium
d) aluminium
Answer: d
Explanation: Aluminium is sputtered on the whole waffer before removing the excess metal from the
wafer.

In negative logic convention, the Boolean Logic [1] is equivalent to:

A +VDD
B0V
C -VDD
D None of the mentioned
Answer: B

In positive logic convention, the true state is represented as:

A1
B0
C -1
D-0
Answer: A

In CMOS logic circuit the n-MOS transistor acts as:

A Load
B Pull up network
C Pull down network
D Not used in CMOS circuits
Answer: C

In CMOS logic circuit the p-MOS transistor acts as:

A Pull down network
B Pull up network
C Load
D Short to ground
Answer: B

In CMOS logic circuit, the switching operation occurs because:

A Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’ and turns ON simultaneously for
input ‘1’
B Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’ and turns OFF simultaneously for
input ‘1’
C N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-MOS transistor
turns OFF, and p-MOS transistor turns ON for input ‘0’
D None of the mentioned
Answer: c

When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is :
A 1 or Vdd or HIGH state
B 0 or ground or LOW state
C High impedance or floating(Z)
D None of the mentioned
Answer: c

When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is :
A 1 or Vdd or HIGH state
B 0 or ground or LOW state
C Crowbarred or Contention(X)
D None of the mentioned
Answer:C
CMOS technology is used in developing
A microprocessors
B microcontrollers
C digital logic circuits
D all of the mentioned
Answer: D
Explanation: CMOS technology is used in developing microcontrollers, microprocessors, digital logic
circuits and other integrated circuits.

CMOS has
A high noise margin
B high packing density
C high power dissipation
D high complexity
Answer: B

P-well is created on
A p subtrate
B n substrate
C p & n substrate
D none of the mentioned
Answer:B

Oxidation process is carried out using

A hydrogen
B low purity oxygen
C sulphur
D nitrogen
Answer: A

Photoresist layer is formed using

A high sensitive polymer
B light sensitive polymer
C polysilicon
D silicon di oxide
Answer: B

P-well doping concentration and depth will affect the

A threshold voltage
B Vss
C Vdd
D Vgs
Answer: A

Which type of CMOS circuits are good and better?

A p well
B n well
C all of the mentioned
D none of the mentioned
Answer: B

N-well is formed by
A decomposition
B diffusion
C dispersion
D filtering
Answer: B

_______ is sputtered on the whole wafer

A silicon
B calcium
C potassium
D aluminium
Answer: D

VLSI technology uses ________ to form integrated circuit

A transistors
B switches
C diodes
D buffers
Answer: A

Medium scale integration has

A ten logic gates
B fifty logic gates
C hundred logic gates
D thousands logic gate
Answer: C

Which color is used for n-diffusion?

A red
B blue
C green
D yellow
Answer:C

n and p transistors are separated by using

A differentiation line
B separation line
C demarcation line
D black line
Answer: C

Which is more complex process?

A buried contact
B butting contact
C buried & butting contact
D none of the mentioned
Answer: A

Etching is the process used for

Deposition of metal layer
Selective removal of undesired metallic layer
Introducing dopants into semiconductor
None of these

In positive photoresist on exposure to UV light

Unexposed photoresist is removed by appropriate solvent
Exposed photoresist is removed by appropriate solvent
Complete photoresist is removed by appropriate solvent
No effect on photoresist
Which one of the following is the most common form of radiation used in photolithography
Electronic beam radiation
Infrared light
Ultraviolet light
X-ray

Which one of the following is not one of the functions of silicon dioxide in semiconductor
processing
Provides electrical insulation between levels in multilevel metallization systems
Serves as a conducting path between levels in multilevel metallization systems
Serves as a mask to prevent diffusion of dopants into silicon
Serves to isolate devices in a circuit

Expression for drain current ID in saturation region for NMOS is given by

None of these

Expression for Shockley diode equation is

None of these

The Ebers–Moll model is valid for:

Bipolar junction transistors
MOS transistors
Uni-polar junction transistors
Junction field-effect transistors

Advantage of short channel device is

Reduced area requirement
Improvement in speed
Reduced input capacitance associated with smaller device
All of these

Which spice model of MOSFET is termed as semi empirical model

Level 1 model
Level 2 model
Level 3 model
Both (a) or (b)

SPICE is one of the most widely used simulation programs. What does SPICE stand for?
Simulation Program with Integrated Circuit Emphasis.
Simulation Program with In-Circuit Emulation.
Simulation Protocol for Internal Circuit Exploration
Self-Projecting Implementation of Circuit Examples

What is in the expression of threshold voltage

Channel length modulation parameter
Bulk threshold parameter
Surface potential
None of these

BSIM model is the spice model of

MOSFET
Diode
BJT
None of these

Random logic form is used to describe digital circuits that

Lacks regularity of circuit function
Demonstrates regularity in their layout
Regularity is not a factor
None of these
Difference between PLA FSM and Micro programmed FSM is
Micro programmed FSM is more complex
Micro programmed FSM is desirable for larger systems
Both of these
None of these

The Register storage circuit used within sequential circuit is

Quasi static register storage cell
A static register cell
Both (a) and (b)
One of these

A useful circuit structure to implement a shift or rotate is

Barrel Shifter
Microcode controller
Algotronix
None of these

Twin tub process uses

N well
P well
Both n well and p well
None of these

Which of the following is the layout design approaches

Micron design rules
Lambda design rules
Both (a) or (b)
None of these

Lateral latch up triggering occur when

Current flows in the emitter of NPN transistor
Current flows in the emitter of PNP transistor
Current flows in both the transistor
No current flows

Latch up prevention technique is

Use of guard ring
Reduction of R-well and R-substrate
Keeping sufficient spacing between the NMOS and PMOS transistor
All of the
Quiz-2
Q1.  In CMOS inverter, the propagation delay of a gate is the/an _________ transition
delay time for the signal during propagation from input to output especially when the
signal changes its value.
a. Highest
b. Average
c. Lowest
d. None of the above
ANSWER: b

Q2. In CMOS circuits, which type of power dissipation occurs due to switching of
transient current and charging & discharging of load capacitance? 
a. Static dissipation
b. Dynamic dissipation
c. Both a and b
d. None of the above
ANSWER: B

Q3. Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?
a. Load capacitance
b. Supply voltage
c. Gain factor of MOS
d. All of the above
ANSWER: d

Q4. The power consumption of static CMOS gates varies with the _____ of power
supply voltage.
a. square
b. cube
c. fourth power
d. 1/8 th power
ANSWER: A

Q5 In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin
count?
a. Input pad design
b. Output pad design
c. Three state pad design
d. All of the above
ANSWER: c

Q6. Which type of CPLD packaging comprises pins on all four sides that wrap around
the edges of chip?
a. Plastic-Leaded Chip Carrier (PLCC)
b. Quad Flat Pack (QFP)
c. Ceramic Pin Grid Array (PGA)
d. Ball Grid Array (BGA)
ANSWER: a
Q7. Which among the following EDA tool is available for design simulation?
a. OrCAD
b. ALDEC
c. Simucad
d. VIVElogic
ANSWER: d

Q8.  In MOS devices, the current at any instant of time is ______of the voltage across
their terminals.
a. constant & dependent
b. constant & independent
c. variable & dependent
d. variable & independent
ANSWER: b

Q9. For complex gate design in CMOS, OR function needs to be implemented by

_______ connection/s of MOS.
a. Series
b. Parallel
c. Both series and parallel
d. None of the above
ANSWER: B

Q10. In pull-up network, PMOS transistors of CMOS are connected in parallel with the
provision of conducting path between output node & Vdd yielding _____ output.
a. 1
b. 0
c. Both a and b
d. None of the above
ANSWER: a

An NMOS transistor with device transconductance K = 20µA/V2and threshold voltage of 1.5 V is

operated atVGS= 5V and ID= 100 µA. Find VDS.Solution :- Let us assume that the MOSFET is
operating in Saturation,ID sat= K/2 ( VGS– VTH )2= 20/2 ( 5 – 1.5)2= 122.5 µAFor device in saturation,
the ID122.5 µA but IDof device isGiven as 100 µA which is less than ID sathence the device is not In
saturation but in linear region. ---------------------- ( 2 Marks )ID linear= K/2 { 2 ( VGS– VTH ) VDS–
VDS2}100 µA = 20/2 { 2 ( 5 – 1.5) VDS– VDS2}10 = 7VDS– VDS2VDS2– 7VDS+ 10 = 0( VDS– 5 )
( VDS– 2 ) = VDS= 5 or VDS= 2 For linear region, VDS< ( VGS– VTH )i.e. VDS< ( 5 – 1.5)i.e. VDS<
3.5VHence VDS= 2V ----------------------- ( 3 Marks )1

Solution :- Let us assume that the MOSFET is operating in Saturation,ID sat= K/2 ( VGS– VTH )2= 20/2
( 5 – 1.5)2= 122.5 µAFor device in saturation, the ID122.5 µA but IDof device isGiven as 100 µA which
is less than ID sathence the device is not In saturation but in linear region. ---------------------- ( 2 Marks )
ID linear= K/2 { 2 ( VGS– VTH ) VDS– VDS2}100 µA = 20/2 { 2 ( 5 – 1.5) VDS– VDS2}10 = 7VDS–
VDS2VDS2– 7VDS+ 10 = 0( VDS– 5 ) ( VDS– 2 ) = VDS= 5 or VDS= 2 For linear region, VDS<
( VGS– VTH )i.e. VDS< ( 5 – 1.5)i.e. VDS< 3.5VHence VDS= 2V ----------------------- ( 3 Marks )1
InternshTraining

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on
“BiCMOS Technology”.
1. MOS technology has more load driving capability.
a) true
b) false
View Answer
Answer: b
Explanation: One of the disadvantage of MOS technology is it has limited
load driving capabilities.
2. What is the disadvantage of MOS device?
a) limited current sourcing
b) limited voltage sinking
c) limited voltage sourcing
d) unlimited current sinking
View Answer
Answer: a
Explanation: MOS devices have limited current sourcing and current
sinking abilities.
3. What are the advantages of BiCMOS?
a) higher gain
b) high frequency characteristics
c) better noise characteristics
d) all of the mentioned
View Answer
Answer: d
Explanation: BiCMOS provides higher gain, better noise and high
frequency characteristics than MOS transistors.
4. What are the features of BiCMOS ?
a) low input impedance
b) high packing density
c) high input impedance
d) bidirectional
View Answer
Answer: a
Explanation: Some of the features of BiCMOS are low input impedance,
low packing density, unidirectional, high output drive current etc.
5. BiCMOS has low power dissipation.
a) true
b) false
View Answer
Answer: b
Explanation: BiCMOS has high power dissipation and CMOS has low
power dissipation.
6. CMOS is
a) unidirectional
b) bidirectional
c) directional
d) none of the mentioned
View Answer
Answer: a
Explanation: BiCMOS is unidirectional and CMOS is bidirectional.
7. In bipolar transistor, its quality can be improved by
a) increasing collector resistance
b) decreasing collector resistance
c) collector resistance does not affect the quality
d) decreasing gate resistance
View Answer
Answer: b
Explanation: The quality of bipolar transistor can be improved by reducing
the collector resistance, which can be done by using the additional layer of
n+ subcollector.
8. BiCMOS can be used in
a) amplifyig circuit
b) driver circuits
c) divider circuit
d) multiplier circuit
View Answer
Answer: b
Explanation: BiCMOS is more advantageous and improved than CMOS
and it can be used in I/O and driver circuits.
9. Advantages of E-beam masks are
a) small feature size
b) larger feature size
c) looser layer
d) complex design
View Answer
Answer: a
Explanation: The advantages of E-beam masks are it has tighter layer to
layer registration and it has smaller feature sizes.
10. Which process is used in E-beam machines?
a) raster scanning
b) vector scanning
c) both of the mentioned
d) none of the mentioned
View Answer
Answer: c
Explanation: The two approaches to the design of E-beam machines are
raster scanning and vector scanning.
11. What is the feature of vector scanning?
a) faster
b) slow
c) easy handling
d) very simple design
View Answer
Answer: a
Explanation: Vector scanning is faster but data handling involved is more
complex. Vector scanning is done between the end points.
12. Which has high input resistance?
a) nMOS
b) CMOS
c) pMOS
d) BiCMOS
View Answer
Answer: b
Explanation: CMOS technology has high input resistance and is best for
constructing simple low-power logic gates.
13. BiCMOS has lower standby leakage current.
a) true
b) false
View Answer
Answer: b
Explanation: BiCMOS has potential for high standby leakage current and
has high power consumption compared to CMOS.