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IEEE 2020-2021 VLSI Project Titiles

The document lists 19 VLSI projects from IEEE in 2020-2021, including titles and year. The projects cover a range of topics in digital circuits and analog circuits, including adders, SRAM cells, oscillators, multipliers, and more. Technologies included CMOS, memristors, FinFETs, and other integrated circuit technologies.

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RatnakarVarun
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115 views2 pages

IEEE 2020-2021 VLSI Project Titiles

The document lists 19 VLSI projects from IEEE in 2020-2021, including titles and year. The projects cover a range of topics in digital circuits and analog circuits, including adders, SRAM cells, oscillators, multipliers, and more. Technologies included CMOS, memristors, FinFETs, and other integrated circuit technologies.

Uploaded by

RatnakarVarun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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S.

No IEEE 2020-2021 VLSI Project Year


Titles
1 A Carry Look ahead Adder Based on Hybrid CMOS- Memristor Logic Circuit 2020

2 Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of 2020


CMOS Integrated Circuits

3 A 7T-SRAM With Data-Write Technique by Capacitive Coupling 2020

4 Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time 2020

5 A 60GHz CMOS Power Amplifier with Parametric Matching Networks-(ADS 2020


Software)

6 A CMOS PUF Circuit Primitive Based on a Two-Dimensional Nonlinear 2020


Dynamical System

7 A Digital-to-Time Converter with Coupled Phase- Rotating LC Oscillators in 90-nm 2020


CMOS Technology

8 A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery
Circuit with High Speed Feed Forward Correction in 65 nm CMOS.

9 CMOS implementation of wide frequency bandwidth Resonator's Q-factor 2020


measurement circuit.

10 Design of Low Leakage SRAM Bitcell 2020

11 Multistage Linear Feedback Shift Register Counters With Reduced Decoding 2020
Logic in 130-nm CMOS for Large-Scale
Array Applications
12 Hybrid Logical Effort for Hybrid Logic Style Full Adders in 2020
Multistage Structures
13 A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency 2020
Compensation Technique

14 Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise 2020

15 Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for 2020


Low-Power 3 D Graphics

16 A Two-Speed, Radix-4, Serial–Parallel Multiplier 2020

17 Designing Efficient Circuits Designing Efficient Circuits Based on Runtime- 2020


Reconfigurable Field-Effect Transistors

18 Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for 2020


Enhanced Read Time and Low Leakage

19 Efficiently Mapping VLSI Circuits With Simple Cells 2020

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