Module 4

ARM CORTEX M4-Instruction Set Summary

Dr. Nisha K C R
Professor-Dept. of ECE
New Horizon College of Engineering

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 Thumb 2 Technology
• Thumb-2 is a superset of Thumb instructions,
including new 32-bit instructions for more
complex operations.
• Thumb-2 is a combination of both 16-bit and 32-
bit instructions.
• The Thumb-2 technology extended the Thumb
3

Instruction Set Architecture (ISA) into a highly

efficient and powerful instruction set that delivers
significant benefits in terms of ease of use, code
size, and performance
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 Thumb 2 Technology
• The extended instruction set in Thumb-2 is a superset of the previous 16-bit
Thumb instruction set, with additional 16-bit instructions alongside 32-bit
instructions. It allows more complex operations to be carried out in the
Thumb state, thus allowing higher efficiency by reducing the number of states
switching between ARM state and Thumb state.
• Focused on small memory system devices such as microcontrollers and
reducing the size of the processor, the Cortex-M3,M4 supports only the
Thumb-2 (and traditional Thumb) instruction set.

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Data Types in Cortex M4

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Commonly Used Directives

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Instruction Set - Cortex M4

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LIST OF SYMBOLS

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 Moving data within the processor
Move data from one register to another
Move data between a register and a special register (e.g., CONTROL,
PRIMASK, FAULTMASK, BASEPRI)
Move an immediate constant into a register

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Immediate Addressing

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Memory Access Instructions

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Optional Modifier to mention the data

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Memory Access Instructions

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Indexed Addressing Mode

Data in Memory

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Indexed Addressing Mode

Offset Data in Memory

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Illustration

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 Memory Access Instructions

Example

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Memory Access Instructions

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 Memory Access Instructions

Example

LDR R3, [R0, R2, LSL #2] ; Read memory [R0+(R2 << 2)] into R3
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Memory Access Instructions

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 Post Indexing
LDR R0, [R1], #offset ; Read memory[R1], then R1 updated to R1+offset

STR R0, [R1], #12 ; Store memory [R1], then R1 updated to R1+offset

STR r0, [r1], #12

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 Multiple load and Multiple store Instructions

LDR R4,=0x20000000 ; Set R4 to 0x20000000 (address)

LDMIA R4, {R0-R3} ; Read 4 words and store them to R0 - R3

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 Multiple load and Multiple store
Instructions
• Suppose you wanted to load a subset of all registers,
for example, registers r0 to r3, from memory, where
the data starts at address 0xBEEF0000 and continues
upward in memory. The instruction would simply be
LDMIA r9, {r0-r3}

• where the base register r9 holds the address

0xBEEF0000. The addressing mode used here is called
Increment After, or IA. This says to increment the
address after each value has been loaded from
memory

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 Multiple load and Multiple store
Instructions
• This has the same effect as four separate LDR instructions, or
LDR r0, [r9]
LDR r1, [r9, #4]
LDR r2, [r9, #8]
LDR r3, [r9, #12]
• At the end of the load sequence, register r9 has not been changed and still
holds the value 0xBEEF0000. If you wanted to load data into registers r0
through r3 and r12, you could simply add it to the end of the list, i.e.,
LDMIA r9, {r0-r3, r12}
• The lowest register will always be loaded from the lowest address in
memory, and the highest register will be loaded from the highest address.
For example, you could say
LDMIA r9, {r5, r3, r0-r2, r14}
and register r0 will be loaded first, followed by registers r1, r2, r3, r5, and r14.

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For example, if register r10 contained 0x4000,
LDMIA r10, {r0, r1, r4}
would begin by loading register r0 with data from address 0x4000. The value in the base
register is incremented by one word after the first load is complete. The second register,
r1, is loaded with data from 0x4004, and register r4 is loaded with data from 0x4008.
Note here that the base register is not updated after the instruction completes. The other
three suffixes indicate whether the base register is changed before or after the load or
store, as well as whether it is incremented or decremented, as shown in Figure

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 Stack
• PUSH and POP make it very easy to conceptually deal with stacks
(since the instruction implicitly contains the addressing mode)
• Suppose a stack that starts at address 0x20000200, grows downward
in memory (a full descending stack), and has two words pushed onto
it with the following code:
AREA Example3, CODE, READONLY
ENTRY
SRAM_BASE EQU 0X 20000200
LDR sp, =SRAM_BASE
LDR r3, =0xBABEFACE
LDR r4, =0xDEADBEEF
PUSH {r3}
PUSH {r4}

POP {r4}
POP {r3}
stop B stop ; stop program Dr.K C R Nisha_Professor-ECE
 Stack

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 Stack

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 Multiple load and Multiple store Instructions

LDR R8,=0x8000 ; Set R8 to 0x8000 (address)

STMIA R8!, {R0-R3} ; R8 change to 0x8010 after the store

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Push and Pop Instruction

Example

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Recall -Memory Access Instructions

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 Arithmetic Operation

Carry bit is set on addition when crossing 255-0 and Carry bit is cleared
on subtraction when crossing 0-255

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Arithmetic Data Operation

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Generalized format

Note: If optional S suffix is present

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Condition code bits contains the status of previous arithmetic operation
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 Logical Shift and Rotate Operations

Software uses Logical and Shift operations to

• Combine Information
• Extract Information
• Test Information

Unary Operation
Produces its result given a single input parameter
Ex. Negate, Complement, Increment, Decrement

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Logical Operations

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Logical Operations

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 Logical Operations

Generalized format

Note: Z and N condition code bits are updated

Some flexible second operand2 may affect carry bit

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Shift and Rotate Operations

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Shift and Rotate Operations

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Shift and Rotate Operations

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 Data Conversion Operations
Instructions are available for handling signed and unsigned extensions of data; for
example, to convert an 8-bit value to 32-bit, or from 16-bit to 32-bit. The signed and
unsigned instructions are available in both 16-bit and 32-bit forms

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 Data Conversion Operations
• For SXTB/SXTH, the data are sign extended using bit[7]/bit[15] of Rn.
• With UXTB and UXTH, the value is zero extended to 32-bit.

• Illustration:
• For example, if R0 is 0x55AA8765; 0101 0101 1010 1010 1000 0111 0110 0101

• SXTB R1, R0 ; R1 = 0x00000065; 0000 0000 0000 0000 0000 0000 0110 0101

SXTH R1, R0 ; R1 = 0xFFFF8765 ; 1111 1111 1111 1111 1000 0111 0110 0101

UXTB R1, R0 ; R1 = 0x00000065 ; 0000 0000 0000 0000 0000 0000 0110 0101
UXTH R1, R0 ; R1 = 0x00008765 0000 0000 0000 0000 1000 0111 0110 0101

• These instructions are useful for converting between different data types.

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 Data Conversion Operations

The 32-bit form of these instructions can access high registers, and optionally
rotate the input data before the signed extension operations,

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 Reverse Operation
• These instructions are usually used for converting data between little endian and big
endian.
• The 16-bit form of these instructions can only access low registers (R0 to R7).

• REV reverses the byte order in a data word, and REVH reverses the byte order
inside a half-word.
For example, if R0 is 0x12345678, in executing the following:
REV R1, R0 ; R1 will be 0x78563412
REVH R2, R0 ; R2 will be 0x34127856.
• REVSH - processes the lower half-word and then sign extends the result.
For example, if R0 is 0x33448899, running:
REVSH R1, R0; R1 will become 0xFFFF9988.

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Reverse Operation

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 Bit field processing Instruction
To make the Cortex!-M3 and Cortex-M4 processor an excellent architecture for
control applications, these processors support a number of bit-field processing
operations,

• BFC (Bit Field Clear) clears 1 to 31 adjacent bits in any position of a register.
The syntax of the instruction is:
BFC <Rd>, <#lsb>, <#width> ;

For example:
LDR R0,=0x1234FFFF; 0001 0010 0011 0100 1111 1111 1111 1111
BFC R0, #4, #8
This will give R0 = 0x1234F00F.
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 Bit field processing Instruction

• BFI (Bit Field Insert) copies 1 to 31 bits (#width) from one register to any location
(#lsb) in another register. The syntax is:

BFI <Rd>, <Rn>, <#lsb>, <#width>

For example:
LDR R0,=0x12345678 ;
LDR R1,=0x3355AACC ;

BFI R1, R0, #8, #16 ; Insert R0[15:0] to R1[23:8]

This will give R1 = 0x335678CC;

Note:
The parameter #lsb indicates the least significant bit of the bitfield (in other words, where to
start in the bit pattern going from right to left) and should be in the range of 0 to 31. The #width
parameter indicates the width of the bitfield; this parameter should be in the range of 1 to (32-
lsb).

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 Compare and Test

The compare and test instructions are used to update the flags in the APSR,
which may then be used by a conditional branch or conditional execution
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 Program flow control
Several Program Control Instruction:

• Branch Instructions
• Function Call Instructions
• Conditional branch
• Combined compare and conditional branch
• Conditional execution (IF-THEN instruction)
• Table branch

A number of instructions can cause branch operations:

• Branch instructions (e.g., B, BX)
• A data processing instruction that updates R15 (PC) (e.g., MOV, ADD)
• A memory read instruction that writes to PC (e.g., LDR, LDM, POP)
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 Program flow control
Function Call Instructions
• To call a function, the Branch and Link (BL) instruction or Branch and Link with eXchange
(BLX) instructions can be used (Table 5.32).
• They execute the branch and at the same time save the return address to the Link
Register (LR), so that the processor can branch back to the original program after the
function call is completed.
When these instructions are executed:
• The Program Counter is set to the branch target address.
• The Link Register (LR/R14) is updated to hold the return address, which is the address of
the instruction after the executed BL/BLX instruction.
• If the instruction is BLX, the Thumb bit in EPSR will also be updated using the LSB of the
register holding the branch target address.

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 Program flow control

Conditional Branch Instructions

Conditional branches are executed conditionally based on
the current value in APSR (N, Z, C, and V flags, as shown in Table 5.33).

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Program flow control

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 Program flow control

Conditional Branch Instructions

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 Program flow control

Conditional Branch Instructions

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 Program flow control

CMP R0, #1 ; compare R0 to 1

BEQ p2 ; if Equal, then go to p2
MOVS R3,#1 ;R3=1
B p3 ; go to p3
p2 ; label p2
MOVS R3, #2
p3 ; go to p3

….; other subsequence operations

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 Program flow control
CONDITIONAL EXECUTION- IF Then Instructions

• Besides conditional branches, Cortex-M3 and Cortex-M4 processors also

support conditional execution.
• After an IT (IF-THEN) instruction is executed, up to four of the subsequent
instructions can be conditionally executed based on the condition specified by
the IT instruction and the APSR value.
• An IT instruction block consists of an IT instruction, with conditional execution
details, followed by one to four conditional execution instructions.
• The conditional execution instructions can be data processing instructions or
memory access instructions.
• The last conditional execution instruction in the IT block can also be a
conditional branch instruction.
• The IT instruction statement contains the IT instruction opcode with up to an
additional three optional suffixes of “T” (then) and “E” (else), followed by the
condition to check against, which is the same as the condition symbol for
conditional branches.
• The “T”/”E” indicates how many subsequence instructions are inside the IT
instruction block, and whether they should or should not be executed if the
condition is met. Dr.K C R Nisha_Professor-ECE
Program flow control
CONDITIONAL EXECUTION- IF Then Instructions

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 Program flow control
CONDITIONAL EXECUTION- IF Then Instructions
Different combinations of “T” and “E” sequence are possible:
•Just one conditional execution instruction: IT
•Two conditional execution instructions: ITT, ITE
•Three conditional execution instructions: ITTT, ITTE, ITET, ITEE
•Four conditional execution instructions: ITTTT, ITTTE, ITTET, ITTEE, ITETT,
•ITETE, ITEET, ITEEE

Example

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 Program flow control
Example:

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 To find Factorial

AREA Prog2, CODE, READONLY

ENTRY ; mark first instruction to execute

MOV r6,#10 ; load 10 into r6

MOV r7,#1 ; if n=0, at least n!=1
Loop CMP r6,# 0
ITTT GT ; Start of IF Then Block
MULGT r7, r6, r7
SUBGT r6, r6, #1
BGT loop ; end of IF-THEN block
stop B stop ; stop program

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Euclid’s algorithm for computing the GCD of two
positive integers (a,b) can be written as
while (a != b) {
if (a>b) a=a – b;
else b=b – a; }

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 Table branch instructions
The Cortex-M3 and Cortex-M4 support two table branch instructions to
implement branch Tables:
TBB (Table Branch Byte) and TBH (Table Branch Half-word).
• The TBB is used when all the entries in the branch table are organized as a byte
array (offset from base address is less than 2x2^8=512 bytes)

• TBH is used when all the entries are organized as a half-word array (offset from base
address is less than 2x2^16=128K bytes).
The TBB instruction has the syntax:

TBB [Rn, Rm]

where Rn stores the base address of the branch table and Rm is the branch
table index.

The syntax of TBH is TBH [Rn, Rm, LSL #1]

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Table branch instructions

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 Saturation operations
• Saturation is commonly used in signal processing. For example, after certain operations
such as amplification, the amplitude of a signal can exceed the maximum
allowed output range.
• If the value is adjusted by simply cutting off the MSB bits, the resulted signal waveform
could be completely distorted as shown in Fig.
• The saturation operation reduces the distortion by forcing the value to the maximum
allowed value.
• The distortion still exists, but if the value does not exceed the maximum range by too
much it is less noticeable.

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Saturation operations

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 Saturation operations
• The Cortex-M3 processor supports two instructions that provide saturation
adjustment of signed and unsigned data.
• SSAT (for signed data) and USAT (for unsigned data).

For example, if a 32-bit signed value is to be saturated into a 16-bit signed value,
the following instruction can be used:
SSAT R1, #16, R0

For example, you can convert a 32-bit signed value to a 16-bit unsigned value
using:

USAT R1, #16, R0

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 Saturation operations
• Algorithms for handling speech data, adaptive control algorithms, and routines for filtering
are often sensitive to quantization effects when implemented on a micro- processor or
microcontroller.
• Saturated math is one such approach, especially when dealing with signed data.

• For example, consider a digital waveform in Figure 7.7, possibly the output of an adaptive
predictor, where the values are represented by 16-bit signed integers;
• the largest positive value in a register would be 0x00007FFF and the largest negative
value would be 0xFFFF8000.
• If this signal were scaled in some way, it’s quite possible that the largest value would
overflow, effectively flipping the MSB of a value so that a positive number suddenly
becomes negative, and the waveform might appear as in Figure 7.8.
• Using saturated math instructions, the signal would get clipped, and the waveform might
appear as in Figure 7.9, not correcting the values but at least keeping them within limits.

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Saturation operations

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Saturation operations

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Multiply and MAC Instructions

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Multiply and MAC Instructions

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Multiply and MAC Instructions

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Multiply and MAC Instructions

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Multiply and MAC Instructions

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Multiply and MAC Instructions

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Multiply and MAC Instructions

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 SIMD Instructions

For details refer text book chapter 5, table 5.53

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 Floating Point
In C programming, you can define data as floating point values. For example,
a value can be declared as single precision:
float pi = 3.141592F;

or double precision:
double pi = 3.1415926535897932384626433832795;

Floating point data allows the processor to handle a much wider data range
(compared to integers or fixed point data) as well as very small values.

To represent a tiny small number and large number using fewer number of
bits in computer memory----- Floating Point
Ex.
00000000005=0.5X10^-10 –> Small No.
50000000000=5X10^10 -> Large No.

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Floating Point

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Floating Point

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Floating Point

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Special registers- CONTROL Registers

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 Floating Point Registers
• The Cortex-M4 processor has an
optional floating point unit.
• In the architecture, the FPU is
viewed as a co-processor.
• To be consistent with other ARM
architectures, the floating point unit
is defined as Co-Processor #10 and
#11 in the CPACR programmer’s
model

• Provides additional registers for

floating point data processing, as
well as a Floating Point Status and
Control Register (FPSCR)

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 Floating Point Registers-Overview

• The FPU adds a number of

registers to the processor
system:
• CPACR (Co-processor Access
Control Register) in SCB
(System Control Block)
– The CPACR register allows you
to enable or disable the FPU. It
is located in address
0xE000ED88 and
• Floating point register bank
• Floating point Status and
Control Register (FPSCR)

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 Floating Point Registers-Overview
• Floating point register
bank
– The floating point register bank
contains thirty-two 32-bit
registers, which can be
organized as sixteen 64-bit
double-word registers
– S0 to S15 are caller saved
registers
– S16 to S31 are callee saved
registers.

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 Floating Point Registers
• S0 to S31/D0 to D15
• Each of the 32-bit registers S0 to S31 (“S” for single precision)
can be accessed using floating point instructions, or accessed
as a pair, in the symbol of D0 toD15 (“D” for double-
word/double-precision).
• For example, S1 and S0 are paired together to become D0,
and S3 and S2 are paired together to become D1.

Note: Floating point unit in the Cortex-M4 does not support

double precision floating point calculations
(Can use Floating point instructions for transferring double
precision data).
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 Floating Point Status Control Registers

• Floating point status and control register (FPSCR)

• The FPSCR contains various bit fields for a couple
of reasons:
– To define some of the floating point operation
behaviors
– To provide status information about the floating point
operation results

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Dr.K C R Nisha_Professor-ECE
 Floating Point Registers

Memory-mapped floating point unit control registers

• In addition to the floating point register bank and FPSCR, the
floating point unit also introduces several additional memory-
mapped registers into the system.
– For example, the Coprocessor Access Control Register (CPACR) is used
to enable or disable the floating point unit.
– By default the floating point unit is disabled to reduce power
consumption.

Note: Before using any floating point instructions, the floating point unit
must be enabled by programming the CPACR register

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 Moving data within the processor

For the Cortex-M4 processor with the floating point unit, one can also:
• Move data between a register in the core register bank and a register
in the floating point unit register bank
• Move data between registers in the floating point register bank
• Move data between a floating point system register (such as the FPSCR
• Floating point Status and Control Register) and a core register
• Move immediate data into a floating point register
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Memory Access Instructions-FPU

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Floating Point Instructions

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Floating Point Instructions

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Addition of Floating point numbers
Ex.1

Ex.2
LDR r0, =0xE000ED88 ; Read-modify-write LDR
LDR r1, [r0]
ORR r1, r1, #(0xF << 20) ; Enable CP10, CP11
STR r1, [r0]
VMOV.F s0, #0x3FC00000 ; single-precision 1.0
VMOV.F s1, s0
VADD.F s2, s1, s0 ; 1.5+1.5=??
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 Floating point numbers
Ex.3
;Function-------à X^3+2X-8

VMOV.F32 s0,#2.0 ; use s0 to hold 2.0 temporarily

VMUL.F32 s2, s1, s1 ; initial squaring of input
VMUL.F32 s3, s1, s0 ; multiply input by 2
VMOV.F32 s0, #8.0 ; use s0 to hold 8.0 temporarily
VMUL.F32 s2, s2, s1 ; finish cubing of input
VSUB.F32 s3, s3, s0 ; subtract off 8.0 from 2x
VADD.F32 s0, s2, s3 ; add in x^3 to return reg
BX lr ; return

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Data exchange from one memory
location to another

Address data
R0+R5 20000000 12345678 R3

Address data
R1+R5 20000050 1511 2522 R4

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 GCD- Lab manual
AREA MYCODE, CODE,READONLY
ENTRY
EXPORT START
START
LDR R0,=4
LDR R1,=2
LOOP CMP R0,R1
BEQ STOP
BLT LESS
SUBS R0,R0,R1
B LOOP
LESS SUB R1,R1,R0
B LOOP
STOP B STOP
END
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 To find Factorial

AREA Prog2, CODE, READONLY

ENTRY ; mark first instruction to execute

MOV r6,#10 ; load 10 into r6

MOV r7,#1 ; if n=0, at least n!=1
Loop CMP r6,# 0
ITTT GT ; Start of IF Then Block
MULGT r7, r6, r7
SUBGT r6, r6, #1
BGT loop ; end of IF-THEN block
stop B stop ; stop program

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 Reference
1. The Definitive Guide to ARM Cortex M3 and Cortex M4 Processors Joseph Yiu,3rd
Edition,2014 Elseiver
2. ARM Assembly Language Fundamentals and Techniques, William Hohl et.al, CRC press

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