R.M.K.

ENGINEERING COLLEGE
RSM NAGAR, KAVARAIPETTAI – 601 206

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

LAB MANUAL

Subject Code: EC8461

Subject Name: CIRCUIT DESIGN & SIMULATION LABORATORY

Lab-in-charge Year Coordinator Approved by

HOD/ECE

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 VISION OF THE INSTITUTE

❖ To be the most preferred destination in the country for pursuing education in Engineering
and it allied fields, at the undergraduate and post graduate levels, and for undertaking
doctoral research.
❖ To transform learners into achievers at the global level with the right attitude towards
changing societal needs.

MISSION OF THE INSTITUTE

M1: To develop the needed resources and infrastructure and to establish a conducive ambience
for the teaching- learning process
M2: To nurture in the students professional and ethical values and instill in them a spirit of
innovation and entrepreneurship
M3: To encourage in the students a desire for higher learning and research to equip them to
face the global challenges
M4: To provide opportunities for students to get the needed additional skills to make them
industry ready
M5: To interact with industries and other organizations to facilitate transfer of knowledge and
know- how

VISION OF THE DEPARTMENT

❖ To be one of the most sought after Centres of Excellence in the field of Electronics and
Communication Engineering by providing high quality education.
❖ To mould the students to compete internationally and to become excellent researchers and
innovators who can provide solution to societal issues.
MISSION OF THE DEPARTMENT

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 MISSION OF THE DEPARTMENT

M1: To provide the needed resources and infrastructure and to establish a conducive ambience
for the teaching-learning and research processes and to meet with the technological
developments.
M2: To create high quality professionals and entrepreneurs in the field of Electronics and
Communication Engineering with the right attitude to serve the society with ethical
values.
M3: To modernize the laboratories on par with industry standards and to collaborate with them
to improve the skill set of the students for providing innovative solutions to the industry.
M4: To provide a good ambience which encourages the students to pursue higher education.

PROGRAMME EDUCATIONAL OBJECTIVES

PEO 1: Graduates will develop the ability to identify, formulate and solve challenging
problems in the field of Electronics and Communication Engineering.
PEO 2: Graduates will acquire the professional skills that make them ready for immediate
employment or to pursue higher studies in the related disciplines.
PEO 3: Graduates will be molded with a strong educational foundation that prepares them for
leadership roles.
PEO 4: Graduates will show the understanding of impact of engineering solutions in the society
and also will be aware of contemporary issues.
PEO 5: Graduates will develop confidence to communicate their ideas effectively to industry
and society.

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OBJECTIVES:
• To gain hands on experience in designing electronic circuits
• To learn simulation software used in circuit design
• To learn the fundamental principles of amplifier circuits
• To differentiate feedback amplifiers and oscillators
• To differentiate the operation of various multivibrators

DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS

1. Series and Shunt feedback amplifiers-Frequency response, Input and output impedance
2. RC Phase shift oscillator and Wien Bridge Oscillator
3. Hartley Oscillator and Colpitts Oscillator
4. Single Tuned Amplifier
5. RC Integrator and Differentiator circuits
6. Astable and Monostable multivibrators
7. Clippers and Clampers

SIMULATION USING SPICE (Using Transistor):

1. Tuned Collector Oscillator

2. Twin -T Oscillator / Wein Bridge Oscillator
3. Double and Stagger tuned Amplifiers
4. Bistable Multivibrator
5. Schmitt Trigger circuit with Predictable hysteresis
6. Analysis of power amplifier

OUTCOMES:

On completion of this laboratory course, the student should be able to:

• Analyze various types of feedback amplifiers
• Design oscillators, tuned amplifiers, wave-shaping circuits and multivibrators
• Design and simulate feedback amplifiers, oscillators, tuned amplifiers, wave-shaping circuits
and multivibrators using SPICE Tool.

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 INDEX

Ex. No Date Name of the Experiment Page No Marks Signature

Current Series (Series-Series) feedback amplifier 9

Voltage Series (Series-Shunt) feedback amplifier 17

Voltage Shunt (Shunt-Shunt) feedback amplifier 23

Current Shunt (Shunt-Series) feedback amplifier 27

RC Phase shift Oscillator 31

Wien Bridge Oscillator 37

LC (Hartley & Colpitt’s) Oscillator 41

Single tuned amplifier 48

RC Integrator & Differentiator 55

Astable Multivibrator 59

Monostable Multivibrator 65

Clippers and Clampers 71

Simulation Experiments

Simulation of Tuned Collector Oscillator 83

Simulation of Wien Bridge Oscillator 85

Simulation of Double Tuned Oscillator 87

Simulation of transistor based Bistable 89

Multivibrator

Simulation of Schmitt Trigger 91

Content Beyond the Syllabus

Class A Power Amplifier 95

Class B Power Amplifier 101

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Circuit Diagram

Amplifier without Feedback

VCC = 12 V

R1
61 K RC
4.7 K
C
_ + B
BC 107
1 F
E
V0
AFO + C
R2 RE E
50 mV 10 K 100 µF
1 K

Page 8
Ex.No Current Series (Series-Series) Feedback Amplifier

Date:
Aim:

To design a current series feedback amplifier circuit and determine the frequency
response, gain, bandwidth, input and output impedance with and without feedback.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 1

2 Resistors 61 KΩ, 10 KΩ, 1 KΩ, Each 1

4.7 KΩ

3 Capacitors 1 µF, 100 µF Each 1

4 Regulated Power Supply (0 – 30) V 1

5 Function Generator (0 – 1 MHz) 1

6 CRO (0 – 20 MHz) 1

7 Bread board 1

8 Connection Wires As required

Design:

Assume IC = 1 mA, VR E = 1V, R2 = 10 KΩ, VCC = 12V

To find RE:

VR E = IERE

VR E 1V
 RE = = = 1 K
IE 1 mA

Page 9
 Amplifier with Feedback
VCC = 12 V

R1
61 K RC
4.7 K
C
_ + B
BC 107
1 F
E
V0
AFO R2 RE
50 mV 10 K 1 K

Model Graph:
Gain (dB)
Without feedback

0.707 A1

With feedback

0.707 A2

f(Hz)
fL2 fL1 fH1 fH2

Page 10
To find R1:

 R2 
VR 2 = VCC  
 R1 + R2 
 

 R1 
I B   drop is neglected compared to VBE and VRE drops. It is this neglecting that
 R1 + R2 
results in β independent voltage divider bias design.

Applying KVL to the input

VR2 – VBE – VRE = 0

VR2 = VBE + VRE = 0.7 + 1 = 1.7 V

 R2 
VR 2 = VCC  
 R1 + R2 
 

 10 K 
 1.7 = 12  
 R1 + 10 K 

 R1 = 61 KΩ

To find RC :

Drop across RE is assumed to be 1V. The drop across VCE with a supply of 12 V is given by 12 –
1 = 11V. It is equal to 11 / 2 = 5.5V

Now the voltage across the resistance RC is 5.5 V

VC = 5.5 V, IC = 1 mA

VC 5.5
RC = = = 5.5 KΩ
I C 1 mA

Instead of using 5.5 KΩ, we can use a standard value of 4.7 KΩ

 RC = 4.7 KΩ

Page 11
Tabular Column for without feedback Vi = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vi Gain(dB) = 20 log V0 / Vi

Page 12
Theory:

Depending on the relative polarity of the signal being feedback in to a circuit, one may
have negative or positive feedback. If feedback is of opposite polarity to input signal negative
feedback results. While negative feedback results in reduced overall gain, a number of
improvements are obtained like higher impedance, better stabilized voltage gain etc., are
obtained.

In the circuit, the feedback signal is the voltage across RE and the sampled signal is the
load current. Hence this is a case of current series feedback. This topology stabilizes the
transconductance Gm. The gain of the amplifier decreases as result of the negative feedback
applied, whereas its bandwidth is improved.

Procedure:

1. Connections are given as per the circuit diagram.

2. An input signal of 50 mV is fed to the circuit, corresponding output is observed in the
CRO.
3. The readings of the output voltage (from the CRO) are noted by varying the frequency
from (0 – 1 MHz).
4. Gain is calculated as the ratio of output voltage to input voltage.
5. Graph is plotted between frequency and gain in dB in a semi log graph sheet and
bandwidth is calculated.

Bandwidth

a. Plot the frequency response.

b. Identify the maximum gain region.
c. Drop a horizontal line by -3dB.
d. The -3dB line intersects the frequency response plot at two points.
e. The lower intersecting point -3dB line with the frequency response plot gives the
lower cut-off frequency.
f. The upper intersecting point -3dB line with the frequency response plot gives the
upper cut-off frequency.
g. The difference between the upper cut-off frequency and the lower cut-off frequency is
called the Bandwidth. Thus Bandwidth = fH - fL

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Tabular Column for with feedback Vi = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vi Gain(dB) = 20 log V0 / Vi

Page 14
Result:

Thus the frequency response of series – series feedback amplifier with feedback and
without feedback is plotted.

Without Feedback With Feedback

Gain (Mid-band)

Bandwidth

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 Circuit Diagram

VCC = 12 V

R1
61 K
1 F
_ BC 107
+

50 mV R2
AFO 10 K RE
V0
1 K

Model Graph:

Gain A
(dB)
Amax
0.707 A (3dB)

B.W = fH - fL

f (Hz)
fL fH

Page 16
Ex.No Voltage Series (Series-Shunt) Feedback Amplifier

Date:
Aim:

To design a voltage series feedback amplifier and determine the frequency response,
gain, bandwidth, input and output impedance.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 1

2 Resistors 61 KΩ, 10 KΩ, 1 KΩ Each 1

3 Capacitors 1 µF 1

4 Regulated Power Supply (0 – 30) V 1

5 Function Generator (0 – 1 MHz) 1

6 CRO (0 – 20 MHz) 1

7 Bread board 1

8 Connection Wires As required

Design:

Assume IC = 1 mA, VR E = 1V, R2 = 10 KΩ, VCC = 12V

To find RE:

VR E = IERE

VR E 1V
 RE = = = 1 K
IE 1 mA

To find R1:

 R2 
VR 2 = VCC  
 R1 + R2 
 

Page 17
Tabular Column Vi = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vi Gain(dB) = 20 log V0 / Vi

Page 18
  R1 
I B   drop is neglected compared to VBE and VRE drops. It is this neglecting that results
 R1 + R2 
in β independent voltage divider bias design.

Applying KVL to the input

VR2 – VBE – VRE = 0

VR2 = VBE + VRE = 0.7 + 1 = 1.7 V

 R2 
VR 2 = VCC  
 R1 + R2 
 

 10 K 
 1.7 = 12  
 R1 + 10 K 

 R1 = 61 KΩ

Theory:

Depending on the relative polarity of the signal being feedback in to a circuit, one may
have negative or positive feedback. If feedback is of opposite polarity to input signal negative
feedback results. While negative feedback results in reduced overall gain, a number of
improvements are obtained like higher impedance, better stabilized voltage gain etc., are
obtained.

The circuit given has the voltage series feedback. The feedback signal as well as the
output signal is the voltage across the emitter resistance RE, which gives rise to this type of
feedback. It increases input resistance and decreases output resistance.

Procedure:

1. Connections are given as per the circuit diagram.

2. An input signal of 50 mV is fed to the circuit, corresponding output is observed in the
CRO.
3. The readings of the output voltage (from the CRO) are noted by varying the frequency
from (0 – 1 MHz).
4. Gain is calculated as the ratio of output voltage to input voltage.
5. Graph is plotted between frequency and gain in dB in a semi log graph sheet and
bandwidth is calculated.

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 Bandwidth

a. Plot the frequency response.

b. Identify the maximum gain region.
c. Draw a horizontal line by -3dB.
d. The -3dB line intersects the frequency response plot at two points.
e. The lower intersecting point -3dB line with the frequency response plot gives the
lower cut-off frequency.
f. The upper intersecting point -3dB line with the frequency response plot gives the
upper cut-off frequency.
g. The difference between the upper cut-off frequency and the lower cut-off frequency is
called the Bandwidth. Thus Bandwidth = fH - fL

Result:

Thus the frequency response of voltage – series feedback amplifier is plotted.

Gain (Mid-band) = ______________

Bandwidth = ______________

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 Circuit Diagram

VCC = 12 V

RC 4 KΩ

R’

40 KΩ
RS
BC 107
10 KΩ

VS V0

50mV

Model Graph

Gain A
(dB)

Amax
0.707 A (3dB)

B.W = fH - fL

f (Hz)
fL fH

Page 22
Ex.No Voltage -Shunt (Shunt-Shunt) Feedback Amplifier

Date:
Aim:

To determine the frequency response, gain, bandwidth, input and output impedance of
voltage shunt feedback amplifier.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 1

2 Resistors 40 KΩ, 10 KΩ, 4 KΩ Each 1

3 Regulated Power Supply (0 – 30) V 1

4 Function Generator (0 – 1 MHz) 1

5 CRO (0 – 20 MHz) 1

6 Bread board 1

7 Connection Wires As required

Theory:

Depending on the relative polarity of the signal being feedback in to a circuit, one may
have negative or positive feedback. If feedback is of opposite polarity to input signal negative
feedback results. While negative feedback results in reduced overall gain, a number of
improvements are obtained like higher impedance, better stabilized voltage gain etc., are
obtained.

The circuit given has the voltage shunt feedback. The feedback signal is the current
through the feedback resistor and the output signal is the voltage across the collector terminal,
which gives rise to this type of feedback. It decreases the input resistance as well as the output
resistance.

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Tabular Column Vs = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vs Gain(dB) = 20 log V0 / Vs

Page 24
Procedure:

1. Connections are given as per the circuit diagram.

2. An input signal of 50 mV is fed to the circuit, corresponding output is observed in the
CRO.
3. The readings of the output voltage (from the CRO) are noted by varying the frequency
from (0 – 1 MHz).
4. Gain is calculated as the ratio of output voltage to input voltage.
5. Graph is plotted between frequency and gain in dB in a semi log graph sheet and
bandwidth is calculated.

General Procedure for Calculation of Bandwidth:

a. Plot the frequency response.

b. Identify the maximum gain region.
c. Draw a horizontal line by -3dB.
d. The -3dB line intersects the frequency response plot at two points.
e. The lower intersecting point -3dB line with the frequency response plot gives the lower
cut-off frequency.
f. The upper intersecting point -3dB line with the frequency response plot gives the upper
cut-off frequency.
g. The difference between the upper cut-off frequency and the lower cut-off frequency is
called the Bandwidth. Thus Bandwidth = fH - fL

Result:

Thus the frequency response of voltage – shunt feedback amplifier is plotted.

Gain (Mid-band) = ______________

Bandwidth = ______________

Page 25
 Circuit Diagram

VCC = 12 V

RC1 3 KΩ RC2 500 Ω

RS
BC 107 BC 107
1.2 KΩ
R’

VS 1.2 KΩ V0

50 mV Re 50 Ω

Model Graph

Gain A
(dB)
Amax
0.707 A (3dB)

B.W = fH - fL

f (Hz)
fL fH

Page 26
Ex.No Current -Shunt (Shunt-Series) Feedback Amplifier

Date:
Aim:

To determine the frequency response, gain, bandwidth, input and output impedance of
current shunt feedback amplifier.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 2

2 Resistors 3 KΩ, 500Ω, 50Ω Each 1

1.2 KΩ 2

3 Regulated Power Supply (0 – 30) V 1

4 Function Generator (0 – 1 MHz) 1

5 CRO (0 – 20 MHz) 1

6 Bread board 1

7 Connection Wires As required

Theory:

Depending on the relative polarity of the signal being feedback in to a circuit, one may
have negative or positive feedback. If feedback is of opposite polarity to input signal negative
feedback results. While negative feedback results in reduced overall gain, a number of
improvements are obtained like higher impedance, better stabilized voltage gain etc., are
obtained.

The circuit given has the current shunt feedback. The feedback signal is the current
through the feedback resistor connected between the emitter of second transistor and the base of
the first transistor and the output signal is the voltage across the collector terminal with respect to
ground, which gives rise to this type of feedback. It decreases the input resistance and increases
the output resistance.

Page 27
Tabular Column Vs = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vs Gain(dB) = 20 log V0 / Vs

Page 28
Procedure:

1. Connections are given as per the circuit diagram.

2. An input signal of 50 mV is fed to the circuit, corresponding output is observed in the
CRO.
3. The readings of the output voltage (from the CRO) are noted by varying the frequency
from (0 – 1 MHz).
4. Gain is calculated as the ratio of output voltage to input voltage.
5. Graph is plotted between frequency and gain in dB in a semi log graph sheet and
bandwidth is calculated.

General Procedure for Calculation of Bandwidth:

a. Plot the frequency response.

b. Identify the maximum gain region.
c. Draw a horizontal line by -3dB.
d. The -3dB line intersects the frequency response plot at two points.
e. The lower intersecting point -3dB line with the frequency response plot gives the lower
cut-off frequency.
f. The upper intersecting point -3dB line with the frequency response plot gives the upper
cut-off frequency.
g. The difference between the upper cut-off frequency and the lower cut-off frequency is
called the Bandwidth. Thus Bandwidth = fH - fL

Result:

Thus the frequency response of current – shunt feedback amplifier is plotted.

Gain (Mid-band) = ______________

Bandwidth = ______________

Page 29
Circuit Diagram

VCC = 12 V

RC
61 K R1 4.7 K

V0
47 F
_ + BC 107

C2
R2
10 K 1 K C1 100 F

0.01 F 0.01 F 0.01 F

C C C
10 K 10 K 10 K R
3
R3 R3

Page 30
Ex.No RC Phase Shift Oscillator

Date:
Aim:

To design a RC Phase shift oscillator and to obtain the sine wave of desired frequency.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 1

2 Resistors 61 KΩ, 1 KΩ, 4.7 KΩ Each 1

10 KΩ 4

3 Capacitors 100 µF, 47 µF Each 1

0.01 µF 3

4 Regulated Power Supply (0 – 30) V 1

5 CRO (0 – 20 MHz) 1

6 Bread board 1

7 Connection Wires As required

Design:

Assume IC = 1 mA, VR E = 1V, R2 = 10 KΩ, VCC = 12V, f = 650 Hz, C = 0.01 µF

To find RE:

VR E = IERE

VR E 1V
 RE = = = 1 K
IE 1 mA

To find R1:

 R2 
VR 2 = VCC  
 R1 + R2 
 

Page 31
Model Graph :

Amplitude (V)

Time (ms)

Observation:

Amplitude Time Period T Frequency (1/T)

(V) (ms) (Hz)

Page 32
  R1 
I B   drop is neglected compared to VBE and VRE drops. It is this neglecting that results
 R1 + R2 
in β independent voltage divider bias design.

Applying KVL to the input

VR2 – VBE – VRE = 0

VR2 = VBE + VRE = 0.7 + 1 = 1.7 V

 R2 
VR 2 = VCC  
 R1 + R2 
 

 10 K 
 1.7 = 12  
 R1 + 10 K 

 R1 = 61 KΩ

To find R3:

1
f =
2  RC 6
1
R =
2  fC 6
1
= = 9.996 K
2  x 650 x 0.01 x 10 −6 x 6

 R3 ≈ 10 KΩ

Theory:

An oscillator is a device that can be used to generate an alternating voltage or current. It

is also a converter that converts DC to AC which is at 0 frequency, to higher frequency. RC
phase shift oscillator produces sinusoidal oscillations and hence a sine wave. Amplifier when
provided with a +ve feedback forms an oscillator and the phase shift between input signal and
the feedback signal must be ‘zero’ or an integral multiple of 180.

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Page 34
 In the circuit diagram the amplifier is followed by three section of RC phase shift
oscillator network. The output of the RC network produces a phase shift of 180° and the
amplifier provides another phase shift of 180°. The resistors R1, R2 combination produces DC
Emitter bias and RE, CE provides temperature stability and ac signal degeneration. The
1
component resistor and capacitor are selected to obtain the desired frequency, f = .
2 RC 6

The R and C are selected in such a way that the RC combination phase angle be 60°, so
that using a ladder network of 3 RC sections a phase shift of 180° is obtained between the input
and output. This provides a total phase shift of 360° and hence a sine wave of desired frequency
is obtained. Thus the RC phase shift oscillator serves as a frequency determining network.

Procedure:

1. Connections are given as per the circuit diagram.

2. The power supply is turned ON.
3. The output is taken across the collector of the transistor.
4. The output sine wave is viewed in the CRO.
5. The amplitude and the time period is observed from the CRO and the frequency is
calculated.
6. The sine wave is plotted on the graph.

Result:

Thus the RC phase shift oscillator is designed and the sine wave is obtained as output.

Desired frequency (Theoretical) = __________________

Obtained frequency (Practical) = __________________

Page 35
Circuit diagram

VCC = 12 V

R8
2.2 K
R5
R2 R4 100 K
100 K 2.2 K
C1
10 F
C2
BC 107 0.01 F

BC 107
R9
15.9 K

R6 R7
R1 R3 32 K 1 K
32 K 1 K R10 C3
15 K 0.01 F

Page 36
Ex.No Wien Bridge Oscillator

Date:
Aim:

To design and construct Wien bridge oscillator of frequency of 10 KHz and to plot the
sinusoidal waveform.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 2

100 KΩ, 2.2 KΩ, 32 KΩ,1 KΩ Each 2

2 Resistors
15.9 KΩ, 15 KΩ Each 1

0.01 µF 2
3 Capacitors
10 µF 1

4 Regulated Power Supply (0 – 30) V 1

5 CRO (0 – 20 MHz) 1

6 Bread board 1

7 Connection Wires As required

Design:

Assume C = 0.01 µF and f0 = 10 KHz

1
The frequency of oscillation of wien bridge oscillator is given by f 0 =
2 RC
1
10 x 10 3 =
2 x R x 0.01 x 10 −6
 R = 1.59 KΩ ≈ 1.5 KΩ

To avoid loading effect R1 = 10R

Page 37
Model waveform:

Amplitude (V)

Time (ms)

Observations:

Amplitude Time Period (ms) Frequency (Hz)

Page 38
  R1 = 10 x 1.5 KΩ = 15 KΩ
For the loop gain AV to be greater than 1, Rf should be equal to 2R1
 Rf = 2R1 = 2 x 15 KΩ = 30 KΩ

Theory:
The closed loop circuit of the wien bridge oscillator gives the positive feedback. At f0, β
= 1/3 therefore for sustained oscillation, the amplifier must have a gain of precisely 3. However
from particular point of view, AV may be slightly less or greater than 3. To compensate the
change an adaptive negative feedback is used. Since the amplifier works as a non-inverting
amplifier, the feedback network will not provide any phase shift.
The circuit can be viewed as wien bridge with a series RC network in one arm and a
parallel RC network in the adjoining arm. Resistors R1 and Rf are connected in the remaining
two arms. The condition of zero phase shift is obtained by balancing the bridge.

Procedure:
1. Construct the circuit as shown in the circuit diagram.
2. Switch ON the power supply and observe the waveform in the CRO.
3. Note the values of amplitude and frequency.
4. Plot the curve on the graph.
5. Verify the results with the design.

Result:

Thus wien-bridge oscillator is designed and sine wave is obtained as output.

Desired frequency (Theoretical) = __________________

Obtained frequency (Practical) = __________________

Page 39
Circuit Diagram

Colpitts Oscillator

VCC = 12 V

R1 RC
61 K 4.7 K

C V0
0.1 F
0.03 F B
BC 107

+
R2 RE CE
10 K 1 K - 100 µF

0.01 F 0.01 F

C1 C2

0.1 mH

Page 40
Ex.No LC Oscillator

Date:
Aim:

To design Colpitts oscillator and Hartley oscillator to get sine wave output of desired
frequency.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 1

2 Resistors 10 KΩ, 61 KΩ, 1KΩ, 100 KΩ, 12 KΩ, Each 1

270 Ω , 4.7 KΩ

3 Capacitors 0.01 100 µF, 0.03 µF, 22 µF Each 1

0.02 µF 2
0.1 µF 3

4 Inductor Decade Inductor Box (0.1 mH) 1

5 Regulated Power Supply (0 – 30) V 1

6 CRO (0 – 20 MHz) 1

7 Bread board 1

8 Connection Wires As required

Design:

Colpitts Oscillator:

Assume IC = 1 mA, VR E = 1V, R2 = 10 KΩ, VCC = 12V

To find RE:

VR E = IERE

VR E 1V
 RE = = = 1 K
IE 1 mA

Page 41
Model Graph :

Amplitude (V)

Time (ms)

Page 42
To find R1:

 R2 
VR 2 = VCC  
 R1 + R2 
 

 R1 
I B   drop is neglected compared to VBE and VRE drops. It is this neglecting that results
 R1 + R2 
in β independent voltage divider bias design.

Applying KVL to the input

VR2 – VBE – VRE = 0

VR2 = VBE + VRE = 0.7 + 1 = 1.7 V

 R2 
VR 2 = VCC  
 R1 + R2 
 

 10 K 
 1.7 = 12  
 R1 + 10 K 

 R1 = 61 KΩ

To find RC :

Drop across RE is assumed to be 1V. The drop across VCE with a supply of 12 V is given by 12 –
1 = 11V. It is equal to 11 / 2 = 5.5V

Now the voltage across the resistance RC is 5.5 V

VC = 5.5 V, IC = 1 mA

VC 5.5
RC = = = 5.5 KΩ
I C 1 mA

Instead of using 5.5 KΩ, we can use a standard value of 4.7 KΩ

 RC = 4.7 KΩ

To find inductance L:

Assume f = 250 KHz, C1 = C2 = 0.01 µF

Page 43
Hartley oscillator

VCC = 10 V

100 KΩ 4.7KΩ

0.1 F
V0
0.1 F
BC 107

12KΩ 270Ω 22 F

1 mH 0.8 mH

0.1 F

Page 44
 1 C1 . C 2
f0 = , Ceq =
2 LC eq C1 + C 2

1 C1 + C 2
f0 =
2 L C1 C 2
 L = 0.1 mH

 L = 0.1 mH

Hartley Oscillator:

f0 = 12 KHz, assume C = 0.1 µF

1
f0 = , where Leq = L1 + L2
2 Leq .

1
12 x 10 3 =
2 Leq x 0.1 x 10 −6

 Leq = 11.8 mH

Let L1 = 1 mH and L2 = 0.8 mH

Theory:

The LC oscillator uses L and C as the element which forms tank circuit or oscillatory
circuit. This is also referred to as resonating tuned circuits. L and C are connected in parallel
when capacitor gets charged, the energy gets stored as electrostatic energy. After charging, it
discharges through L. When capacitor is fully discharged, maximum current flows through the
circuit.

The LC oscillator along with amplifier supplies this loss of energy at proper times. The
care of proper polarity is taken by feedback network. Thus LC oscillator is obtained. Due to
energy which is lost, the oscillations are maintained hence called sustained oscillations, or
undamped oscillations.

The resistors R1, R2 and RE provide the necessary d.c bias to the transistor. The feedback
network consisting of capacitors C1 and C2 and an inductor L determines the frequency of the
oscillator.

Page 45
Observation:

Amplitude Time Period T Frequency (1/T)

Oscillator
(V) (ms) (Hz)

Colpitt

Hartley

Page 46
Procedure:

1. Connect the circuit as per the circuit diagram.

2. The power supply is turned ON.
3. The output is taken across the collector of the transistor.
4. The output sine wave is viewed in the CRO.
5. The amplitude and the time period is observed from the CRO and the frequency is
calculated.
6. The sine wave is plotted on the graph.

Result:

Thus the Colpitt’s oscillator and Hartley oscillator are designed and the sine wave is
obtained as output.

Desired Frequency Practical Frequency

Oscillator (Theoretical) (Obtained)

Colpitt

Hartley

Page 47
Circuit Diagram

Single tuned Amplifier

VCC = 12 V

C L
R1 1 F 6 mH
61 K

_ + B
BC 107
47 F
E
V0
AFO R2 CE
RE
50 mV 10 K - 100 µF
1 K

Page 48
Ex.No Single tuned Amplifier

Date:
Aim:

To design and test a single tuned amplifier and determine the frequency response of an
amplifier.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 1

2 Resistors 61 KΩ, 10 KΩ, 1KΩ Each 1

3 Capacitors 1 µF, 100 µF, 47 µF Each 1

4 Decade Inductor Box (DIB) (1 – 100) mH 1

5 Regulated Power Supply (0 – 30) V 1

6 CRO (0 – 20 MHz) 1

7 Function Generator (0 – 1 MHz) 1

8 Bread board 1

9 Connection Wires As required

Design:

Assume IC = 1 mA, VR E = 1V, R2 = 10 KΩ, VCC = 12V

To find RE:

VR E = IERE

VR E 1V
 RE = = = 1 K
IE 1 mA

Page 49
Model Waveform

Gain (dB)

Amax
-3 dB

Frequency ( Hz)
fL f0 fH

Page 50
To find R1:

 R2 
VR 2 = VCC  
 R1 + R2 
 

 R1 
I B   drop is neglected compared to VBE and VRE drops. It is this neglecting that results
 R1 + R2 
in β independent voltage divider bias design.

Applying KVL to the input

VR2 – VBE – VRE = 0

VR2 = VBE + VRE = 0.7 + 1 = 1.7 V

 R2 
VR 2 = VCC  
 R1 + R2 
 

 10 K 
 1.7 = 12  
 R1 + 10 K 

 R1 = 61 KΩ

To find inductance L:

Assume f = 2 KHz, C = 1 µF

1
f0 =
2 LC
1
2 x 10 3 =
2 L x 1 x 10 −6
 L = 6.322 mH  6 mH

 L = 6 mH

Page 51
Tabular Column Vi = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vi Gain(dB) = 20 log V0 / Vi

Page 52
Theory:

Amplifiers, which amplify a specific frequency or narrow band of frequency, is called

tuned amplifier. Tuned amplifiers are used for the amplification of radio frequencies. The tuned
circuit offers very high impedance at resonant frequency and very small impedance at other
frequencies. If the signal has same frequency as resonant frequency of LC circuit, large
amplification will result. When signals of many frequencies are present at the input it will select
and strongly amplify the signals of resonant frequency while reject the others. Thus they are used
in radio receivers.

The circuit consists of transistor amplifier containing a parallel band circuit as collector load.
The values of capacitors and inductors of the tuned circuit are so selected that its resonant
frequency is the frequency to be amplified.

Procedure:

1. Connect the circuit as per the circuit diagram.

2. Set the input voltage as 50 mV using generator.
3. Keeping the input voltage constant vary the frequency from 1 Hz to 1 MHz in regular
steps and note down the corresponding output voltage.
4. Plot the gain (dB) vs frequency on a log scale.
5. The mid frequency voltage gain is divided by √2 and these points are marked in the
frequency response curve.
6. The high frequency point is called upper 3dB point. The lower frequency point is called
lower 3 dB point. The difference between upper 3dB and lower 3dB point in frequency
scale gives the bandwidth of the amplifier.

Result:

Thus the single tuned amplifier was designed and the frequency response was obtained.

Bandwidth = _________________

Resonant frequency = _________________

Page 53
Circuit Diagram

Differentiator
0.1 F

10 V
1 kHz V0
10 KΩ R

Model Waveform

Voltage

Output
Input

5V

-5V

Page 54
Ex.No RC Integrator and Differentiator

Date:
Aim:

To design Integrator and Differentiator and verify the waveforms.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Resistors 10 KΩ 1

2 Capacitors 0.1 µF 1

3 CRO (0 – 20 MHz) 1

4 Function Generator (0 – 1 MHz) 1

5 Bread board 1

6 Connection Wires As required

Design:

Assume f = 1 KHz, C = 0.1 µF

T = τ = RC

T = 1 / f = 1 ms

 1 x 10 −3
R= = = 10 K
C 0.1 x 10 −6

Theory:

Integrator

The integrating circuit consists of a series resistor and a shunt capacitor. This passes low
frequencies of the input and attenuates high frequencies because the reactance of the capacitor C

Page 55
Circuit Diagram

Integrator
10 KΩ
R

10 V 0.1 F C V0
1 kHz

Model Waveform

Voltage
Input

5V

Output

0 t (ms)

-5V

Observation

Input Output

Amplitude Time Period Amplitude Time Period

(V) (ms) (V) (ms)

Differentiator

Integrator

Page 56
decreases with increasing frequency. At very high frequencies the capacitor acts as a virtual short
circuit and the output falls to zero. Hence this circuit is called low-pass filter.

It gives an output waveform similar to the time integral of the input waveform. i.e.,
1
RC 
V0 = Vi dt and hence, the circuit is called integrator. In general, the time constant of the

integrating circuit shall be large compared with the period of the input signal.

Differentiator

It consists of a series capacitor and a shunt resistor. Since the reactance of a capacitor is
1
XC = , XC decreases with increasing frequency (f). Therefore, at very high frequencies,
2 fC
the capacitor acts as a short circuit and all the higher frequency components appear at the output
with less attenuation than the lower frequency components. Hence this circuit is called high-pass
filter.

With reducing time constant, the pulse at the output becomes narrower with negligible
sag. If the time constant is reduced sufficiently, the output will be simply a series of alternate
positive and negative spikes. Mathematically, such a waveform is the first derivative of the input
dV
waveform i.e. V0 = RC i and hence, the circuit is called differentiator. In general, the time
dt
constant of the differentiating circuit shall be small compared to the period of the input signal.

Procedure:

1. Connect the circuit as per the circuit diagram.

2. Apply the 1 KHz wave input of 10 V.
3. Observe the waveform as shown in the figure.
4. Plot the graph between amplitude and time period.

Result:

Thus the Differentiator and Integrator have been designed and the output has been verified.

Page 57
Circuit Diagram

Astable Multivibrator

VCC = 12 V

RC1 R1 R2 RC2
4.7 KΩ 72 KΩ 72 KΩ 4.7 KΩ
C1 C2
VC1 _ _ + VC2
+
Q1 0.01 F 0.01 F Q2
BC 107 BC 107

Page 58
Ex.No Astable Multivibrator

Date:
Aim:

To design an Astable multivibrator to get a square waveform and to calculate its TON and
TOFF.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 2

2 Resistors 72 KΩ, 4.7 KΩ Each 2

3 Capacitors 0.01 µF 2

4 Regulated Power Supply (0 – 30) V 1

5 CRO (0 – 20 MHz) 1

6 Bread board 1

7 Connection Wires As required

Design:

Assume VCC = 12 V, hfe = 20, f = 1 KHz, IC = 2.5 mA, VCE(Sat) = 0.2 V

To find RC

Applying KVL to the outside loop we have

VCC – ICRC – VCE(Sat) = 0

VCC − VCE ( Sat)

 RC =
IC
12 − 0.2
= = 4.7 K
2.5 x 10 −3

 RC = RC1 = RC2 = 4.7 KΩ

Page 59
Model Waveform

Amplitude (V)

TON
VC1

TOFF
0 t (ms)

Amplitude (V)

TON
VC2
TOFF

0 t (ms)

Page 60
To find R

T = 1.38 RC

T = 1 ms, Assume C = 0.01 µF

T
R =
1.38 x C
1 x 10 −3
= = 72.463 K  72 K
1.38 x 0.01 x 10 −6

 R = R1 = R2 = 72 KΩ

Theory:

An astable multivibrator also known as free running multivibrator generates square

wave of known period. It does not have any permanent stable state. It has two quasi stable states.

The astable multivibrator may be thought of as two common emitter amplifying stages.
Each stage provides a positive feedback through a capacitor at the input of the other. Since the
amplifier stage produces a phase shift of 180°, the total phase shift is 360° or 0°. The feedback is
the positive feedback. Due to capacitive coupling none of the transistors can remain permanently
in cutoff or saturation. Instead the circuit has two quasi table state and it makes periodic
transitions between the two stages.

Page 61
Observation

Output Amplitude (V) Time Period (ms)

TON =
VC1
TOFF =

TON =
VC2
TOFF =

VB1

VB2

Page 62
Procedure:

1. The circuit connections are given as per the circuit diagram.

2. The supply is switched ON.
3. The output is taken at the collector of Q1 and Q2.
4. The amplitude and time period of TON and TOFF is calculated separately for the obtained
square waveform.
5. The graph is drawn for the measured values.

Result:

Thus an astable multivibrator is designed to get a square wave and its TON and TOFF are
calculated and a graph is drawn.

Page 63
Circuit Diagram

Monostable Multivibrator

VCC = 6 V

R
RC1 950Ω 0.0001F RC2 950Ω
17 KΩ
C C1
VC1 VC2
0.01 F R1=7.8 KΩ
Q1 Q2
BC 107 BC 107

R2 7.3 KΩ
0.01 C2
F
_
VBB = - 1.5
Input trigger +
pulse V

Page 64
Ex.No Monostable Multivibrator

Date:
Aim:

To design a monostable multivibrator for developing an output pulse of 140 µs duration.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Transistor BC 107 2

2 Resistors 7.3 KΩ, 17 KΩ, 7.8KΩ Each 1

950 Ω 2

3 Capacitors 0.01 µF 2
0.02 0.00001 µF 1

4 Dual Regulated Power Supply (0 – 30) V 1

5 CRO (0 – 20 MHz) 1

6 AFO (0 – 1 MHz) 1

7 Bread board 1

8 Connection Wires As required

Design:

Assume IC(sat) = 6 mA, hFEmin = 20, VCC = 6V, VBB = - 1.5 V

To find RC1 & RC2:

VCC − VCE ( sat) 6 − 0 .3

RC1 = RC 2 = =
I C ( sat) 6 x 10 −3

 RC1 = RC2 = 950 Ω

Page 65
Model Waveform

Amplitude
(Volts)

Input Trigger wave

TON
TOFF
t (ms)

Amplitude
(Volts) Output Pulse
wave

TON

TOFF

t (ms)

Page 66
To find R:

I C ( sat) 6 x 10 −3
I B 2 ( sat) = = = 0.3 mA
hFE (min) 20

Also, IB1(sat) = 0.3 mA

VCC − V BE ( sat) 6 − 0.7

R= =
I B 2 ( sat) 0.3 x 10 −3

 R = 17.67 KΩ

To find C:

At quasi-stable state, Q1 is ON and Q2 is OFF

T = 0.693 RC

T 140 x 10 −6
C = =
0.693 R 0.693 x 17.67 x 10 3

 C = 0.0114 µF

To find R1 & R2:

Assume IB1(sat) = IR2

Therefore, IR1 = IB1(sat) + IR2 = 0.3 mA + 0.3 mA = 0.6 mA

VCC = VBE(sat) + IR1 (RC2 + R1)

6 = 0.7 + 0.6 x 10-3 (950 + R1)

VCC − VBE ( sat)

R1 = − RC 2
I R1
Therefore,
6 − 0.7
= − 950
0.6 x 10 −3

 R1 = 7.883 K Ω

Page 67
Observation

Time Period (ms)

Amplitude (Volts)
TON (ms) TOFF (ms)

Input Trigger

Output Pulse wave

Page 68
 VBE ( sat) − ( − VBB )
R2 =
I R2
0.7 + 1.5
=
0.3 x 10 −3

 R2=7.33 K Ω

To find C1:

The speed up capacitor C1 is chosen such that R1C1 = 1 µs and hence,

10 −6
C1 =
7.833 x 10 3

 C1 = 126.9 pF

Theory:

A monostable multivibrator has a stable state and quasi stable state. An external trigger
circuit is required to be applied to approximate point in the quasi stable state. The circuit remains
in the quasi stable state for the predetermined length of time and then changes to the stable state
automatically. The circuit of multivibrator using two NPN transistors is shown. The output of
transistor Q2 is coupled to base of transistor Q1 through R1. The output of transistor Q1 is coupled
to the base of transistor Q2 through C. The output of the monostable multivibrator is available at
the collector terminal of either transistor.

Procedure:

1. The circuit connections are given as per the circuit diagram.

2. Switch ON dc the supply.
3. The trigger pulse is given at the base of transistor Q1.
4. The output is taken at the collector of Q2. Pulse wave is obtained.
5. The time period of TON and TOFF are calculated separately and the graph is drawn with
measured values.

Result:

Thus the monostable multivibrator is designed to get a pulse wave and its TON and TOFF is
calculated and a graph is drawn.

Page 69
 Vi
Circuit Diagram

Positive Clippers
5V
R1
200 Ω t (ms)

AFO
(0-1MHz) RL 1 KΩ V0 - 5V
D1
10V (p-p) IN4001

V0

0 t (ms)

- 5V

Negative Clippers Vi

5V
R1
200 Ω
0 t (ms)

AFO D1
(0-1MHz) IN4001 RL 1 KΩ V0 - 5V
10V (p-p)

V0

5V

0 t (ms)

Page 70
Ex.No Clippers and Clampers

Date:
Aim:

To study the operations of positive and negative clippers, biased clippers, combinational
clippers and positive and negative clamping.

Apparatus Required:

Sl.No Equipments / components Type Quantity

1 Resistors 200 Ω, 1KΩ, 10 KΩ Each 1

2 Capacitors 1 µF 1

3 Diode IN4001 2

4 AFO (0-1MHz) 1

5 CRO (0 – 20 MHz) 1

6 Bread board 1

7 Connection Wires As required

Theory:

Clippers

The circuit with which the waveform is shaped by removing (or clipping) a portion of the
input signal without distorting the remaining part of the alternating waveform is called a clipper.
Clipping circuits are also referred to as voltage (or current) limiters, amplitude selectors, or
slicers. These circuits find extensive use in radars, digital computers, radio and television
receivers etc.

The clipping circuits employ the components like diode, resistor and dc battery. The
resistor R is used to limit the current flowing through the diode when it is forward biased. There
are four general categories of clippers (i) positive clipper (ii) negative clipper (iii) biased clipper
and (iv) combination clipper.

Page 71
 Biased Clipper

(i) Biased positive Clipper

Amplitude (V)
R1
Input
200 Ω
AFO Output
(0-1MHz)
D1 3V
IN4001 RL 1 KΩ V0
10 V (p-p) +
VR 3V Time (ms)
-

-5V

Input-output waveforms

(ii) Biased positive clipper with reverse polarity of VR

Voltage (V)
R1
200 Ω Input
AFO
(0-1MHz)
D1
IN4001 RL 1 KΩ V0
10 V (p-p) -
VR 3V 0 t (ms)
+

-3V

Output

Input-output waveforms

Page 72
1. Positive Clipper:

In the positive clipper circuit, when the input voltage is positive, diode conducts
and acts as short-circuit and hence there is zero signal at the output, i.e. the positive half
cycle is clipped off. When the input signal is negative, the diode does not conduct and
acts as an open switch, the negative half cycle appears at the output as shown in the
figure.
The positive clippers act as half wave rectifier. Thus the positive clipper has
clipped half cycle completely and allowed to pass the negative half cycle of the input
signal.

2. Negative Clipper

In the negative clipping circuit, the diode is connected in a direction opposite to

that of a positive clipper. During the positive half cycle of the input signal, the diode
conducts and acts as a open-circuit and hence, the positive half cycle of the input signal
will appear at the output as shown in the figure. During the negative half cycle of the
input signal, the diode conducts and acts as a closed circuit. The negative half cycle will
not appear at the output i.e. the negative half cycle is clipped off as shown in the figure.

3. Biased Clipper

In some applications, it is required to remove a small portion of positive or negative

half cycle of the signal voltage and hence biased clipper is used. The name bias is
designated because the adjustment of the clipping level is achieved by adding a biasing
voltage in series with the diode or resistor.

(a) Biased positive clipper

In the biased positive clipper, the diode conducts as long as the input voltage is
greater than +VR and the output remains at +VR until the input voltage becomes less
than +VR. When the input voltage is less than +VR, the diode does not conduct and
acts as an open switch. Hence the entire input signal having less than +VR as well as
negative half cycle of the input wave will appear at the output. The clipping level can
be shifted up or down by varying the bias voltage VR.

(b) Biased positive clipper with reverse polarity of VR

The figure shows the biased clipper with reverse polarity of VR along with the
input and output voltage waveforms. Here, the entire signal above -VR is clipped off.

Page 73
 (iii)Biased Negative clipper Voltage (V)

Output
R1
200 Ω 5V
AFO D1
(0-1MHz) IN4001
RL 1 KΩ V0
0 t (ms)
10 V (p-p) -
VR 3V
+ -3V

Input

Input-output waveforms

(iv) Biased Negative clipper with reverse polarity of VR

R1
Voltage (V)
200 Ω
Output
AFO D1
(0-1MHz) IN4001
RL 1 KΩ +VR
V0
10 V (p-p) +
VR 3V 0 t (ms)
-

Input

Input-output waveforms

Page 74
 (c) Biased negative clipper

In the biased negative clipper as shown in the figure, when the input voltage Vi ≤
-VR the diode conducts and clipping takes place. The clipping level can be shifted up
or down by varying the bias voltage (-VR).

(d) Biased negative clipper with reverse polarity of VR

The figure shows the biased negative clipper with reverse polarity of VR along
with the input and output waveforms. Here, the entire signal below +VR is clipped
off.

4. Combination clipper

This is the combination of a biased positive clipper and a biased negative clipper.
Figure shows the combination clipper along with the input and output voltage
waveforms. When the input signal voltage Vi ≥ +VR1, diode D1 conducts and acts as a
closed switch, while D2 is reverse biased and D2 acts as an open switch. Hence, the
output voltage cannot exceed the voltage level of +VR1 during the positive half cycle.
Similarly, when the input signal voltage Vi ≤ -VR2, diode D2 conducts and acts a
closed switch, while diode D1 acts as an open switch. Hence the output voltage V0 cannot
go below the voltage level of -VR2 during the negative half cycle.
The clipping levels may be changed by varying the values of VR1 and VR2. If VR1
= VR2, the circuit will clip both the positive and negative half cycles at the same voltage
levels and hence, such a combination clipper is called symmetrical clipper.

Page 75
Combination Clipper

R1

200 Ω
AFO D2
(0-1MHz) IN4001
D1
IN4001 RL 1 KΩ V0
10 V (p-p) + VR2 -
VR1 3V 3V
- +

Voltage (V)

Input

+3V

0 t (ms)
-3V
Output

Input – Output waveform

Page 76
Clampers

Clamping network shifts (clamps) a signal to a different dc level, i.e. it introduces a dc

level to an ac signal. Hence, the clamping network is also known as dc restorer. These circuits
find application in television receivers to restore the dc reference signal to the video signal.

The clamping network has the various circuit components like a diode, a capacitor and a
resistor. The time constant for the circuit τ = RC must be large so that the voltage across the
capacitor does not discharge significantly when the diode is not conducting.

(a) Positive clamper

During the negative half of the input signal, the diode conducts, and acts like a
short circuit. Now, the output voltage, V0 = 0V. The capacitor is charged to V volts and it
behaves like a battery. During the positive half of the input signal, the diode does not
conduct, and acts like an open circuit. Hence, the output voltage, V0 = 2V. This gives
positively clamped voltage and the total swing of the output is equal to the total swing of
the input signal.

(b) Negative Clamper

During the positive half cycle, the diode conducts, i.e. it acts like a short circuit.
The capacitor charges to V volts. During this interval, the output which is taken across
the short circuit will be V0 = 0V. During the negative half cycle, the diode is open. The
output voltage is -2V. This gives negatively clamped voltage and the total swing of the
output is equal to the total swing of the input signal.

Page 77
 Positive Clamper Negative Clamper

C1 C1

1 F 1 F

AFO D1 AFO
(0-1MHz) IN4001 RL 10 KΩ V0 (0-1MHz) RL 10 KΩ V0
D1
10V (p-p) 10V (p-p) IN4001

Vi
Vi

5V
5V

0 t (ms) 0 t (ms)

-5V -5V

V0 V0

10V
0 t (ms)

5V
-5V

0 t (ms)
-10V

Page 78
Page 79
Observations

Input Output
Circuit
Amplitude Time Period Amplitude Time Period
(V) (ms) (V) (ms)

Clipper

(i) Positive Clipper

(ii) Negative Clipper

Biased Clipper

(i) Biased Positive Clipper

(ii) Biased Positive Clipper with

reverse polarity of VR

(iii)Biased Negative Clipper

(iv) Biased Negative Clipper with

reverse polarity of VR

Combination Clipper

Clamper

(i) Positive Clamper

(ii) Negative Clamper

Page 80
Procedure:

1. Circuit connections are given as shown in the figure.

2. A sine wave with 10 V peak to peak 1 KHz frequency is given as the input.
3. The output is obtained in the CRO and is verified with the theoretical values.
4. Graph is drawn as shown in the model graph.

Result:

Thus the operation of clipper and clamper circuits have been observed and verified.

Page 81
Tuned Collector Oscillator circuit

Output Waveform

Page 82
Ex.No Simulation of Tuned Collector Oscillator

Date:
Aim:

To simulate transistor based tuned collector oscillator circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

RESULT:

Thus tuned collector oscillator circuit is simulated using Multisim.

Page 83
Wien Bridge Oscillator circuit

Output Waveform

Page 84
Ex.No Simulation of Wien Bridge Oscillator

Date:
Aim:

To simulate transistor based voltage time base generator circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

RESULT:

Thus voltage time base generator circuit is simulated using Multisim.

Page 85
Double Tuned Amplifier Circuit

Output Waveform

Page 86
Ex.No Simulation of Double Tuned Amplifier

Date:
Aim:

To simulate transistor based double tuned amplifier circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

RESULT:

Thus double tuned amplifier circuit is simulated using Multisim.

Page 87
 XFG1

VCC
5V
VCC 2

R3 R4
3.3kΩ 3.3kΩ
D1 D2
XSC1

1N4001 1N4001 Ext T rig

1 R1 5 R2 4
+
_
A B
Q2 6.2kΩ 6.2kΩ Q1 + _ + _ GND
3
OUTPUT

BC107BP BC107BP

GND

BISTABLE MULTIVIBRATOR

Page 88
Ex.No Simulation of Transistor based Bistable Multivibrator

Date:

Aim:

To simulate transistor based Bistable multivibrator.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

RESULT:

Thus Bistable Multivibrator is simulated using Multisim.

Page 89
Schmitt Trigger Circuit

Input and Output Waveform

Page 90
Ex.No Simulation of Schmitt Trigger

Date:
Aim:

To simulate transistor based schmitt trigger circuit.

TOOLS:

Multisim Version

PROCEDURE:

❖ Select start -all programs -National Instruments - Multisim.

❖ Select place-component and place the component as required.

❖ Connect the components as per circuit diagram.

❖ Click start button to start the simulation.

❖ Verify the result with the simulation result.

RESULT:

Thus schmitt trigger circuit is simulated using Multisim.

Page 91
Page 92
CONTENT BEYOND THE SYLLABUS

Page 93
Page 94
Ex.No Class A Power Amplifier

Date:

Aim:
(i) Observation of output waveform.
(ii) Measurement of maximum output power.
(iii) Determination of Efficiency.
(iv) Comparison with calculated values.

Apparatus Required:

Sl.No Name of the component Specification Quantity Required

1. Transistor CL 100 1
2. Resistor 1.8K 1
380  1
160  1
40  1
3. Capacitor 10 F 2
4. Power Supply (0 – 30) V 1
5. Audio Frequency Oscillator (AFO) (0 – 1) MHz 1
6. Cathode Ray Oscilloscope (CRO) (0 – 20) MHz 1
7. Bread Board 1
8. Connecting wires As required

Design:
(i) Choose VCC = 10 V, VBE = 0.6V, IC = 25 mA, VRE = 1 V, VCEQ = 5V

(ii) Design of RE & RC:

V RE = I C R E

V RE 1
R E = =
IC 25 mA
RE = 40 

Page 95
Tabular Column for Class A Amplifier Vi = 50 mV

Frequency (Hz) V0 (volts) Gain = V0 / Vi Gain(dB) = 20 log V0 / Vi

Page 96
 By applying KVL to the output side,
VCC – ICRC - VCE – VRE = 0
Substituting the values we get
RC = 160 

(iii)Design of R1 & R2:

Rth = 0.1(1 + h fe ) RE
= 0.1(79) 40
= 316 

IC 25 x 10 −3
IB = = = 0.32 mA
h fe 78

By applying KVL to the input side,

Vth = IB Rth + VBE + VRE
= 0.32 x 10-3 x 316 + 0.6 + 1
= 1.7 V
Rth 316
R1 = x VCC = x10 = 1.850 K
Vth 1.7
 R1 = 1.850 K

Rth 316
R2 = = = 380 
Vth 1.7
1− 1 −
V CC 10

 R2 = 380 K

Calculation:
2
VCC
Input Power Pin = VCC . I CQ =
2 RL
V 2 p− p
OutputPower Pac =
8 RL

Page 97
Page 98
 Output power
% Efficiency = x 100
Input power
V 2 p− p
% = 2
x 100
4VCC

Procedure:

1. Connect the circuit as per the circuit diagram.

2. Set VS=50mV using AFO.
3. Keeping the input voltage constant, vary the frequency from few Hz to 1MHz in regular steps
& note down the correspondingly output voltage.
4. Plot the graph: gain Vs frequency.

5. Calculate bandwidth from the graph.

Result:
Thus,
(i) The output waveform was observed.
(ii) Maximum output power is measured.
(iii)Efficiency is determined. %  = ------------------

Page 99
Circuit Diagram of Class B Amplifier

TR1= CL100 , TR2=CK100, DIODE= 1N4007

with crossover distortion without crossover distortion

Page 100
Ex.No Class B Power Amplifier

Date:
Aim:
To construct a Class – B (complementary symmetry) power amplifier. To observe the
output waveform with crossover Distortion, measure the maximum power output and to
determine the efficiency.

Apparatus required:

Sl.No Name of the component Specification Quantity Required

1. Transistor CL 100 , CK 100 Each 1
2. Resistor 4.7 K 2
100  2
3. Capacitor 47 F 2
4. Power Supply (0 – 30) V 1
5. Audio Frequency Oscillator (AFO) (0 – 1) MHz 1
6. Cathode Ray Oscilloscope (CRO) (0 – 20) MHz 1
7. Bread Board 1
8. Connecting wires As required

Theory:
The figure illustrates a Class – B Power Amplifier, which employs one PNP, and one
NPN transistor and require no transformed. This type of amplifier uses complementary
symmetry. i.e., the two transistor have identical characteristics but one is PNP and the other
NPN.
Its operation can be explained by referring to the figure. When the signal voltage is
positive, T1 (the NPN transistor) conducts, while T2 (the PNP transistor) is cut off. When the
signal voltage is negative, T2 conducts while T1 is cut off. The load current is
iL = ic1 – ic2
some advantages of the circuit are that the transformer less operation saves on weight and
cost and balanced push – pull input signals are not required. The disadvantage is obtaining pause
of transistor matched closely enough to achieve low distortion.

Page 101
Model Graph

Formulae

 Vmin 
Efficiency = 1 − 
4  VCC 

1 VCC 
2

Power Gain = 2  2 
  RL 

Page 102
Procedure:
1. Connect the circuit as per the diagram.
2. Set VS = 50mV(say) using the signal generator.
3. By connecting a CRO across load resistor we can obtain output wave form given in model
graph
4. Using the given formulae, we can calculate efficiency of amplifier.

Result
Thus a Class – B (complementary symmetry) power amplifier is constructed and the
output waveforms are observed and the maximum power output and efficiency is calculated.

Page 103