Instrumentation-II

-Er. Suresh Timilsina

Assistant Professor
IOE, Paschimanchal Campus
 Syllabus
Chapters
1. Microcontroller Based Instrumentation System
2. Parallel Interfacing with Microprocessor Based System
3. Serial Interfacing with Microprocessor Based System
4. Interfacing A/D and D/A converters
5. Data Acquisition and Transmission
6. Grounding and Shielding
7. Circuit Design
8. Circuit Layout
9. Software for instrumentation and control Application
10.Case Study
 Books-
1. D.V hall, “ Microprocessor and Interfacing, Programming and Hardware”, Revised 2nd
Edition

2. K.R Fowler, “Electronic Instrument Design- Architecting for the life cycle”, Oford
University Press

3. Ramesh S. Gaonkar,” Microprocessor Architecture, programming and application with

8085”, 5th Edition
 Marks Distribution
Chapter Marks
1 8 Internal Marks-20 marks

2 8 Title Marks
3 10 Assignment 5
4 8 Assessment 10
5 8 Attendance 5
6 6
7 6
Practical Marks-25 mark
8 6
9 8 Title Marks
10 12 LAB Report 5
Total 80 Case Study Report 15
Attendance 5
 Chapter-1
Microprocessor-A Microprocessor is a multipurpose programmable, clock driven, register based
electronic device that accepts binary data as input, process them and provide
result as output according to the instruction stored.

Instrumentation System- The system which is defined as the assembly of various instruments and
other components interconnected to measure, analyze and control physical quantities such as
electrical, thermal and mechanical etc.

Microprocessor based Instrumentation (MBI)- Any instrumentation system controlled and

processed by microprocessor is known as microprocessor based system. Eg- ATM, Automatic
Washing Machine, Fuel control etc.
 Microcontroller Vs Microprocessor

Microcontroller Microprocessor

1. It is designed to perform a small set 1. It is designed to perform a wide set

of specific function. of general purpose functions.
2.It has inbuilt RAM and Timer. 2. It doesn’t has inbuilt RAM and Timer.

3.Boolean operation is directly possible. 3.Boolean operation is not possible

directly.
4.It takes few instructions to read and 4.It takes many instructions to read and
write data from external memory. write data from external memory.
Advantages of Microprocessor Based System

• Complete Automation
• Added Intelligence
• Less Manpower
• Low Operating Cost
• Fast
• Uniform Products
• Can be Modified Accordingly
Here, the system is closed loop system. The temperature sensor senses the temperature
of a system which is compared by the microprocessor with the sampled saved in it. If the
temperature exceeds the limit then the heater control system is activated which controls
the temperature automatically. This closed loop system is more accurate and no human
operators is required.
 Address Decoding
• The processor communicates with all the parts interconnected in the system through a common address and data
bus. As a result of this, only one device can transmit data at a time and others can only receive that data. If more
than one device attempt to send data through the bus at the same time, the proper communication among the
devices does not become possible because the data sent by them gets garbled. To avoid this situation, ensuring
that the proper device gets addressed at proper time, the technique called "address decoding" is used. They are:
I/O Mapped I/O
It can address 2^8=256 bytes if mapped in I/O mode. They are used to read 8-bit data from or write 8-bit data to
selected device. In this, the I/O device is addressed with 8-bit address.
Memory Mapped I/O
In this mode, the I/O devices are addressed with 16-bit address. The total addressing capability of the processor 8085
in this mode is 2^16 = 65536 bytes = 64 KB.

In both modes described above, depending on the addresses that are allocated to the device, the address decoding
are categorized in the following two groups:
• Unique Address Decoding
If all of the address lines available on that mapping mode are used for address decoding, then that decoding is called
unique address decoding.
• Non-unique Address Decoding
If all of the address lines available on that mapping mode are not used for address decoding, then that decoding is
called unique address decoding.
 Address Decoding

RD RD

• Data pins: Since each memory location stores eight bits, there are eight data lines D0-D7 connected to the
memory chip.
• Address pins: The number of address pins depends on the size of the memory. In this case, a memory of size 1 kB
x 8 will have 210 different memory locations. Hence, it will have ten address lines A0 to A9. Similarly, the 2 kB
RAM will have 211 different memory locations. So, there are 11 address lines A0-A10.
• CS pin: When this pin is enabled, the memory chip knows that the microprocessor is talking to it and responds to
it accordingly. We need to generate this signal for each of the chips according to the range of addresses assigned
to them. Basically, we select a chip only when it is needed. The Chip Select (CS) pin is used for this.
• OE pin: When this active-low output enable pin is enabled, the memory chip can output the data in data bus.
• WR pin: Upon activation of this active-low memory write pin, data on the data bus is written on the memory chip
at the location specified by the address bus.
• RD pin :Upon activation of this active-low memory read pin, data on the memory is read.
• VCC and GND pins: These pins serve the purpose of powering the ICs. For simplicity, we will not show these pins
in the diagram.
 Address Decoding

3*8 Decoder circuit Chip Selection Process

2000H = 0011 0000 0000 0000

22FFH = 0011 0011 1111 1111
From the table below, we can observe that ten bits from A0 to A9 are changing. These ten bits are
directly connected to the address lines of the memory chip.
These ten bits take the value of either 0 or 1 to form addresses. The first address is 00 0000 0000,
and the second address is 00 0000 0001, the third is 00 0000 0010 and so on. The last address will
be 11 1111 1111.
Meanwhile, bits A11 to A15 do not change and don’t have any effect on the addressing process
inside the memory chip. So, we can conclude that the values of bits A15-A11 (0011 00) given in
the above table are in a unique, unchanging configuration for this memory chip. If even one of
these bits changes, the address won’t belong to this memory chip. So, we can use these values of
A15-A11 to uniquely identify this memory chip, which is exactly what the CS signal is
supposed to do.
Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
number
Starting
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
address
Ending
0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1
Address
 Address Decoding

Q1. Draw an interfacing circuit to interface 2 RAM chip each of 8K size.

No. of address lines required for register select is 8*1024=23 ∗ 210 = 213
Therefore 13 address lines are used in register select.
For chip select we use 16-13 bits.
For register select Ao-A12 and for chip select A13,A14,A15
Now for RAM 1
Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H

Ending Address 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 9FFFH

Now for RAM 2

Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 A000H

Ending Address 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BFFFH

 Address Decoding

Q1. Draw an interfacing circuit to interface 2 ROM chip each of 8K size and 1 RAM of 1K size.
No. of address lines required for ROM register select is 8*1024=23 ∗ 210 = 213
Therefore 13 address lines are used in register select and 3 for chip select.
No. of address lines required for RAM register select is 1*1024=20 ∗ 210 = 210
Therefore 10 address lines are used in register select and 6 for chip select.
Now for RAM 1
Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H

Ending Address 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 83FFH

Now for R0M 1

Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H

Ending Address 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFH

 Address Decoding

Q. Design an interfacing circuit to interface 4K ROM, 2K RAM and 1k EPROM.

No. of address lines required for 4K ROM register select is 4*1024=22 ∗ 210 = 212
Therefore 12 address lines are used in register select and 4 for chip select.
No. of address lines required for 2K RAM register select is 2*1024=21 ∗ 210 = 211
Therefore 11 address lines are used in register select and 5 for chip select.
No. of address lines required for 2K EPROM register select is 1*1024=20 ∗ 210 = 210
Therefore 10 address lines are used in register select and 6 for chip select.

Now for R0M

Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H

Ending Address 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 8FFFH

Now for RAM

Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 9000H

Ending Address 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 97FFH

 Address Decoding

Now for EPROM (Condition 1)

Starting with 9800H
Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 9800H

Ending Address 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 93FFH

Now for EPROM (Condition 2)

Address bit
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number

Starting address 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 A000H

Ending Address 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 A3FFH

 Q. Interface two 8K RAM chip and one 4K EPROM chips with 8086. Selecting FFFF0H as one of the
Address of EPROM which lie in between and starting address of RAM to be 00000H.

For RAM 1 and 2

No. of address lines required for 8K RAM register select is 8*1024=23 ∗ 210 = 213
Therefore 13 address lines are used in register select and 7 for chip select.
For EPROM
No. of address lines required for 4K EPROM register select is 4*1024=22 ∗ 210 = 212
Therefore 12 address lines are used in register select and 8 for chip select.
RAM 1
Address bit
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number
Starting
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H
address
Ending
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 01FFFH
Address

RAM 2
Address bit
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
number
Starting
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 02000H
address
Ending
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 03FFFH
Address
 Chapter-2 Parallel Interfacing with Microprocessor Based System

Q. Why do we need Parallel Interfacing?

How Does it Work
• With a serial interface we had a single signal traveling one bit at a time on the wire.
• With a parallel interface instead of having one wire carrying data, we have several wires.
• Because of that we can transfer data not one bit at a time but several bits at a time. On parallel interfaces we have 8 data
transmission wires, so the parallel interface can transfer a single byte at once.

• The advantage of a parallel interface over a serial interface is speed.

• In theory it should be eight times faster then a serial interface because we can use eight data wires at a time.
• One of the problems with the parallel interface was cable length. When we’re dealing with a parallel interface we’re
transferring eight signals across eight wires all at one time. Because of this, it is possible that some bits on some wires get
sooner to the destination (or later), instead of all bits arriving at the same time. If that happens, the receiving device
doesn’t know where the byte begins and where they byte ends. This problem is called signal jitter and it’s very common
with parallel interfaces. To reduce signal jitter we decrease the length of the cable.
• Parallel ports on the back of a computer are always female connectors.
.
 Methods Of Parallel Data Transfer

• Parallel transmission of data is used for short distance where the speed of information transfer is
considered.
• The information exchanged between I/O peripherals may be at different speed considering the device.
• In this case microprocessor can be used to select a particular speed of operation.
• This process is known as synchronizing.
• The various ways of synchronizing techniques are as follows-

a) Simple I/O- When we need to get digital data from a simple switch into a microprocessor (such that a
temperature sensor) then we just connect the switch to an input port and read the port. The
data is always ready and present so, we can read it at any time. Like wise when we want to
output data to a LED. We just connect the LED to output port. The LED is always ready. So,
we can send data to it at any time.

• Here, crossline represents the time at which a new data

Became valid at the output lines.
• It is not suitable for high speed data transfer.
 Methods Of Parallel Data Transfer

b) Simple Strobe I/O- In many applications valid data is present on an external device only at a certain time.
To indicate valid data is present we must send out strobe signal. STB low is for low rate
of Data transfer. For high speed data transfer this method doesn’t work as there is no
signal which tells the sending device when it is safe to send the next data. To prevent
this problem handshaking is introduced.
 Methods Of Parallel Data Transfer

c) Single Handshaking I/O-

• When Data in input port is ready, it sends a control signal STB low. When control Signal is read by
microprocessor it reads data from input/output devices.
• When reading from I/O devices is completed, it sends a acknowledgement signal to I/O device.
• When acknowledge signal from microprocessor is read by I/O devices, It again sends next data to
Microprocessor. This mechanism is called Single Handshaking with I/O.
• Similarly for O/P, microprocessor send STB low signal to O/P device. The O/P device when get STB
low signal it read data from microprocessor then send ACK signal to Microprocessor indicating to send
next data.

Parallel data lines

ACK
STB Low

Microprocessor Port Device Peripherials

 Methods Of Parallel Data Transfer

d) Double Handshaking I/O-

• The Peripheral or sending device asserts its STB low to ask the receiving device i.e Microprocessor
whether it is ready or not for data reception.
• The microprocessor raises its ACK signal high to indicate it is ready. The peripheral device then sends
the data and raises its STB line high to assure that the valid data is available for receiving device.
• When microprocessor read data, it drops its ACK signal low to indicate the reading is complete and
request the peripheral device to send next data.
• For data transfer where even more coordination is required between sending system and the receiving
system a double hand shake is used.
 8255 PPI(Programmable Peripheral Interface)

• 8255 is a programmable I/O device that acts as interface between peripheral devices and the
microprocessor for parallel data transfer. 8255 PPI (programmable peripheral interface) is programmed
in a way so as to have transfer of data in different conditions according to the need of the system.
• In 8255, 24 pins are assigned to the I/O ports. Basically it has three, 8-bit ports that are used for simple
or interrupt I/O operations.
• The three ports are Port A, Port B and Port C and as each port has 8 lines, but the 8 bits of port C is
divided into 2 groups of 4-bit each. These are given as port C lower i.e., PC3 – PC0 and port C upper
i.e., PC7 – PC4. And are arranged in group of 12 pins each thus designated as Group A and Group B.
• The two modes in which 8255 can be programmed are as follows: i) Bit set/reset mode ii) I/O mode
• The bits of port C gets set or reset in the BSR mode.
• The other mode of 8255 i.e., I/O mode is further classified into: a) Mode 0: Simple input/output
b) Mode 1: Input output with handshaking c) Mode 2: Bidirectional I/O handshaking

Mode 1 and Mode 2 both are same but the only difference is mode 1 does not support bidirectional
handshaking.
 • Data bus buffer: It is used to connect the internal
Block Diagram of 8255 PPI bus of 8255 with the system bus so as to establish
proper interfacing between the two. The data bus
buffer allows the read/write operation to be
performed from/to the CPU.
The buffer allows the passing of data from ports or
control register to CPU in case of write operation
and from CPU to ports or status register in case of
read operation.
• Read/ Write control logic: This unit manages
the internal operations of the system. This unit
holds the ability to control the transfer of data
and control or status words both internally and
externally.
Whenever there exists a need for data fetch then it
accepts the address provided by the processor
through the bus and immediately generates
command to the 2 control groups for the particular
operation.
 Group A and Group B control: These two groups are
Block Diagram of 8255 PPI handled by the CPU and functions according to the command
generated by the CPU. The CPU sends control words to the
group A and group B control and they in turn sends the
appropriate command to their respective port.
Group A has the access of the port A and higher order bits of
port C. While group B controls port B with the lower order
bits of port C.
CS: It stands for chip select. A low signal at this pin shows
the enabling of communication between the 8255 and the
processor.
RD – It is the signal used for read operation. A low signal at
this pin shows that CPU is performing read operation at the
ports or status word.
WR –A low signal at this pin allows the CPU to perform
write operation over the ports or control register of 8255
using the data bus buffer.
A0 and A1: These are basically used to select the desired port
among all the ports of the 8255 and it do so by forming
conjunction with RD and WR. It forms connection with the
LSB of the address bus.
The table below shows the operation of the control signals:

A1 A0 RD' WR' CS' Input/Output Operation

0 0 0 1 0 Port A - Data Bus

0 1 0 1 0 Port B - Data Bus

1 0 0 1 0 Port C - Data Bus

0 0 1 0 0 Data Bus - Port A

0 1 1 0 0 Data Bus - Port B

1 0 1 0 0 Data Bus - Port C

1 1 1 0 0 Data Bus - Control register

Reset: It is an active high signal that shows the resetting of the PPI. A high signal at this pin
clears the control registers and the ports are set in the input mode.