HD66850F

Color LCD Interface Engine (CLINE)

Description Features
The HD66850F CLINE interface controller con- • Various LCD panel sizes supported
verts multi-color video signals for CRT display — 640 or 720 dots wide
into color or monochrome LCD data. — 32 to 512 lines high
• Programmable display size
This device enables an LCD system to replace a
— 32 to 720 dots wide
CRT display system without any changes to the
original display system. It automatically adapts to — 32 to 512 lines high
display modes of the IBM-VGA (Video Graphics • Easy-to-see display
Array™) system, facilitating the configuration of — Centering
an LCD system. — Stretching (display stretched to fill out the
panel)
The CLINE can control TN-type (Twisted Nematic) • Improved gradation display quality using the
color and monochrome LCDs and can display a pulse width modulation method
maximum of 4096 color levels or 16 gray levels. • Desired gradation levels assignable to each
display color through the use of internal grada-
Note: Video Graphics Array is a trademark of
tion level palettes
International Business Machines Corpor-
• Changeable LCD frame frequency
ation, U.S.A.
— Through the use of a multi-port RAM frame
buffer
— Within the range of 1/2 to 2 times of CRT
display dot clock frequency
• High-speed operating frequency: 32 MHz (CRT
display dot clock)
• Recommended LCD drivers: HD66110ST
(column) and HD66115T (common)
• Single power supply: +5 V

Ordering Information
Type No. Package
HD66850F 136-pin plastic QFP (FP-136)
HD66850F
Pin Arrangement

A5/RD/DOTE

A3/CS/AJ3
A2/RS/AJ2
A4/WR/SP
HSYNC
VSYNC
BLANK

A1/AJ1
A0/AJ0
GND8

GND7

VCC6
VCC7
RES

UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
LD7
LD6
LD5
LD4
D7
D6
D5
D4
D3
D2
D1
D0
136

103
R0 1 102 GND6
R1 LD3
R2 LD2
R3 LD1
G0 LD0
G1 GND5
G2 XCL1
G3 YCL1
(NOTE) CL2
B0 FLM
B1 M
B2 SCLK
B3 DATAE
VCC1 DISPON
DOTCLK VCC5
GND1 LMODE4
LDOTCK LMODE3
MS0 LMODE2
MS1 LMODE1
MS2 LMODE0
MS3 GND4
MS4 HSIZE
MS5 VSIZE
MS6 VMODE
MS7 MMODE1
MS8 MMODE0
MS9 VCC4
MS10 PMODE1
MS11 PMODE0
MS12 SYNC
MS13 TEST1
MS14 TEST0
MS15 GND3
VCC2 34 69 MD15
35

68
MA8/SOE1

DT/OE
GND2
SOE0

MD10
MD11
MD12
MD13
MD14
CASL
RAS0
RAS1
VCC3
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7

CAS
WE
SC

(Top view)

Note: Pin No. 9 is not used; must be fixed low.

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 HD66850F
Pin Description
Type Symbol Pin No. Pin Name I/O Function
Power VCC1 – 14, 34, 53, 76, VCC1 – VCC7 — All of these pins must beAll
supply VCC7 88, 115, 124 connected to a +5V supply
GND1 – 16, 46, 70, 82, GND1 – GND7 — All of these pins must be grounded.
GND8 97, 102, 131, 136
MPU/ROM D0 – D7*1 (M) 116 – 123 Data 0 – 7 I/O Transfer data between internal
or program registers and MPU
interface
D0 – D7*1 (R) 116 – 123 Data 0 – 7 I Input data to internal registers from
external ROM
DOTE (P) 130 Dot clock edge I Switches RGB data latch timing
change High: Data latched at the rising
edge of DOTCLK pulses
Low: Data latched at the falling
edge of DOTCLK pulses
RD (M) 130 Read I Inputs a read signal for reading
data from internal registers
A5 (R) 130 Address 5 O Outputs external ROM address 5
SP (P) 129 Spread display I Selects either of the following
select I display size modes
High: Double – width display
Low: Normal display
WR (M) 129 Write I Inputs a write signal for writing
data to internal registers
A4 (R) 129 Address 4 O Outputs external ROM address 4
AJ3 (P) 128 Adjust 3 I Adjusts the display timing signal
(table 1)
CS (M) 128 Chip select I Inputs a chip select signal to select
the CLINE
High: The CLINE not selected
Low: The CLINE selected
A3 (R) 128 Address 3 O Outputs external ROM address 3
AJ2 (P) 127 Adjust 2 I Adjusts the display timing signal
(table 1)
RS (M) 127 Register select I Inputs a register select signal to
select either CLINE data registers
or index register
High: Data registers
Low: The index register
A2 (R) 127 Address 2 O Outputs external ROM address 2
AJ0, AJ1*2 (P) 125, 126 Adjust 0, 1 I Adjust the display timing signal
(table 1)
A0, A1*2 (R) 125, 126 Address 0, 1 O Output external ROM addresses 0
and 1, respectively
(M): For MPU programming method (R): For ROM programming method (P): For pin programming method
I/O: Input/Output

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HD66850F
Type Symbol Pin No. Pin Name I/O Function
CRT R0 – R3*3 1–4 Red serial data 0 – 3 I Input CRT display R data
interface
G0 – G3*3 5–8 Green serial data 0 – 3 I Input CRT display G data or
monochrome data
B0 – B3*3 10 – 13 Blue serial data 0 – 3 I Input CRT display B data: For
monochrome display, B1 selects 16-
gray-scale display and B0 indicates
the type of CRT display data input.
B1 = high: Prohibited
B1 = low: 16-level gray scale
display
B0 = high: 64-color data input
B0 = low: 16-level gray scale
data input
DOTCLK 15 Dot clock I Inputs the dot clock pulses for CRT
display
HSYNC 134 Horizontal I Inputs the CRT horizontal synchro-
synchronization nization signal
VSYNC 133 Vertical I Inputs the CRT vertical synchroniza-
synchronization tion signal
BLANK 135 Blanking I Inputs a display timing siganl
indicating horizontal or vertical
display period, or a blank signal
indicating the display period with
border area period
LCD UD4 – 111 – 114 LCD upper panel data O Output LCD upper panel data or
interface UD7*4 4–7 R data
UD0 – 107 – 110 LCD upper panel data O Output LCD upper panel data or
UD3*4 0–3 G data
LD4 – 103 – 106 LCD lower panel data O Output LCD lower panel data or
LD7*4 4–7 B data
LD0 – 98 – 101 LCD lower panel data O Output LCD lower panel data or
LD3*4 0–3 I data
XCL1*4 96 X-driver latch clock O Outputs the LCD data latch clock
pulses for X-drivers
YCL1 95 Y-driver shift clock O Outputs the LCD data line shift
clock pulses for Y-drivers
CL2 94 X-driver shift clock O Outputs the LCD data line shift
clock pulses for X-drivers
FLM 93 First line maker O Outputs the first line maker for
Y-drivers
I/O: Input/Output

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 HD66850F
Type Symbol Pin No. Pin Name I/O Function
LCD M 92 M O Outputs a signal for converting LCD
interface drive signals to AC
SCLK 91 Shift clock O Outputs clock pulse with a
frequency identical to CL2 but
without a retrace period
DATAE*4 90 Data enable O Indicates LCD data display period
DISPON*4 89 Display on O Controls LCD on/off
LDOTCK 17 LCD dot clock I Inputs LCD dot clock pulses
Buffer MD0 – 54 – 69 Memory data 0 – 15 O Output data to be written to buffer
memory MD15*5 memory
interface
MS0 – 18 – 33 Memory serial data I Input data read from buffer memory
MS15*6 0 – 15
MA0 – 38 – 45 Memory address O Output buffer memory addresses
MA7*5 0–7 0–7
MA8/ 37 Memory address 8/ O Outputs buffer memory address 8
SOE1*5 serial output enable 1 when 1-Mbit RAMs are used or
outputs a serial data output enable
signal when 256-kbit RAMs are used
SOE0*5 36 Serial output enable 0 O Output a serial data output enable
signal for buffer memory
WE*5 48 Write enable O Outputs a write enable signal for
buffer memory
DT/OE*5 47 Data transfer/output O Outputs a data transfer signal or
enable an output enable signal for buffer
memory
RAS0, 51, 52 Row address strobe 0, O Outputs a row address strobe signal
RAS1*5 row address strobe 1 for buffer memory
CAS, 49, 50 Column address O Outputs a column address strobe
CASL*5 strobe signal for buffer memory
SC*5 35 Serial clock O Outputs serial read clock pulses for
buffer memory
Mode PMODE0, 74, 75 Program mode 0, I Select a CLINE programming
control PMODE1 Program mode 1 method (table 2)
LMODE0 – 83 – 87 LCD mode 0 – 4 I Select a display mode (table 9)
LMODE4
MMODE0, 77, 78 Memory mode 0, 1 I Select a memory configuration
MMODE1 (table 3)
SYNC 73 Synchronization I Select a basic clock for LCD
High: DOTCLK
Low: LDOTCK
I/O: Input/Output

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HD66850F
Type Symbol Pin No. Pin Name I/O Function
Mode VMODE 79 VGA mode I Specifies a CRT display system
control High: Non-VGA system
(cont) Low: VGA system
VSIZE 80 LCD vertical size I Specifies the vertical size of the
LCD panel
High: 480 lines
Low: 400 lines
HSIZE 81 LCD horizontal size I Specifies the horizontal size of the
LCD panel
High: 720 dots
Low: 640 dots
RES 132 Reset I Inputs an external reset signal
TEST0, 71, 72 Test 0, 1 I Used for tests; Must be grounded
TEST1
I/O: Input/Output
Notes: 1. Must be fixed low for pin programming method.
2. Must be fixed low for MPU programming method.
3. Must be fixed low when not used.
4. Must be left disconnected when not used.
5. Must be left disconnected when buffer memory is not used.
6. Must be fixed low when buffer memory is not used.

Table 1 Display Timing Signal Fine Adjustment

Pin
Number of Dots
AJ3 AJ2 AJ1 AJ0 Adjusted
0 0 0 0 0
0 0 0 1 –1
0 0 1 0 –2
1 0 0 0 0
1 0 0 1 +1
1 0 1 0 +2
1 0 1 1 +3
1 1 0 0 +4
1 1 0 1 +5
1 1 1 0 +6
Note: – (minus) indicates advancing the phase of the display timing signal,
+ (plus) indicates delaying the phase of the display timing signal.

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 HD66850F
Table 2 Programming Method Selection

Pin
PMODE1 PMODE0 Programming Method
0 0 Pin
0 1 Internal registers (MPU)
1 0 Internal registers (ROM)
1 1 Prohibited

Table 3 Memory Configuration Selection

Pin
MMODE1 MMODE0 Memory Configuration
0 0 1-Mbit RAM
0 1 256-kbit RAM
1 0 No memory
1 1 No memory (when the CRT controller
supports dual screen display)

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HD66850F
Block Diagram

UD7–UD0
LD7–LD0

DISPON
DATAE
SCLK
XCL1
YCL1
FLM
CL2

M
VMODE

VSIZE LCD interface

HSIZE
LMODE4– Line buffer memory
LMODE0 (R, G, B)

Gradation
MS0–MS15
control Frame
Bus MD0–MD15
buffer
control MA0–MA7

Memory interface
memory
Gradation MA8/SOE1
control
Palette SOE0

(R, G, B) DT/OE
Stretch/ WE
Serial to centering SC
parallel
control RAS0/RAS1
converter
CAS/CASL
MMODE 1/0

RES Gradation level

Internal
LDOTCK Timing reducing circuit
register
DOTCLK control
SYNC
Double–width MPU/ROM PMODE 1/0
display control interface D7–D0
BLANK
HSYNC
VSYNC

R3–R0

G3–G0

B3–B0

DOTE/RD/A5
SP/WR/A4
AJ3/CS/A3
AJ2/RS/A2
AJ1/A1
AJ0/A0

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 Table 4 Register List

Index Reg Data Bits

Reg. Program Read/
CS RS 3 2 1 0 No. Register Name Units Write 7 6 5 4 3 2 1 0

1 — — — — — — — — — * * * * * * * *
Register List

0 0 0 0 0 0 IR Index — W — — — — IA3 IA2 IA1 IA0

0 1 0 0 0 0 R0 Control — R/W — — — STE CRE CCE SP DISP

ON

0 1 0 0 0 1 R1 Input timing control Dot R/W — — — DOTE AJ3 AJ2 AJ1 AJ0

0 1 0 0 1 0 R2 Horizontal display size Character R/W — DH6 DH5 DH4 DH3 DH2 DH1 DH0

0 1 0 0 1 1 R3 Vertical display size (high-order) Line R/W — — — — — — — DV8

0 1 0 1 0 0 R4 Vertical display size (low-order) Line R/W DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
CLINE registers are summarized in table 4.

0 1 0 1 0 1 R5 Centering raster Line R/W CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
(Raster)

0 1 0 1 1 0 R6 Centering character Character R/W — — — CC4 CC3 CC2 CC1 CC0

0 1 0 1 1 1 R7 Border color control — R/W — — — BM BCI BCR BCG BCB

0 1 1 0 0 0 R8 Stretching control Line R/W — — — — SF3 SF2 SF1 SF0

0 1 1 0 0 1 R9 Stretching index (high-order) Line R/W SI15 SI14 SI13 SI12 SI11 SI10 SI9 SI8

0 1 1 0 1 0 R10 Stretching index (low-order) Line R/W SI7 SI6 SI5 SI4 SI3 SI2 SI1 SI0

0 1 1 0 1 1 R11 Gradation level palette address — W — — PS1 PS0 PA3 PA2 PA1 PA0

0 1 1 1 0 0 R12 Gradation level palette data — R/W — — PD5 PD4 PD3 PD2 PD1 PD0

0 1 1 1 0 1 R13 Gradation display clock period Dot R/W — — — — — — — GC8

(high-order)

0 1 1 1 1 0 R14 Gradation display clock period Dot R/W GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0
(low-order)

0 1 1 1 1 1 R15 Reserved — — — — — — — — — —

Notes: 1. Bits marked with * cannot either read from or written to.
2. Bits marked with – are invalid and must be initialized to 0s; they cannot be read.

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HD66850F
HD66850F
System Description
Figure 1 shows an example of a VGA-compatible Addition of an external frame buffer memory
display system implemented with the CLINE. In (dual-port RAM) allows the LCD frame frequency
this system, a color palette HD153119 (Hitachi), to be increased above that of a CRT. This enables
which is capable of digital output, is used with a easy-to-see gradation display and the control of
VGA-compatible CRT controller. The CLINE LCDs having a dual screen configuration.
receives digital color data and display sychro-
nization signals from the color pallette and the CLINE operation may be controlled by internal
CRT controller, respectively, and displays 4096- registers through the 80-family MPU bus or an
color images on a color LCD, or 16-level grayscale external ROM (as shown in the figure), or simply
images on a monochrome LCD. With minor by pins.
modification of the existing CRT display system,
simultaneous LCD and CRT display is possible.

MPU or ROM

R0–R3
G0–G3
B0–B3
P0–P7 Color
palette
VGA HD153119 CLINE LCD
compatible
CRT controller
HSYNC, VSYNC
DOTCLK, BLANK

Frame buffer
memory

Analog data
CRT

Figure 1 System Block Diagram

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 HD66850F
Functional Description
Programming Methods Figure 2 (a) shows a connection example of the
CLINE and MPU buses for the MPU program-
To control CLINE functions, set the appropriate ming method. The CLINE bus, which is com-
pins and/or internal registers according to the patible with the 80-family microprocessor bus, can
functions used. Controlling methods include pin be directly connected to the host MPU bus.
and internal register programming methods.
Internal register programming includes the MPU Figure 2 (b) shows a connection example of the
and ROM programming methods. Any of the three CLINE and ROM for the ROM programming
methods can be selected by the combined setting method. In this case, data is automatically loaded
of pins PMODE0 and PMODE1 (table 2). into internal registers from the external ROM
attached for this purpose. Note that with the ROM
The pin programming method uses pins to control programming method, the reset signal must be
CLINE functions, and the internal register applied before rewriting the internal registers or
programming method uses data written to the gradation level palettes.
internal registers to control the functions.

Address bus

Data bus ROM

IOW
A0–A5 D0–D7
IOR
Decoder

CS RS WR RD D0–D7 A0–A5 D0–D7

HD66850F HD66850F

(a) Connection of MPU bus with CLINE (b) Connection of ROM with CLINE

Figure 2 Connection of MPU Bus or ROM with CLINE

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HD66850F
Automatic Adaptation to VGA Display Modes not automatic.) Consequently, in VGA display
modes, rewriting these registers is disabled.
VGA CRT display system display size varies
depending on the display mode. (VGA display Note that display stretching and centering are
sizes are: 320, 360, 640, or 720 dots wide and 350, unavailable when buffer memory is not used in the
400, or 480 lines high.) The CLINE identifies the system, even in VGA display modes. In these
current display mode from VSYNC and HSYNC cases, a display of different vertical size would be
signal polarities and the display period length, and placed in the upper section of the LCD panel,
changes the display size automatically (tables 5 resulting in a blank area in the lower section.
and 6). This function is enabled by setting the Centering the display in a system without memory
VMODE pin low. The CLINE, based on this requires external circuits or BIOS tuning.
function, automatically sets the necessary registers
(R0, R2, R3, R4, R5, R6, R8, R9, and/or R10) When displaying an image 720 dots wide (9 dots ×
corresponding to the parameters of the display size, 80 characters) on an LCD panel 640 dots wide, the
double-width display, gradation display clock, and CLINE removes the ninth horizontal dot of each
stretching/centering display functions. (In MPU or character to prevent losing the far-right portion of
ROM programming method, selection of vertical the image.
centering (bit 3 of R0) or stretching (bit 4 of R0) is

Table 5 Automatic Vertical Display Size Settings for VGA Display Modes

VSYNC HSYNC Display Size Border Rasters Displayed Rasters

Negative Positive 350 lines 1-6 7-356
Positive Negative 400 lines 1-7 8-407
Negative Negative 480 lines 1-8 9-488

Table 6 Automatic Horizontal Display Size Settings for VGA Display Modes

BLANK Signal High Level

Pulse Width Display Size Border Dots Displayed Dots

256-335 dots 320 dots (256-color) 1-5 6-325
336-359 dots 320 dots (16-color) 1-8 9-328
360-511 dots 360 dots 1-9 10-369
640-703 dots 640 dots 1-8 9-648
704-767 dots 720 dots 1-9 10-729

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 HD66850F
LCD Panel Size Since LCD panel horizontal size is limited to 640
or 720 dots even in internal register programming
LCD panel size is specified by either pins or method, centering function must be used as well so
internal registers. that the total number of horizontal dots including
the CRT display area and border areas become 640
For VGA modes, vertical panel size of 400 or 480
or 720. Refer to the following equation to calculate
lines can be selected by the VSIZE pin and
the number of centering characters. For the
horizontal panel size of 640 or 720 lines by the
definition of the border areas and centering
HSIZE pin.
characters, see figure 25, Centering Characters.
For non-VGA modes, the panel size is also
LCD panel horizontal size (dot) =
specified by the VSIZE and HSIZE pins in pin
{number of horizontal display characters +
programming method. In internal register
(number of centering characters × 2)} × 8
programming method, vertical display size is
specified by the vertical display size register (R3 Double-Width Display
and R4), within the range of 2 to 512 lines. Here,
note that the vertical display size specified by R3 Some CRT display systems have a low-resolution
and R4 is the CRT display vertical size. When this display mode of 320 horizontal dots in addition to
size differs from the LCD panel vertical size, a high-resolution display mode of 640 horizontal
centering or stretching function must be used. dots. In this case, the CRT display system lowers
Refer to the following equations for calculating the the dot clock frequency to reduce one line of data
number of centering rasters and the stretching to 320 dots. If such data is supplied to the LCD
ratio. For the definition of the centering rasters, see system of 640 horizontal dots as-is, the entire
figure 23, Centering Rasters, display will be placed on the left section of the
panel with the right half blank. To accommodate
• For centering this situation, the CLINE doubles the width of the
low-resolution display. This function is enabled by
LCD panel vertical size (line) =
the SP/WR/A4 pin in pin programming method or
CRT display vertical size (line) + centering
the SP bit (bit 1) of the control register (R0) in
rasters (lines) × 2
internal register programming method (table 7). In
• For stretching either method, for VGA display systems, the
CLINE detects low-resolution display mode and
LCD panel vertical size (line) = automatically enables double-width display.
CRT display vertical size (line) × stretching ratio

Table 7 Double-Width Display Usage

Programming Method CRT System Mode Setting

Pin: SP VGA Automatic
Non-VGA 0: Normal display
1: Double-width display
Internal register: VGA Automatic
Control register bit 1
Non-VGA 0: Normal display
(SP bit)
1: Double-width display

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HD66850F
Stretching and Centering Display Stretching function is controlled by the stretching
control register (R8) and the stretching index
When the display size differs from the LCD panel register (R9 and R10) so as to double the vertical
size, data will be displayed on the upper-left display size at most.
section of the LCD panel with blank space to the
right and/or below if no countermeasures are taken. Figure 3 shows display examples using stretching/
To provide a user-friendly display, the CLINE can centering functions. In these examples, a display of
stretch a display to fill out the panel or center a 640 dots × 350 lines is displayed on an LCD panel
display. Both stretching and centering functions are of 720 dots × 400 lines, using stretching/centering
enabled by control register (R0) bits 2, 3, and 4. functions.

Note that stretching and centering functions are For VGA modes, in both internal register program-
available only in a system where buffer memory is ming and pin programming methods, necessary
used. This is because these functions are realized parameters are automatically calculated from the
through adjustment of memory access. Similarly, relationship between display size and the LCD
stretching and centering functions are unavailable panel size and set in the appropriate registers.
in non-VGA modes when the CLINE is controlled Consequently, there is no need to account for
by the pin programming method. Simultaneous use display size.
of the vertical centering and stretching functions is
also impossible. However, the vertical centering or stretching
function can be selected in the internal register
In the internal register programming method, hori- programming method. (In pin programming
zontal centering function is controlled by the centering method, the stretching function is automatically
character register (R6) within the range of 1 to 32 selected.) Table 8 describes the use of the
characters (8 to 256 dots), while vertical centering stretching and centering function.
function is controlled by the centering raster register
(R5) within the range of 1 to 256 lines.

720 dots 720 dots

Vertical
640 dots centering 640 dots

350 lines Display 400 lines 400 lines

Display

Horizontal centering Horizontal centering

(a) Horizontal centering and (b) Horizontal centering and

vertical centering vertical stretching

Figure 3 Display Examples Using Stretching/Centering Functions

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 HD66850F
Table 8 Stretching and Centering Function Usage

Programming CRT System

Direction Method Mode Display Arranging Function Setting
Vertical Pin VGA Stretching Automatic
Non-VGA None — *1
Internal register VGA Stretching or centering Automatic *2
Non-VGA Stretching or centering Necessary
Horizontal Pin VGA Centering Automatic
Non-VGA None — *1
Internal register VGA Centering Automatic
Non-VGA Centering Necessary
Notes: 1. Display size must be LCD panel size.
2. Either stretching or centering function must be selected by the internal register.

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HD66850F
Display Modes configuration (single or dual), gradation display
method, and width of data transfer to LCD drivers.
Display Mode Settings and LCD Module Table 9 lists the display modes and figures 4 (a) to
Configurations: The CLINE supports 20 display 4 (g) show the corresponding LCD module
modes, depending on the settings of the LMODE4 configurations.
to LMODE0 pins. The display mode includes
display color mode (color or monochrome), screen

Table 9 Display Modes and LCD Module Configurations

Pin: LMODE
Mode Display Color Mode Screen Data LCD Module
No. 4 3 2 1 0 (Gradation Display Method) Config. Width Config.
1 0 0 0 0 0 Monochrome: black and white Single 4 Fig. 4 (a)
2 0 0 0 0 1 Dual 4 Fig. 4 (b)
3 0 0 0 1 0 Single 8 Fig. 4 (c)
4 0 0 0 1 1 Dual 8 Fig. 4 (d)
5 0 0 1 0 0 Monochrome: 16 gray levels Single 4 Fig. 4 (a)
(Frame-based data thinning)
6 0 0 1 0 1 Dual 4 Fig. 4 (b)
7 0 0 1 1 0 Single 8 Fig. 4 (c)
8 0 0 1 1 1 Dual 8 Fig. 4 (d)
9 0 1 0 0 0 Monochrome: 16 gray levels Single 4 Fig. 4 (a)
(1/2 pulse width modulation)
10 0 1 0 0 1 Dual 4 Fig. 4 (b)
11 0 1 0 1 0 Single 8 Fig. 4 (c)
12 0 1 0 1 1 Dual 8 Fig. 4 (d)
13 1 0 0 0 0 16 colors Single 2 Fig. 4 (e)
14 1 0 0 1 0 Single 4 Fig. 4 (f)
15 1 0 0 1 1 8 colors Single 8 Fig. 4 (g)
16 1 0 1 0 0 4096 color Single 2 Fig. 4 (e)
(Frame-based data thinning)
17 1 0 1 1 0 Single 4 Fig. 4 (f)
18 1 0 1 1 1 Single 8 Fig. 4 (g)
19 1 1 0 1 0 4096 color Single 4 Fig. 4 (f)
(1/2 pulse width modulation)
20 1 1 0 1 1 Single 8 Fig. 4 (g)
Note: Modes 15, 18, and 20 are interleaving structure modes.

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 HD66850F

4 bits
4 bits Column drivers
Column drivers

LCD
LCD
4 bits
HD66106

(a) Single screen, 4-bit data width (b) Dual screen, 4-bit data width

8 bits
8 bits Column drivers
Column drivers

LCD
LCD
8 bits
HD66107

(c) Single screen, 8-bit data width (d) Dual screen, 8-bit data width

2 bits 4 bits
R R
G G
B Color drivers B Color drivers
I I

LCD LCD

(e) Single screen, 2-bit data width, color drivers (f) Single screen, 4-bit data width, color drivers

8 bits
Column drivers

RGBRGB
LCI

8 bits
Column drivers

(g) Single screen, 8-bit data width,

interleaving structure

Figure 4 LCD Module Configurations by Display Modes

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HD66850F
Gradation Level Reduction: Although a CRT The B0 pin must be set to 1, and the B1 pin to 0.
display system can represent information for over Unused display data input pins must be fixed to
100,000 color levels, an LCD cannot handle so 0. See figure 5 (a).
much information.
— 16-level grayscale input and 16-level gray-
Consequently, CRT color or gradation level scale output (modes 5-12)
information must be reduced in order for the
CLINE to display it. Reduction methods vary Both B0 and B1 pins must be set to 0. Unused
depending on the input color or gradation level display data input pins must be fixed to 0. See
information, the LCD panel (color or mono- figure 5 (b).
chrome), and other factors. Table 10 lists gradation
• When color LCD panel is used (LMODE4 = 1)
level reduction for CLINE modes, where “Input
Bits” indicates CRT display color data and — 64-color input and 16- or 8-color output
“Reduced Data” indicates input to the gradation (modes13-15)
level palettes.
Two-bit R, G, and B data must be input to the
Input Display Data Connection: Input display R2-R3, G2-G3, and B2-B3 pins, respectively.
data connection and pin settings depend on the Unused display data input pins must be fixed to
CRT input mode (color or gradation level 0). See figure 6 (a).
information) and the LCD panel used.
— 4096-color input and 4096-color output
• When monochrome LCD panel is used (modes 16-20)
(LMODE4 = 0)
Four-bit R, G, and B data must be input to the
— 64-color input and 16-level grayscale output R0-R3, G0-G3, and B0-B3 pins, respectively. If
(modes 5-12) the input has more than 4096 colors, use the
high-order four bits of each color. See figure 6
(b).

Table 10 Gradation Level Reduction for CLINE Display Modes

Input Bits Reduced Data

Input CLINE Display LCD Gradation Level
Mode R G B Mode 3 2 1 0 Panel Reduction (Bits)
4096 4 4 4 4096 color D3 D2 D1 D0 Color 12 → 12
colors levels
64 2 2 2 16 colors R G B I Color 6→4
colors
64 2 2 2 16 gray levels D3 D2 D1 D0 Monochrome 6→4
colors
16 gray — 4 — 16 gray levels D3 D2 D1 D0 Monochrome 4→4
levels
16 gray — 4 — Monochrome All 0s or all 1s Monochrome 4→1
levels (black & white)

1396
 HD66850F

R0, R1 R2, R3
G0, G1 G2, G3
B0, B1 B2, B3 CLINE 16-level grayscale
LCD data
0 B1
1 B0

(a) 64-color input and 16-level grayscale output

16-level gray-
G0–G3
scale data
CLINE 16-level grayscale
LCD data
0 B1
0 B0

(b) 16-grayscale input and 16-level grayscale output

Figure 5 Input Display Data Connection and Pin Settings when a Monochrome LCD Panel is Used

1397
HD66850F

R0, R1 R2, R3
G0, G1 G2, G3 Color LCD data
CLINE
B0, B1 B2, B3

(a) 64-color input and 16- or 8-color output

R0–R3 R0–R3
G0–G3 G0– G3 Color LCD data
CLINE
B0–B3 B0– B3

(b) 4096-color input and 4096-color output

Figure 6 Input Display Data Connection and Pin Settings when a Color LCD Panel is Used

1398
 HD66850F
LCD Data Output: The CLINE uses pins modes with pulse width modulation is slightly
UD7–UD0 and LD7–LD0 for display data output. different. This type of example is shown in figure
Output data from these pins depend on the display 8. Figure 8 shows the display data output timing in
mode, as shown in table 11. However, data output mode 10 (1/2 pulse width modulation, 4-bit
timings are basically the same in all display modes. monochrome data transfer, and dual screen
Display data output timing for modes 15 and 18 (8- configuration).
bit color data transfer, bidirectional connection,
without pulse width modulation) is shown in figure However, LCD lower panel data LD3–LD0 are not
7. Display data output timing for the LCD display shown in the figure.

Table 11 LCD Data Output Pins and Display Data by Display Modes

Monochrome Modes
4-Bit/ 4-Bit/ 8-Bit/ 8-Bit/
Color Modes
Single Dual Single Dual
Pin Screen Screen Screen Screen 2-Bit 4-Bit 8-Bit
UD7 — — D7 UD7 — R3 R15 G10 B5
UD6 — — D6 UD6 — R2 B15 R9 G4
UD5 — — D5 UD5 R1 R1 G14 B9 R3
UD4 — — D4 UD4 R0 R0 R13 G8 B3
UD3 D3 UD3 D3 UD3 — G3 B13 R7 G2
UD2 D2 UD2 D2 UD2 — G2 G12 B7 R1
UD1 D1 UD1 D1 UD1 G1 G1 R11 G6 B1
UD0 D0 UD0 D0 UD0 G0 G0 B11 R5 G0
LD7 — — — LD7 — B3 G15 B10 R4
LD6 — — — LD6 — B2 R14 G9 B4
LD5 — — — LD5 B1 B1 B14 R8 G3
LD4 — — — LD4 B0 B0 G13 B8 R2
LD3 — LD3 — LD3 — (I3) R12 G7 B2
LD2 — LD2 — LD2 — (I2) B12 R6 G1
LD1 — LD1 — LD1 (I1) (I1) G11 B6 R0
LD0 — LD0 — LD0 (I0) (I0) R10 G5 B0
Notes: 1. The left bit corresponds to MSB.
2. U and L indicate upper panel and lower panel data, respectively.
3. Data in parentheses are for 16-color display.
4. — indicates that the corresponding pins are not used; must be left disconnected.

1399
HD66850F

R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3

1st 2nd 3rd 4th

dot dot dot dot
LCD screen

YCL1

XCL1

CL2

UD7 R0 G5 B634
UD6 B0 R6 G635
UD5 G1 B6 R636
UD4 R2 G7 B 636
UD3 B2 R8 G637
UD2 G3 B8 R638
UD1 R4 G9 B 638
UD0 B4 R 10 G639
LD7 G0 B5 R635
LD6 R1 G6 B635
LD5 B1 R7 G 636
LD4 G2 B7 R637
LD3 R3 G8 B637
LD2 B3 R9 G638
LD1 G4 B9 R 639
LD0 R5 G 10 B639

Figure 7 Display Data Output Timing in Display Modes without Pulse Width Modulation
(Modes 15 and 18)
1400
 HD66850F
In figure 8, data P0–0, P4–0, ... P636–0 make up determines the display status as follows: (first data,
the first set of data for one line to be output to LCD second data) = (0, 0): display off; (1, 0): 1/2 pulse
drivers via pin UD3. Likewise, data P0–1, P4–1, ... width modulation; and (1, 1): display on. For more
P636–1 make up the second set of data. The details, refer to the Gradation Display Methods
combination of the first and second sets of data section.

YCL1

XCL1

CL2

UD3 P0-0 P4-0 P636-0 P0-1 P4-1 P636-1

UD2 P1-0 P5-0 P637-0 P1-1 P5-1 P637-1

UD1 P2-0 P6-0 P638-0 P2-1 P6-1 P638-1

UD0 P3-0 P7-0 P639-0 P3-1 P7-1 P639-1

Figure 8 Display Data Output Timing in Display Modes with Pulse Width Modulation
(Mode 10)

1401
HD66850F
Gradation Display Methods Consequently, the X-driver latch clock must be
different from the Y-driver shift clock, and a
The CLINE supports the frame-based data thinning conventional LCD module configuration cannot be
method and pulse width modulation method for used. Therefore, clock XCL1 must be supplied to
gradation display. X-drivers and clock YCL1 to Y-drivers (figure 10).

Frame-Based Data Thinning Method: In the The XCL1 period is specified by the gradation
frame-based data thinning method, the CLINE display clock period register (R13 and R14) when
thins out the display data in line or dot units in the no buffer memory is used in non-VGA modes and
specified frames. in the internal register programming method.
(Pulse width modulation is unavailable when
Pulse Width Modulation Method: In the pulse
buffer memory is not used in non-VGA modes, pin
width modulation method, the CLINE combines
programming method.) In the other cases, the
1/2 pulse width modulation and frame-based data
register is automatically set, since the YCL1 period
thinning. In this case, data is output from X-drivers
is fixed (table 12).
twice in one line-selection period (figure 9).

YCL1 Line n Line n + 1

XCL1

X-driver Line n Line n Line n + 1 Line n + 1

input data 1st data 2nd data 1st data 2nd data

X-driver Line n – 1 Line n Line n Line n + 1

output data 2nd data 1st data 2nd data 1st data

Figure 9 Driver Clock and Display Data Timing for Gradation Display
with 1/2 Pulse Width Modulation

1402
 HD66850F
Table 12 XCL1 Period Setting

Memory Mode XCL1 Period Setting

With-memory Half of YCL1 period for 1/2 pulse with Automatic
modulation method
Without-memory VGA Half of YCL1 period for 1/2 pulse width Automatic
modulation method (See note below)
Non-VGA
Internal register Conforms to gradation display clock Required (R13, R14)
programming register (R13, R14) settings
Pin programming —
Note: Total number of horizontal dots must be 400, 450, 800, or 900 for displaying 320, 360, 640, or 720
dots, respectively.

XCL1 X-drivers

YCL1
Y-drivers

LCD
LCD module

Figure 10 X- and Y-Driver Clock Connection for Pulse Width Modulation Method

1403
HD66850F
Gradation Level Palettes In pin programming and MPU programming
methods, these palettes are automatically loaded
Gradation display quality depends greatly on LCD after reset with appropriate data for frame-based
panel characteristics. data thinning modes and 1/2 pulse width
modulation modes. The automatically set data
Consequently, uniform gradation display may be
cannot be rewritten in the pin programming
impossible for some panels. To accommodate this
method, but can be rewritten, any time after 100 µs
situation, the CLINE incorporates a set of grada-
have elapsed after reset, in MPU programming
tion level palettes that can assign any gradation
method.
level to any CRT display color as desired.
By contrast, in the ROM programming method,
16 levels are available for gradation display using
these palettes are not automatically set. Thus
the frame-based data thinning method and 31
writing the necessary data to the palettes is always
levels using 1/2 pulse width modulation method.
required.
Appropriate levels can be selected for the LCD
panel used. Table 13 shows the relationship between the values
set in the palettes (through R12) and gradation
The R-, G-, and B-palettes are used for color level
levels. Values other than those shown here disable
display modes, while only the R-palette is used for
correct display.
16-level grayscale display modes.

1404
 HD66850F
Table 13 Relationship between Gradation Levels and Palette (R12) Values

(a) Frame-based data thinning modes (b) 1/2 pulse width modulation modes

Grada- Grada-
tion Grada- tion Grada-
Level Palette Data (R12 Data Bits) tion Level Palette Data (R12 Data Bits) tion
No. 5 4 3 2 1 0 Level No. 5 4 3 2 1 0 Level
0 1 0 0 0 0 0 0.00 0 0 1 0 0 0 0 0.00
1 1 0 0 0 0 1 0.14 1 0 1 0 0 0 1 0.07
2 1 0 0 0 1 0 0.20 2 0 1 0 0 1 0 0.10
3 1 0 0 0 1 1 0.29 3 0 1 0 0 1 1 0.14
4 1 0 0 1 0 0 0.33 4 0 1 0 1 0 0 0.17
5 1 0 0 1 0 1 0.40 5 0 1 0 1 0 1 0.20
6 1 0 0 1 1 0 0.43 6 0 1 0 1 1 0 0.21
7 1 0 0 1 1 1 0.50 7 0 1 0 1 1 1 0.25
8 1 0 1 0 0 0 0.57 8 0 1 1 0 0 0 0.29
9 1 0 1 0 0 1 0.60 9 0 1 1 0 0 1 0.30
10 1 0 1 0 1 0 0.66 10 0 1 1 0 1 0 0.33
11 1 0 1 0 1 1 0.71 11 0 1 1 0 1 1 0.36
12 1 0 1 1 0 0 0.75 12 0 1 1 1 0 0 0.38
13 1 0 1 1 0 1 0.80 13 0 1 1 1 0 1 0.40
14 1 0 1 1 1 0 0.86 14 0 1 1 1 1 0 0.43
15 1 0 1 1 1 1 1.00 15 0 1 1 1 1 1 0.50
16 1 1 0 0 0 0 0.50
17 1 1 0 0 0 1 0.57
18 1 1 0 0 1 0 0.60
19 1 1 0 0 1 1 0.64
20 1 1 0 1 0 0 0.67
21 1 1 0 1 0 1 0.70
22 1 1 0 1 1 0 0.71
23 1 1 0 1 1 1 0.75
24 1 1 1 0 0 0 0.79
25 1 1 1 0 0 1 0.80
26 1 1 1 0 1 0 0.83
27 1 1 1 0 1 1 0.86
28 1 1 1 1 0 0 0.88
29 1 1 1 1 0 1 0.90
30 1 1 1 1 1 0 0.93
31 1 1 1 1 1 1 1.00

1405
HD66850F
Display On/Off Control In this case, the following relationship must hold
true:
When the LCD drivers used have an LCD on/off
control pin, display can be controlled with the 1/2 × fDOTCLK < fLDOTCK < 2 × fDOTCLK
CLINE DISPON signal. When the LCD drivers
used do not have an LCD on/off control pin, the fDOTCLK: Dot clock frequency
CLINE can turn off display by transferring all-0
The data transfer rate to LCD drivers depends on
display data to the drivers.
the mode in which the CLINE is used. Specifically,
Display will be turned on with the DISPON pin = the rate depends on screen configura-tion (single or
1, turns the display off while DISPON = 0. The dual), data transfer width (bit count), and gradation
DISPON pin is equivalent to the DISPON bit (bit display methods. For example, the data transfer
0) of the control register. rate will be doubled for 1/2 pulse width gradation
display. This is because data must be transferred
In the pin programming method, display is on two times during one line-selection period. The
except for four frames after reset. The four frame data transfer rate (fCL2: CL2 frequency) is calcu-
display-off time period prevents random display at lated from the following equation (fLDOTCK =
power-on. In the MPU programming method, fDOTCLK for synchronous mode):
display is turned off at reset, but can be freely
turned on or off after four frames after reset by fLDOTCK × l
fCL2 =
rewriting the corresponding register bit. In the n×m
ROM programming method, a 1 must be written to
n: Number of panels composing one screen
the DISPON bit to turn on display. Like in other
— 1 for modes 1, 3, 5, 7, 9, 11, 13-20
programming methods, display is off for four
frames after reset. — 2 for modes 2, 4, 6, 8, 10, 12

LDOTCK Frequency and Data Transfer Rate m: Number of bits transferred at one time
— 2 for modes 13, 16
The LDOTCK frequency (fLDOTCK) for asynchro- — 4 for modes 1, 2, 5, 6, 9, 10, 14, 15, 17-20
nous mode is calculated from the following — 8 for modes 3, 4, 7, 8, 11, 12
equation:
l: Constant for each gradation display
fLDOTCK = (Nhd + 48) × Nvd × fF — 1 for modes 1-8, 13-18
— 2 for modes 9-12, 19, 20
Nhd: Number of dots contained in one
horizontal line of the LCD panel
Nvd: Number of horizontal lines from the
LCD panel top to bottom
fF: Frame frequency

1406
 HD66850F
Synchronous/Asynchronous Modes and The CLINE has another mode in which dual screen
Memory LCD panels can be used and fewer memory
devices are required. This is called “synchronous
The CLINE has two timing modes: asynchronous with-memory mode” (figure 11 (c)). In this mode,
and synchronous. the number of memory devices can be reduced to a
half or a third that of asynchronous mode. This is
In asynchronous mode, dot clock pulses for the
because RGB data sent from the CRT system is
CRT system (DOTCLK) are different from those
processed for gradation display before being
for the LCD system (LDOTCK) in frequency to
written into buffer memory. (In asynchronous
accommodate frame frequency conversion. This
mode, on the other hand, R, G, and B data sent
requires buffer memory as shown in figure 11 (a).
from the CRT system is separately written into the
In this mode, dual screen LCD panels can be used.
R-plane, G-plane, and B-plane memories,
In synchronous mode, dot clock pulses for the CRT respectively.)
system are identical to those for the LCD system,
Table 14 summarizes these modes.
thus requiring no buffer memory in principle
(synchronous without-memory mode (figure 11
(b)). However, synchronous without-memory
mode cannot support dual screen LCD panels.

HD66850 HD66850 HD66850

CRT Gradation LCD CRT Gradation LCD CRT Gradation LCD
processing DOTCLK processing DOTCLK processing

DOTCLK LDOTCK DOTCLK DOTCLK

Memory Memory

(a) Asynchronous mode (b) Synchronous without- (c) Synchronous

memory mode with-memory mode

Figure 11 Signal Flow for Synchronous/Asynchronous With-/Without-Memory Modes

1407
HD66850F
The CLINE uses dual port RAMs for buffer The number of memory devices required depends
memory, enabling high-speed display and inde- on the LCD panel size and the display mode.
pendent use of an LCD dot clock and a CRT dot However, it depends only on LCD panel vertical
clock. size and not on horizontal size since the CLINE
uses memory as shown in figure 12. For example,
The CLINE supports three types of memory one 256-kbit memory device is required for the
configurations: 64 k × 4 bits (256 k), 256 k × 4 bits panel having 256 or less lines and two for that
(1 M), and 128 k × 8 bits (1 M), any of which can having 257 to 512 lines. Table 15 lists the number
be selected with the MMODE0 and MMODE1 of memory devices required for each mode.
pins (table 3).

Table 14 Memory Mode Summary

Asynchronous With- Synchronous With- Synchronous Without

Memory Mode Memory Mode Memory Mode
Centering/stretching Possible Possible Impossible
Max number of gray levels 16 16 16
Max number of color levels 16 4096 (frame-based 4096 (pulse width
data thinning) modulation)
Dual screen Possible Possible Impossible
Max number of 512 512 1024
display lines
Frame frequency Possible Impossible Impossible
conversion

1024

Not
256 Used used

640 or 720

64 k ✕ 4 bit memory

Figure 12 Display Sizes and Memory Area Used

1408
 HD66850F
Table 15 Number of Memory Devices for Different Display modes

Number of Memory Devices Required

Asynchronous Synchronous
Display Mode 64 k × 4 256 k × 4 128 k × 8 64 k × 4 256 k × 4 128 k × 8
Monochrome 2 1 1 2 1 1
Modes 1–4
16-level grayscale 8 4 2 2 1 1
(frame-based)
Modes 5–8
16-level grayscale 8 4 2 4 2 1
(1/2 pulse width)
Modes 9–12
8-color Mode 15 6 3 2 6 3 2
16-color Modes 13, 14 8 4 2 8 4 2
4096-color-scale — — — 6 3 2
(frame-based)
Modes 16–18
Frame-based: Frame-based data thinning method
1/2 pulse width: 1/2 pulse width modulation method
Note: With-memory mode does not support color level display using the pulse width modulation method.

1409
HD66850F
Display Timing Signal Fine Adjustment to (1, 0, 1, 0) to delay the signal for two dots.
Conversely, they must be set to (0, 0, 1, 0) to
When the display timing signal is supplied advance the signal for two dots for the case of
externally, a phase shift may appear between CRT figure 13 (b), where the display timing signal is
data and the display timing signal, since each two dots behind.
signal has its own peculiar lag. The CLINE can
adjust the display timing signal with pins AJ3–AJ0 When there is no need to adjust the signal, a setting
(in pin programming method) or with the input of either (0, 0, 0, 0) or (1, 0, 0, 0) will work.
timing control register (R1) (in internal register
programming method) to compensate the phase It should be noted that the VGA CRT system
shift (table 1). applies the BLANK signal, which includes the
border area period, as the display timing signal,
Figure 13 (a) shows an example of adjusting a and that the CLINE removes the border area
display timing signal that is two dots ahead of the period. Consequently, the border area period must
display start position. In this case, pins (AJ3, AJ2, be considered for adjusting the display timing
AJ1, AJ0) or data bits (3, 2, 1, 0) of R1 must be set signal.

1410
 HD66850F

Display start position

CRT display
data
2 dots ahead

Display timing
signal before Fine adjustment
adjustment = (1, 0, 1, 0)

Display timing
signal after
adjustment
(a) Delaying display timing signal

Display start position

CRT display
data 2 dots behind
Display timing
signal before
adjustment Fine adjustment
= (0, 0, 1, 0)
Display timing
signal after
adjustment

(B) Advancing display timing signal

Figure 13 Display Timing Signal Fine Adjustment

1411
HD66850F
Border Color Control border color control register (R7). However, the
desired color can be specified only in asyn-
In the internal register programming method, the chronous mode.
CLINE can specify the color of a blank area that is
left on a centered display (figure 14). Any of 16 In the pin programming method, the specified
colors or the color of the dot immediately before color is always the same color as the dot imme-
the valid display data can be specified by the diately before the valid display data.

Border area
Vertical
centering

Display

LCD panel
Horizontal centering

Figure 14 Border Area and an LCD Panel

1412
 HD66850F
Internal Registers Registers are valid only for the internal register
programming method and are invalid (don’t care)
The CLINE has one index register (IR) and 15 data for the pin programming method. Since all data
registers (R0–R14). In the MPU programming registers are reset to 0s, they must be rewritten
method, the desired register address must be after reset.
written in one cycle into the index register before
writing or reading data to/from the register in the Register Access for MPU Programming Method
following cycle. By contrast, in the ROM pro-
gramming method, the index register is not used; First write the desired data register address into the
the CLINE automatically reads data from the index register with CS = 0, RS = 0, and WR = 0,
ROM, in which data has been written to the ROM then write/read data to/from the register with CS =
addresses corresponding to the desired data 0, RS = 1, and WR = 0 or RD = 0. Figure 15
registers, and writes it to the data register. shows the timing for writing data into an internal

WR

RS

CS

Write (01)H to Write (02)H to

the index register the index register

Write data to R1 Write data to R2

register.

Figure 15 Internal Register Write by MPU

1413
HD66850F
ROM Data Setting for ROM Programming
Method
must have been written to ROM addresses
The desired data must have been previously $0010–$003F. Consequently, data written for
written to the ROM addresses corresponding to the internal registers R11 and R12 are invalid. Figure
data register addresses; that is, to ROM addresses 16 shows the ROM address map.
$0000–$000F. Data for the gradation level palettes

$0000 Data for R0 Internal registers

$0001 Data for R1
$0002 Data for R2

•
•
•

$0010 Data for R-palette 0 R-palettes

$0011 Data for R-palette 1

•
•
•

$0020 Data for G-palette 0 G-palettes

$0021 Data for G-palette 1
•
•
•

$0030 Data for B-palette 0 B-palettes

$0031 Data for B-palette 1
•
•
•

$0040 Not used

$FFFF

Figure 16 ROM Address Map

1414
 HD66850F
Register Function STE bits are set to 1 at the same time, correct
display will be disabled.
Index Register (IR): The index register (figure 17),
composed of four valid bits, selects one of the 15 • CCE bit
data registers. The index register itself is selected — CCE = 1: Horizontal centering function
by the MPU while the RS signal is low and selects enabled
a data register with the register address written. — CCE = 0: Horizontal entering function
disabled
Control Register (R0): The control register (figure
18) is composed of five valid bits, each with a • SP bit
particular function. — SP = 1: Double-width display
— SP = 0: Normal display
• STE bit
— STE = 1: Stretching function enabled • DISPON bit
— STE = 0: Stretching function disabled — DISPON = 1: Display on
— DISPON = 0: Display off
• CRE bit
— CRE = 1: Vertical centering function enabled DISPON is always cleared at reset. In the MPU
— CRE = 0: Vertical centering function disabled programming method, rewriting this bit can always
be rewritten. However, display will be off for four
Simultaneous use of stretching and vertical center-
frames after reset, regardless of the status of this
ing functions is impossible; if both the CRE and
bit.

IR

Data bit 7 6 5 4 3 2 1 0

Value — — — —

Register address

Figure 17 Index Register

R0

Data bit 7 6 5 4 3 2 1 0

Function — — — STE CRE CCE SP DISP

ON

Figure 18 Control Register

1415
HD66850F
Input Timing Control Register: The input timing • AJ3-AJ0 bits: Adjust the externally supplied
control register (figure 19) has five valid bits, display timing signal to synchronize its phase
having two different functions. with that of LCD data. Write the shift, repre-
sented in dots, between the display timing signal
• DOTE bit : Switches RGB data latch timing. and the display start position to these bits. The
— DOTE = 1: Latches data at the rising edge of absolute value of the number of dots to be
the dot clock pulses shifted must be written to the AJ2-AJ0 bits and
— DOTE = 0: Latches data at the falling edge shift polarity to the AJ3 bit. If there is no need to
of the dot clock pulses adjust the display timing signal, these bits may
be set to either (1, 0, 0, 0) or (0, 0, 0, 0).

R1

Data bit 7 6 5 4 3 2 1 0

Value — — — DOTE AJ3 AJ2 AJ1 AJ0

3 2 1 0 Number of Dots
Adjusted

0 0 0 0 0

0 0 1 –1
0 1 0 –2

1 0 0 0 0

0 0 1 +1

0 1 0 +2

0 1 1 +3
1 0 0 +4

1 0 1 +5

1 1 0 +6

Note: – (minus) and + (plus) in the Number of Dots Adjusted column indicate advancing and delaying
the display timing signal, respectively.

Figure 19 Input Timing Control Register

1416
 HD66850F
Horizontal Display Size Register: The horizontal Vertical Display Size Register: The vertical dis-
display size register (figure 20), composed of play size register (figure 21), composed of nine
seven valid bits, specifies the horizontal display valid bits, specifies the vertical display size in units
size in units of characters (eight dots). The value to of lines. The value to write to this register is
write to this register is “number of characters “number of lines displayed from display screen top
displayed on one horizontal line – 1.” A maximum to bottom – 1.” A maximum of 512 lines can be
of 90 characters (720 dots) can be specified. specified.

This register is set automatically in VGA mode. This register is set automatically in VGA mode.

R2

Data bit 7 6 5 4 3 2 1 0

Value — DH6 DH5 DH4 DH3 DH2 DH1 DH0

Figure 20 Horizontal Display Size Register

R3

Data bit 7 6 5 4 3 2 1 0

Value — — — — — — — DV8

Data bit 7 6 5 4 3 2 1 0

Value DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0

R4

Figure 21 Vertical Display Size Register

1417
HD66850F
Centering Raster Register: The centering raster the total number. Since the LCD panel size is
register (figure 22), composed of eight bits, determined by this number and the display size, the
specifies the number of rasters for vertically number of rasters must be correctly written if the
centering the display within the range of 1 to 256. display size differs from the LCD panel size.
The value to write to this register is “number of Incorrect setting disables correct display. This
rasters for centering – 1.” As shown in figure 23, register is enabled the control register’s CRE bit is
the number here indicates the number of rasters in 1. This register is set automatically in VGA mode.
either the upper border area or lower border area, not

R5

Data bit 7 6 5 4 3 2 1 0

Value CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

Figure 22 Centering Raster Register

Number of rasters Border area

(upper) (upper)

Display

Number of rasters Border area

(lower) (lower)

Figure 23 Centering Rasters

1418
 HD66850F
Centering Character Register: The centering LCD panel size is determined by this number and
character register (figure 24), composed of five the display size, the number of characters must be
valid bits, specifies the number of characters for correctly written when the display size differs from
horizontally centering the display within the range the LCD panel size. Incorrect setting disables
of 1 to 32. The value to write to this register is correct display. This register is enabled when the
“number of characters for centering – 1.” As control register’s CCE bit is 1.
shown in figure 25, the number here indicates the
number of characters in either the left border area This register is set automatically in VGA mode.
or right border area, not the total number. Since the

R6

Data bit 7 6 5 4 3 2 1 0

Value — — — CC4 CC3 CC2 CC1 CC0

Figure 24 Centering Character Register

Number of characters Number of characters

(left) (right)

Display
Border area Border area
(left) (right)

Figure 25 Centering Characters

1419
HD66850F
Border Color Control Register: The border color • BCI, BCR, BCG, and BCB bits: Specify the
control register (figure 26), has five valid bite color to be displayed on the border area. These
having two different functions. These functions are bits are enabled when the BM bit is 1; reset to
available only in with-memory mode. 0s.

• BM bit: Specifies border control mode; reset to Stretching Control Register: The stretching con-
0. This bit must be 1 in asynchronous mode. trol register (figure 27), composed of four valid
bits, is used in combination with the stretching
— BM = 1: Displays the color specified by the index register (R9 and R10). It specifies the period
BCI, BCR, BCG, and BCB bits in the border for stretching in units of lines. The value to write
area (disabled in synchronous mode) to this register is “number of lines –1.” This
register is enabled when the control register’s STE
— BM = 0: Displays the color of the dot
bit is 1.
immediately before the display period on the
border area This register is set automatically in VGA mode.

R7

Data bit 7 6 5 4 3 2 1 0

Value — — — BM BCI BCR BCG BCB

Figure 26 Border Color Control Register

R8

Data bit 7 6 5 4 3 2 1 0

Value — — — — SF3 SF2 SF1 SF0

Figure 27 Stretching Control Register

1420
 HD66850F
Stretching Index Register: The stretching index bits, only the bits within the period specified by R8
register (figure 28), composed of 16 valid bits, is are enabled. For example, when R8 is set to four,
used in combination with the stretching control only five bits of SI0 to SI4 of this register are
register (R8). It specifies the lines to be displayed enabled (figure 29).
twice among those specified by R8. The lines
represented by the SI bits which are set to 1s will This register is set automatically in VGA mode.
be displayed twice. Although this register has 16

R9

Data bit 7 6 5 4 3 2 1 0

Value SI15 SI14 SI13 SI12 SI11 SI10 SI9 SI8

Data bit 7 6 5 4 3 2 1 0

Value SI7 SI6 SI5 SI4 SI3 SI2 SI1 SI0

R10

Figure 28 Stretching Index Register

(R9, R10)

SI0 = 0 Line A Line A

Stretching SI1 = 1 Line B Line B

period
(R8 = 4) SI2 = 1 Line C Line B

SI3 = 0 Line D Line C

SI4 = 0 Line E Line C

SI0 = 0 Line F Line D

SI1 = 1 Line G Line E

• •
•
•
•
•
Line F
•
•
•

Figure 29 Stretching Display

1421
HD66850F
Gradation Level Palette Address Register: The • PA3–PA0 bits: Specify the desired gradation
gradation level palette address register (figure 30) level palette using the address written to these
is composed of six valid bits with two different bits. After palette address specification, data is
functions. read from or written to the specified palette and
the address is automatically incremented by 1.
• PS1 and FS0 bits: Specify a method of selecting The address increment manner depends on PS1
the plane of the gradation level palettes (R, G, or and PS0 settings.
B).
— (PS1, PS0) = (0, 0): Gradation level palette
— (PS1, PS0) = (0, 0): Every time the address is automatically incremented by 1
gradation level palette data register (R12) is after reading/writing data from/to R, G, and
read from or written to, either R-, G-, or B- B gradation level palettes in that order,
palette is automatically selected, in that through the gradation level palette data
order register

— (PS1, PS0) = (0, 1): R-palette is selected — Other settings: Gradation level palette
address is automatically incremented by 1
— (PS1, PS0) = (1, 0): G-palette is selected
after reading/writing data from/to any one
— (PS1, PS0) = (1, 1): B-palette is selected gradation level palette, through the gradation
level palette data register

R11

Data bit 7 6 5 4 3 2 1 0

Value — — PS1 PS0 PA3 PA2 PA1 PA0

Figure 30 Gradation Level Palette Address Register

1422
 HD66850F
Gradation Level Palette Data Register: The have elapsed after reset. Note that display is
gradation level palette data register (figure 31), scattered during palette read/write.
composed of six valid bits, contains data which is
read from or written to the gradation level palette In the MPU programming method, gradation level
specified with the gradation level palette address palettes are not directly read from, but are read
register (R11). from via this register. Consequently, any data that
happens to be in this register at that time is read
Gradation level palettes must be set according to out in the first read cycle, and then data
the display mode used (16-level grayscale display corresponding to the specified address is
or 4096-color-scale display); the R-palette must be transferred to this register and read from this
used for 16-level grayscale display, and R-, G-, and register in the following read cycle. The address is
B-palettes for 4096-color-scale display. PD5 bit incremented (or R-, G-, and B-palettes are
must be 1 and PD4 bit must be 0 in frame-based switched) at the same time. In other words, after
data thinning mode. PD4 bit must be 1 in 1/2 pulse address setting, the first data read is incorrect, and
width modulation mode. Show table 13. the second data read is correct. Consequently, one
dummy read is required after setting a gradation
In the MPU programming method, the gradation level palette address. Figure 32 shows the timing
level palettes must be read/written after 100 ms for reading a gradation level palette.

R12

Data bit 7 6 5 4 3 2 1 0

Value — — PD5 PD4 PD3 PD2 PD1 PD0

Figure 31 Gradation Level Palette Data Register

WR

RD
(N+1) (N+2)
D0–D7 $OB N $OC * (N)

Address * N N+1 N+2 N+3

Gradation level * * (N) (N+1) (N+2)

palette data register

(N): Data for address N

Figure 32 Gradation Level Palette Data Read

1423
HD66850F
Gradation Display Clock Period Register: The This register is set automatically in VGA mode.
gradation display clock period register (figure 33),
composed of nine valid bits, specifies the period of • GC8–GC0 bits: Specify the number of dots for
XCL1, the LCD data latch clock, when pulse width T1; T1 is the period of XCL1 for 1/2 pulse width
modulation method is used for gradation display. gradation display. When the total number of dots
The value to write to this register is “specified for one period of the YCL1 clock pulse cannot
number – 1,” in units of dots. Eight through 512 be divided by two for 1/2 pulse width gradation
dots can be specified. Note that this register is display, the remainder is added to T1 as T1’,
invalid in with-memory mode. where T1’ = TL – T1 (figure 34).

R13

Data bit 7 6 5 4 3 2 1 0

Value — — — — — — — GC8

Data bit 7 6 5 4 3 2 1 0

Value GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0

R14

Figure 33 Gradation Display Clock Period Register

TL

YCL1

T1’ T1

XCL1
(1/2 pulse width)

Figure 34 TL, T1, and T’

1424
 HD66850F
Reset Description
The RES signal resets and starts the CLINE. The • A0–A5: Always output 0s during the reset state
RES signal must be supplied at each power-on. in the ROM programming method. Otherwise,
Reset is defined as shown in figure 35. these pins serve as input pins.

Pin: In principle, the RES signal does not control Registers: The contents of all internal registers are
output signals and it operates regardless of other lost and cleared; the desired data must be rewritten
input signals. The reset states of input/output pins after reset.
are described below.
Palettes: Palettes are automatically loaded after
• D0–D7: Not affected by reset. These pins output reset with the appropriate data according to the
data even during the reset state when RD = 0, display mode. When data different from the
CS = 0, RS = 1, and WR = 1, in the MPU automatically set data is needed, the data must be
programming method. overwritten 100 µs or more after reset. (100 µs is
required for automatic data setting.)

0.8 V 0.8 V
RES
Reset state After reset

Figure 35 Reset Definition

1425
HD66850F
There are some restrictions and notices in the asserted width to operate correctly, please keep the
HD66850F. Please check the following content, asserted width with the below value or more.
and use it.
HSYNC to VSYNC, HSYNC to BLANK Phase
Input Signal Timing Shift: There are some restrictions between
HSYNC and VSYNC, and HSYNC and BLANK.
HSYNC, VSYNC Asserted Width: The HSYNC Don’t input them within the restricted phase shift.
and VSYNC input signals have the minimum

Table 16 HSYNC, VSYNC Asserted Width

Condition Item Symbol Minimum Dots

All mode Asserted HSYNC a 12 dots or more
Asserted VSYNC b 2 rasters or more

Table 17 VSYNC, BLANK Phase Shift

Condition Item Symbol Available Dots

All mode VSYNC c 3 dots or less, 16 dots or more
BLANK d 1 dot or more
Note: In VGA mode, the polarities of HSYNC and VSYNC depend on the display resolution on CRT, but we
will explain them as the active-high input in this document.

a
HSYNC
b
VSYNC

Figure 36 HSYNC, VSYNC Asserted Width

HSYNC
c
VSYNC
d
BLANK

Figure 37 VSYNC, BLANK Phase Shift

1426
 HD66850F
Total Horizontal Dots: HD66850F needs 48 dots Horizontal Front Porch: There is a restriction
for the horizontal retrace period, and the HSYNC about the horizontal front porch (from negated
period must be 688 dots or more when 640 dots BLANK to asserted HSYNC) as the below in VGA
display, 768 dots or more when 720 dots display. mode. Please input them with the minimum value
or more. Especially in 320 or 360 dots wide, period
of the front porch is usually just 3 or 4 dots. Please
delay HSYNC asserted timing, and hold the
minimum value. Otherwise the first line on a panel
will be incorrect.

Table 18 Total Horizontal Dots

Condition Symbol Minimum Dots

All mode e 688 dots (when 640 dots display)
768 dots (when 720 dots display)

Table 19 Horizontal Front Porch

Dot Adjust
Condition Symbol Item –2 –1 ±0 +1 +2 +3 +4 +5 +6
VGA mode f Horizontal 320 or 1 dot or more 3 dots or more 7 dots
640 dots display or
more
Horizontal 360 or 1 dot or more 5 dots or more
720 dots display
Note: The BLANK ‘High’ width (g) must be 328 or 336 dots in 320 dots display, 376 dots in 360 dots
display, 656 dots in 640 dots display, and 738 dots display in 720 dots display.

e
HSYNC

Figure 38 Total Horizontal Dots

g
BLANK
f
HSYNC
h

Figure 39 Horizontal Front Porch

1427
HD66850F
When it displays 720 dots wide (text mode) on 640 is 900 dots wide, and the period between negated
dots panel in VGA mode, HD66850F removes 1 BLANK to asserted HSYNC is ‘h’ dots,
dot from each 9 dots. It may not display correctly
according to the combination of the dot ajust and 4 × [(h - 2)/4 ↑] = 9 × M + A
the period from negated BLANK to asserted
(↑: revaluation, M and A: integer)
HSYNC (h in figure 4). In this case, please change
the dot adjust, or delay asserted timing of HSYNC. The ‘A’ which causes trouble depends on the dot
ajust as below.
This restriction causes trouble when the below
equation is satisfied. When the total horizontal dot

Table 20 Display Period + Horizontal Front Porch

Dot Adjust
Condition Symbol Item –2 –1 ±0 +1 +2 +3 +4 +5 +6
VGA mode h Monochrome 743 to 746 dots NG ok ok ok ok NG ok ok ok
& with or 8/16 colors
747 to 750 dots NG ok ok ok NG ok ok ok ok
buffer mode
memory 751 to 754 dots ok ok ok ok NG ok ok ok NG
mode, 720 755 to 758 dots ok ok ok NG ok ok ok ok NG
dots
display on 759 to 762 dots ok ok ok NG ok ok ok NG ok
640 dots 763 to 766 dots ok ok NG ok ok ok ok NG ok
panel
64/512/4096 743 to 764 dots ok NG ok ok ok ok NG ok ok
colors mode
747 to 750 dots ok NG ok ok ok NG ok ok ok
751 to 754 dots NG ok ok ok ok NG ok ok ok
755 to 758 dots NG ok ok ok NG ok ok ok ok
759 to 762 dots ok ok ok ok NG ok ok ok NG
763 to 766 dots ok ok ok NG ok ok ok ok NG
Note: The total horizontal dot must be 900 dots wide.

Dot Adjust
Parameter Item –2 –1 ±0 +1 +2 +3 +4 +5 +6
A Monochrome or 8/16 1 2 3 4 5 6 7 8 0
colors mode
6 7 8 0 1 2 3 4 5
64/512/4096 colors 0 1 2 3 4 5 6 7 8
mode
5 6 7 8 0 1 2 3 4

1428
 HD66850F
Automatic Judgement of VGA Display Resolu- and HSYNC, and the width of BLANK ‘H’
tion: In VGA mode, HD66850 judges the current automatically. Please input these signals as below
display resolution from the polarities of VSYNC, to judge the correct resolution.

Table 21 BLANK ‘High’ Level Width

Condition Symbol VGA Mode No. Horizontal Resolution BLANK H Width

VGA mode j 0/1 360 wide 378 dots
2/3, 7 720 wide 738 dots
4/5 320 wide 336 dots
6, F, 10, 11, 12 640 wide 656 dots
13 (256 col) 320 wide 328 dots

Table 22 Polarities of HSYNC and VSYNC

Condition VGA Mode No. Vertical Resolution HSYNC VSYNC

VGA mode F, 10 350 raster high Positive Negative
0/1, 2/3, 4/5, 6, 7, 13 400 raster high Negative Positive
11, 12 480 raster high Negative Negative

j
BLANK

Figure 40 BLANK High Level Width

1429
HD66850F
Border Area: In VGA mode, there is border area indicates just the display area from BLANK input.
around display area. When the border and display So, please input the BLANK with the horizontal
area is scanned, BLANK is ‘high’ level. HD66850 border dot wide and vertical border high raster as
internally generates the display timing which below.

Table 23 Number of Horizontal Border Dot

Condition Symbol VGA Mode No. Resolution Border

VGA mode k 0/1 360 9 dots
2/3, 7 720 9 dots
4/5 320 8 dots
6, F, 10, 11, 12 640 8 dots
13 (256 col) 320 4 dots

Table 24 Number of Vertical Border Raster

Condition Symbol VGA Mode No. Resolution Border

VGA mode m F, 10 350 6 rasters
0/1, 2/3, 4/5, 6, 7, 13 400 7 rasters
11, 12 480 8 rasters

Border Border
k Display
BLANK

Figure 41 Number of Horizontal Border Dot

m
HSYNC
Border Display
BLANK

Figure 42 Number of Vertical Border Raster

1430
 HD66850F
When 64 k × 4 bit (256 k) or 128 k × 8 (1M) bit Usually, the vertical 480 rasters mode (VGA mode
memory is attached for buffer memory, please 11, 12) has 6 or 7 border rasters, so this limitation
satisfy the below relationship about vertical display will be no problem.
and border raster.

[ Vertical
display raster
] + [ Vertical border
raster after display
]≤ 512
raster

Table 25 Vertical Display Raster + Vertical Border Raster After Display

Vertical Display Raster +

Condition Symbol Vertical Border Raster after Display
VGA and with memory mode n 512 rasters or less

n
VSYNC display raster
Border Display Border
BLANK

Figure 43 Vertical Display Raster

1431
HD66850F
Asynchronous Mode and start to display just from left edge on an LCD
panel without border dot, rise the BLANK input at
In asynchronous mode, the set data in the gradation same DOTCLK edge as change of the video data
palette is broken owing to the dot adjust during (R/G/B).
display. To avoid this problem, in MPU and ROM
programming method, please write ‘1’ to bit 4 In 8/16 colors mode, this restriction is no problem
(BM mode) of the border control register (R7), and in any mode because HD66850F does not access
all ‘0’ to bit 3-0 (border color) of R7. The register the gradation palette. In 64 / 512 / 4096 colors
R7 must be ‘10H’. In pin programming method, mode, it does not support asynchronous mode.
please adjust display timing with AJ3-AJ0 pins,

Same edge for DOTCLK

DOTCLK

BLANK
R/G/B Border color Display Display

Figure 44 Countermeasure in the Pin Programming Method

1432
 HD66850F
Frame Period change at different line in each frame. But period
of the signal M may synchronize with the frame
In synchronous with-memory mode, DOTCLK and period according to the total vertical raster. In this
frame period for CRT are same as one for LCD. case, adjust period of the M, and don’t synchronize
When it displays on a full screen with stretching or them.
centering function, HD66850F needs to extend the
frame period for displaying on LCD. If this frame Especially, it is easy to synchronize them in VGA
period for LCD were longer than one for CRT, 720 × 400 dots mode. For example, when it
HD66850F can not work correctly. displays 720 × 400 dots in synchronous with-
memory mode, usaually number of the total
HD66850F needs 48 dots period for the horizontal horizontal dot for CRT is 900 dots wide, and
retrace, and number of the total horizontal dot for number of the total vertical raster is 448 rasters
LCD is number of the horizontal display dot + 48 high, so the frame period for CRT is 900 × 448 =
dots. This minimum frame period which is 403,200 [dots]. On the other hand, number of the
necessary to display on LCD is shown as below. total horizontal dot for LCD is 720 + 48 = 768 dots
wide, and the frame period (403,200 dots) divided
Minimum frame Number of horizontal by a total horizontal dot for LCD (768 dots) is 512
period for LCD
= (
display dot
+ 48 ) which is interger. So, when line number of period
× Vertical panel size [dots] of the M equals to the following divisor of 512:

[1, 3, 5, 7, 15, 21, 25, 35, 75, 105, 175] (lines),

The frame period for CRT must be longer than the
above minimum one for LCD. period of the M synchronizes with the frame
period, and a horizontal bright line is appeared
For example, when HD66850F stretchs CRT
when the M is changed.
resolution with 640 × 350 dots to the LCD panel
with 640 × 480 dots, the minimum frame period Vertical Centering
for LCD is (640 + 48) × 480 = 330, 240 dots.
Number of vertical centering line depends on ‘the
On the other hand, when number of the total value in register (R5) + 1’ in non-VGA mode, or
horizontal dot for CRT is 800 dots wide, 330, on the VSIZE pin and display resolution in VGA
240/800 = 412.8 rasters, so HD66850F needs 413 mode. But when ‘0’ is written in the register (R5)
or more rasters high as the total vertical raster for and the vertical centering is enabled, HD66850F
CRT. can not works correctly. Don’t set ‘0’ in the
register (R5). And when number of vertical display
In asynchronous mode, HD66850F separates LCD
raster is same as the vertical panel size (VSIZE),
clock (LDOTCK) from CRT clock (DOTCK), and
the vertical centering enable bit (bit 3 in R0) must
the both frame period are different. So, this
be cleared. Especially in VGA mode, please update
limitation is no problem.
the enable bit according to selected VGA display
LCD Alternating Signal M mode.

When LCD alternating signal M is changed at When stretching function is selected, there is no
same line in each frame, brightness of the line restriction about setting ‘0’ in the stretching
differs from one of another line. To avoid this registers (R8, R9, R10).
problem, the signal M is ususally controlled to

1433
HD66850F
Table 26 Notes on VGA Mode Usage by LCD Panel Size

Horizontal Vertical
Size (dots) Size (lines) Notes
640 — • In VGA text modes (0/1, 2/3, 7), there is no space between characters.
720 — • In VGA graphic modes (4/5, 6, F, 10, 11, 12, 13), horizontal centering is
necessary. (Display is automatically centered horizontally in with-
memory mode. See note below.)
— 400 • Data on line 401 through line 480 in VGA 640-by-480 graphic modes
(11, 12) are not displayed.
• Vertical centering or stretching is necessary for VGA 640-by-350 graphic
modes (F, 10). (Display is automatically stretched in with-memory mode.
See note below.)
— 480 • Vertical centering or stretching is necessary for VGA text modes
(0/1, 2/3, 7). (Display is automatically stretched in with-memory mode.
See note below.)
• Vertical centering or stretching is necessary for VGA 640-by-200 or
320-by-200 graphic modes (4/5, 6, 13). (Display is automatically
stretched in with-memory mode. See note below.)
• Vertical centering or stretching is necessary for VGA 640-by-350 graphic
modes (F, 10). (Display is automatically stretched in with-memory mode.
See note below.)
Note: For without-memory mode, external circuits or BIOS tuning are required.

1434
 HD66850F
Table 27 Notes on Internal Register Settings

Notes
Register
No. Bits Register or Bit Function VGA Non-VGA
R0 STE Stretching enable 1 1
R0 CRE Vertical centering enable 2 2
R0 CCE Horizontal centering enable 3 4
R0 SP Double-width display set 5 4
R0 DISPON Display on 6 6
R1 DOTE Dot clock phase select 4 4
R1 AJ3–AJ0 Display timing adjust 4 4
R2 DH6–DH0 Display horizontal size set 7 4
R3–R4 DV8–DV0 Display vertical size set 8 4
R5 CR7–CR0 Centering raster set 8 4
R6 CC4–CC0 Centering character set 3 4
R7 BM Border control mode select 9 9
R7 BCI, BCR, BCG, BCB Border color select 10 10
R8 SF3–SF0 Stretching period 8 4
R9–R10 SI15–SI0 Stretching index set — —
R11 PS1–PS0 Gradation display palette select 11 11
R11 PA3–PA0 Gradation display palette address set
R12 PD5–PD0 Gradation level palette data set
R13–R14 GC8–GC0 Gradation display clock period set 7 12
Notes: 1. Simultaneous use with vertical centering function is impossible.
2. Simultaneous use with stretching function is impossible.
3. Automatically set for a 640- or 320-dot-wide display on a 720-dot-wide LCD panel; cannot be
rewritten.
4. Must be set after reset.
5. Automatically set for a middle-resolution display; cannot be rewritten.
6. Display will turn on four frames after reset. Display will not turn on during four frames after
reset.
7. Automatically set according to the horizontal panel size and number of displayed horizontal
dots; cannot be rewritten.
8. Automatically set according to the vertical panel size and polarity of HSYNC and VSYNC
signals; cannot be rewritten.
9. Available only in with-memory mode.
10. Available only in asynchronous with-memory mode.
11. In the MPU programming method, automatically set for 16-level display after reset; can be
rewritten 100 µs after reset. In ROM programming method, appropriate data must be written.
12. In with-memory mode, automatically set according to the horizontal panel size and number
ofdisplayed horizontal dots; cannot be rewritten. For without-memory mode, appropriate data
must be written after reset.

1435
HD66850F
Table 28 Limits on Register Values

Register Function Applied to Limits

Horizontal display R2 4 ≤ Nchd ≤ (R2 + 1) ≤ 90 (HSIZE = 1)
size control 4≤ Nchd ≤ (R2 + 1) ≤ 80 (HSIZE = 0)
Vertical display R3, R4 4 ≤ Ncvd ≤ (R3, R4 + 1) ≤ 512
size control
Vertical centering R3, R4, R5 2 ≤ (R5 + 1) ≤ 256
(R5 + 1) × 2 + Ncvd = (R3, R4 + 1)
Horizontal centering R2, R6 2 ≤ (R6 + 1) ≤ 32
(R6 + 1) × 2 + Nchd = (R2 +1)
Gradation display R13, R14 (R13, R14 + 1) = (Ncht × 8)/n (MMODE1 = 1)
clock period control n: 2 for 1/2 pulse width gradation display
(R2 + 1) + 8 ≤ Ncht (NMODE1 = 0)
Miscellaneous R2, R3, R4 1/2fDOTCLK ≤ {(R + 1) + 6} × 8 ×
(R3, R4 + 1) × fFLM ≤ 2fDOTCLK
(SYNC = 0)
Ncht: Total number of characters on a CRT horizontal line
(total number of dots on a CRT horizontal line × 1/8)
Nchd: Number of characters displayed on a CRT horizontal line
(number of dots displayed on a CRT horizontal line × 1/8)
Ncvd: Number of lines displayed from screen top to bottom on the CRT display
f LDOTCK: LCD dot clock frequency
fDOTCLK: CRT dot clock frequency
fFLM: Frame frequency

1436
 HD66850F
Absolute Maximum Ratings
Item Symbol Ratings Unit
Power supply voltage VCC –0.3 to 7.0 V
Input voltage Vin –0.3 to VCC + 0.3 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Notes: 1. Permanent LSI damage may occur if maximum ratings are exceeded.
Normal operation should be under recommended operating conditions (VCC = 5.0 ± 10%, GND
= 0V, Ta = –20°C to +75°C. (If these conditions are exceeded, LSI reliability may be affected.
2. All voltages are referenced to GND = 0 V.

Electrical Characteristics
DC Characteristics (VCC = 5.0 V ± 10%, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)

Item Symbol Min Max Unit Test Condition

Input high- RES pin VIH VCC – 0.5 — V
level
DOTE/RD/A5, SP/WR/A4 2.2 — V
voltage
Other input pins*1 2.0 — V
Input low-level VIL — 0.8 V
voltage
Output high- TL interface pins*2 VOH 2.4 — V IOH = –200 µA
level voltage
CMOS interface pins*3 VCC –0.8 — V IOH = –200 µA
Output low- TTL interface pins*2 VOL — 0.4 V IOL = 1.6 mA
level voltage
CMOS interface pins*3 — 0.8 V IOL = 200 µA
Input leakage current ITL –2.5 +2.5 µA
Three-state leakage current ITSL –10.0 10.0 µA
Current consumption ICC — 100 mA Output pins open
Notes: 1. Other input pins: DOTCLK, HSYNC, VSYNC, BLANK, MS0–MS15, LDOTCK, D0–D7,
AJ3/CS/A3, AJ2/RS/A2, AJ1/A1, AJ0/A0, R0–R3, G0–G3, B0–B3, PMODE1, PMODE0,
LMODE0–LMODE4, MMODE1, MMODE0, SYNC, VMODE, VSIZE, HSIZE, TEST1, TEST0
2. TTL interface output pins: D0–D7, DOTE/RD/A5, SP/WR/A4, AJ3/CS/A3, AJ2/RS/A2, AJ1/A1,
AJ0/A0, MD0–MD15, MA0–MA7, MA8/SOE1, SOE0, WE, DT/OE, RAS1, RAS0, CAS, CASL,
SC
3. CMOS interface output pins: UD0–UD7, LD0–LD7, XCL1, YCL1, CL2, FLM, M, SCLK,
DISPON, DATAE

1437
HD66850F
AC Characteristics (VCC = 5.0 V ± 10%, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)

Video interface

No. Item Symbol Min Max Unit Reference

1 DOTCLK cycle time TCYCD 31.2 62.5 ns Figure 45
2 DOTCLK low-level pulse width tWDL 15 — ns
3 DOTCLK high-level pulse width tWDH 15 — ns
4 DOTCLK rise time tDr — 5 ns
5 DOTCLK fall time tDf — 5 ns
6 Video data setup time tVDS 10 — ns
7 Video data hold time tVDH 10 — ns
8 BLANK setup time tBLS 10 — ns
9 BLANK hold time tBLH 10 — ns
10 BLANK low-level pulse width tBLW — 12 µs
11 BLANK phase shift tBLPD 2Tc — ns
12 Phase shift setup time tPDS 2Tc — ns
13 Phase shift hold time tPDH 2Tc — ns
Tc: DOTCLK cycle time

1438
 HD66850F

1
4 5
3 2

DOTCLK 2.0 V 1.5 V 1.5 V

1.5 V
0.8 V 0.8 V
6
7

R0–R3 2.0 V
G0–G3 0.8 V
B0–B3 8 9

BLANK 2.0 V
0.8 V

10

BLANK 0.8 V 0.8 V

11

HSYNC 2.0 V
VSYNC 0.8 V

HSYNC 0.8 V 0.8 V

13 12

2.0 V
VSYNC 0.8 V

Figure 45 Video Interface

1439
HD66850F
Memory Interface

No. Item Symbol Min Max Unit Reference

14 RAS cycle time tRC 12Tc – 10 — ns Figure 46
15 RAS low-level pulse width tRAS 5Tc 128Tc – 20 ns
16 RAS high-level pulse width tRP 4Tc – 40 — ns
17 CAS hold time tCSH 6Tc – 50 — ns
18 RAS, CAS delay time tRCD 3Tc – 40 — ns
19 CAS low-level pulse width tCAS1 3Tc – 35 — ns
20 CASL low-level pulse width tCAS2 2Tc – 30 — ns
21 CAS high-level pulse width tCP1 1Tc – 20 — ns
22 CASL high-level pulse width tCP2 2Tc – 20 — ns
23 CAS cycle time tPC 4Tc – 20 — ns
24 RAS hold time tRSH 4Tc – 40 — ns
25 Row address setup time tASR 2Tc – 50 — ns
26 Row address hold time tRAH 2Tc – 30 — ns
27 Column address setup time tASC 1Tc – 30 — ns
28 Column address hold time tCAH 2Tc – 40 — ns
29 WE setup time tWS 2Tc – 50 — ns
30 WE hold time tWH 2Tc – 40 — ns
31 Memory data setup time tMDS 1Tc – 30 — ns
32 Memory data hold time tMDH 2Tc – 35 — ns
33 Data transfer DT/OE setup time tDTS 2Tc – 50 — ns Figure 47
34 Data transfer DT/OE hold time tDTH 6Tc – 50 — ns
35 Phase shift between CAS and tCDH 2Tc – 40 — ns
DT/OE
36 Phase shift between CAS and tDTR 2Tc – 50 — ns
DT/OE
37 CAS setup time tCSR 2Tc – 50 — ns Figure 48
38 CAS hold time tCHR 6Tc – 50 — ns
39 Phase shift between RAS and CAS tRPC 2Tc – 50 — ns
40 SC cycle time tSCC 4TL – 10 — ns Figure 49
41 SC high-level pulse width tSC 2TL – 50 — ns
42 SC low-level pulse width tSCP 2TL – 50 — ns
43 Memory data read setup time tRDS 40 — ns
44 Memory data read hold time tRDH 5 — ns
45 Phase shift between SOE and SC tDSE 20 — ns
TC: DOTCLK cycle time
TL: LDOTCK cycle time (= TC for synchronous mode)

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 HD66850F

14
15

2.4 V
RAS
0.8 V
17 16
23 24
18
19 , 20 19
CAS 2.4 V 2.4 V
21 , 22
0.8 V 0.8 V
CASL
25 26 27 28 27 28

2.4 V
MA0–8
0.8 V
29 30

WE

31 32 31 32

2.4 V
MD0–15 0.8 V

Figure 46 Memory Interface (Write)

2.4 V
RAS
0.8 V

CAS 0.8 V

35
33 34 36

DT/OE 2.4 V
0.8 V 0.8 V

Figure 47 Memory Interface (Data Transfer)

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HD66850F

RAS 2.4 V
0.8 V
39 37 38

2.4 V
CAS
0.8 V

Figure 48 Memory Interface (Refresh)

40

42
2.4 V
41
SC 0.8 V 0.8 V
43 44 43 44

2.0 V 2.0 V
MS0–15 0.8 V 0.8 V

45

2.4 V
SOE0 – 1 0.8 V

Figure 49 Memory Interface (Serial Read)

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 HD66850F
LCD Driver Interface

No. Item Symbol Min Max Unit Reference

46 CL2 cycle time tWCL2 2TL – 10*1 — ns Figure 50
4TL – 10*2
8TL – 10*3
16TL – 10*4
47 CL2 high-level pulse width tWCL2H 1TL – 40*1 — ns
2TL – 40*2
4TL – 40*3
8TL – 40*4
48 CL2 low-level pulse width tWCL2L 1TL – 40*1 — ns
2TL – 40*1
4TL – 40*2
8TL – 40*4
49 CL1 high-level pulse width tWCL1h 150 — ns
50 LCD data delay time tDD — 30 ns
51 CL1 setup time tSCL1 200 — ns
52 CL1 hold time tHCL1 200 — ns
53 M output delay time tDM — 100 ns
54 FLM setup time tHF 100 — ns
55 LDOTCK cycle time tCYCL 31.2 100 ns
56 LDOTCK high-level pulse width tWLH 15 — ns
57 LDOTCK low-level pulse width tWLL 15 — ns
58 LDOTCK rise time tLr — 5 ns
59 LDOTCK fall time tLf — 5 ns
TL: LDOTCK cycle time (= TC for synchronous mode)
Notes: 1. For display modes 9, 13, 16, 19, and 20
2. For display modes 1, 5, 10, 11, 14, 15, 17, and 18
3. For display modes 2, 3, 6, 7, and 12
4. For display modes 4 and 8

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HD66850F

46
48
0.7 Vcc
CL2 47
0.3 Vcc
50 50 50

UD0 – 7 0.7 Vcc

LD0 – 7 0.3 Vcc
51 52

0.7 Vcc
CL1 49 0.3 Vcc
54

FLM 0.7 Vcc

53

0.7 Vcc
M 0.3 Vcc
55 59 58
57
LDOTCK 2.0 V
56 1.5 V
0.8 V

Figure 50 LCD Driver Interface

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 HD66850F
MPU Interface

No. Item Symbol Min Max Unit Reference

60 RD low-level pulse width tWRDL 4TC + 10 — ns Figure 51
61 RD high-level pulse width tWRDH 4TC + 10 — ns
62 WR low-level pulse width tWWRL 4TC + 10 — ns
63 WR high-level pulse width tWWRH 4TC + 10 — ns
64 RD input inhibited time tRIH 4TC + 10 — ns
65 WR input inhibited time tWIH 4TC + 10 — ns
66 Address setup time tAS 0 — ns
67 Address hold time tAH 0 — ns
68 Data delay time tDDR — 100 ns
69 Data output hold time tDHR 10 — ns
70 Data setup time tDSW 0 — ns
71 Data hold time tDHW 0 — ns
TC: DOTCLK cycle time

64 60 61

RD
2.2 V
0.8 V
65 62 63

2.2 V
0.8 V
WR
66 67 66
67

RS
2.0 V
CS 0.8 V
68 69 70 71

2.4 V 2.0 V
D0 – D7 0.8 V 0.8 V

Figure 51 MPU Interface

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HD66850F
ROM Interface

No. Item Symbol Min Max Unit Reference

72 ROM address cycle time tCYCA 16TC – 20 — ns Figure 52
73 ROM data setup time tDSWD 150 — ns
74 ROM data hold time tDHWD 10 — ns
TC: DOTCLK cycle time

RES Timing

No. Item Symbol Min Max Unit Reference

75 RES low-level pulse width tRES 1 — µs Figure 53

72

2.4 V
A0–A5
0.8 V
73 74

D0–D7 2.0 V
0.8 V

Figure 52 ROM Interface

75

RES
0.8 V

Figure 53 Reset Timing

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 HD66850F
Load Circuit

Pins RL R C Reference
MA0 – MA7, MA8/SOE1, DT/OE, WE, CAS, CASL, 2.4 kΩ 11 kΩ 40 pF Figure 54
RAS0, RAS1, SOE0, MD0 – MD15, D0 – D7, A0/AJ0,
A1/AJ1, A2/RS/AJ2, A3/CS/AJ3, A4/WR/SP, A5/RD/DOTE
DISPON, DATAE, SCLK, M, FLM, CL2, YCL1, XCL1, — — 40 pF Figure 55
LD0 – LD7, UD0 – UD7

+5 V
C: 40 pF
R: 11 k Ω
RL
RL: 2.4 k Ω

All diodes are

1S2074 H
C R

Applicable pins: MA0–MA7, MA8/SOE1, DT/OE, WE, CAS, CASL, RAS0, RAS1, SOE0,
MD0–MD15, D0-D7, A0/AJ0, A1/AJ1, A2/RS/AJ2, A3/CS/AJ3, A4/WR/SP,
A5/RD/DOTE

Figure 54 TTL Load Circuit

40 pF

Applicable pins: DISPON, DATAE, SCLK, M, FLM, CL2, YCL1, XCL1, LD0 – LD7, UD0 – UD7

Figure 55 Capacitive Load Circuit

1447