EED 2003 Logic Design Report of Laboratory Experiment #4

Student Name 1: Mikail DURAN ID 1:2015502030

Student Name 2: Enver Kaan ÇABUK ID 2:2015502085
Group : B1-15

Procedure

Part 1:

We wired the logic circuit Figure 1. We tested it using switches and leds on our breadboards.

R
Q

Q̄
S

Figure 1: RS Flip – Flop

S R Q Q¯

0 1 0 1

0 0 0 1

1 0 1 0

1 1 0 0

1 0 1 0

0 0 1 0

Table 1

1
 Figure 2: SR filip flop design on breadboard

Part 2

We wired the logic circuit Figure 3. We tested it using switches and leds on our breadboards.

Figure 3: D Type Flip – Flop

CP D Q Q¯

1 0 0 1

1 1 1 0

0 1 1 0

0 0 1 0

1 0 0 1
Table 2

2
 Figure 4: D Type Flip – Flop design on beradboard

Part 3

We wired the logic circuit Figure 5. We tested it using switches and leds on our breadboards.

3
 Figure 5: JK Flip-Flop

Pr Cr Clk J K Q
Q¯
0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0 1 0
0 1 0 0 1 1 0
0 1 0 1 0 1 0
0 1 0 1 1 1 0
0 1 1 0 0 1 0
0 1 1 0 1 1 0
0 1 1 1 0 1 0
0 1 1 1 1 1 0
1 0 0 0 0 0 1
1 0 0 0 1 0 1
1 0 0 1 0 0 1
1 0 0 1 1 0 1

4
 1 0 1 0 0 0 1
1 0 1 0 1 0 1
1 0 1 1 0 0 1
1 0 1 1 1 0 1
1 1 0 0 0 No change
1 1 0 0 1 0 1
1 1 0 1 0 1 0
1 1 0 1 1 Toogle
1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

Table 3

Figure 6: JK Flip-Flop design on breadboard

Part 4

5
 We tested the 74109 by applying a slow square wave (0-5V) clock signal to the clock input and using
switches for the inputs. We connected the outputs and the clock signal to the LED’s on our
breadboards to observe the situation.

PRE
J Q

K Q̄

CLK

CLR

Figure 7: 74109 JK Flip-Flop

6
Pr Cr Clk J K Q
Q¯
0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0 1 0
0 1 0 0 1 1 0
0 1 0 1 0 1 0
0 1 0 1 1 1 0
0 1 1 0 0 1 0
0 1 1 0 1 1 0
0 1 1 1 0 1 0
0 1 1 1 1 1 0
1 0 0 0 0 0 1
1 0 0 0 1 0 1
1 0 0 1 0 0 1
1 0 0 1 1 0 1
1 0 1 0 0 0 1
1 0 1 0 1 0 1
1 0 1 1 0 0 1
1 0 1 1 1 0 1
1 1 0 0 0 No change
1 1 0 0 1 0 1
1 1 0 1 0 1 0
1 1 0 1 1 Toogle
1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

7
 Table 4

Figure 8: 74109 JK Flip-Flop design on beradboard

Conclusion
In this experiment, we observed flip-flop circuit .We constructed RS flip flop, D flip flop and JK flip
flop.

First circuit is a RS flip flop.It has a two input.And we designed the circuit with two NOR gates.We
changed the input and we compare the our truth table.They are matched.We observed some
changing of inputs did not affect the outputs.

Second circuit is D flip flop.It has two inputs.And we designed the circuit with five NAND gate.We
changed the input and we compare the our truth table .They are matched. We observed some
changing of inputs did not affect the outputs.

Third circuit is JK flip flop.It has five inputs.And one of input is a clock signal.We constructed the
circuit with nine NAND gates(7400 has two inputs.And we use five.7410 has three inputs.And we use
four.)We changed the input and we compared the our truth table.They are matched. We observed
some changing of inputs did not affect the outputs.

8
Fifth is simplified JK flip flop.It has a five input.And we constructed with integrated circuit which its
datasheet number is 74109. We changed the input and we compared the our truth table.They are
matched. We observed some changing of inputs did not affect the outputs.

At the end , we observed memory of integrated circuits. And we verified the theorical informations
about flip flops in this experiment