HDL Designer Series™ Release Notes

Release v2019.4

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 Table of Contents

Chapter 1
Configuration and Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Supported Platforms and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Platform Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System Requirements on Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Verifying Fonts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Required Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
System Requirements on Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
New Features and Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
External Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Support Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
User Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 2
Known Problems and Workarounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
List of Problems and Workarounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Broken Links in PDF Documentation (MG595892) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Chapter 3
Corrected Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Software Version 2019.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Software Version 2019.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
End-User License Agreement
with EDA Software Supplemental Terms

HDL Designer Series™ Release Notes, v2019.4 3

 Table of Contents

4 HDL Designer Series™ Release Notes, v2019.4

 Chapter 1
Configuration and Compatibility

This document provides an overview of the v2019.4 release of the HDL Designer Series (HDS)
tool.
Supported Platforms and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Platform Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System Requirements on Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System Requirements on Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
New Features and Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
External Tool Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Support Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
User Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

HDL Designer Series™ Release Notes, v2019.4 5

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Configuration and Compatibility
Supported Platforms and System Requirements

Supported Platforms and System

Requirements
Refer to the list of supported platforms and system requirements for details on the v2019.4
release.
Platform Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System Requirements on Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System Requirements on Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Platform Availability
HDL Designer Series is supported on specific platforms.
• Microsoft® Windows® 10 (64 bit)
• Microsoft Windows 7 (64 bit)

• Red Hat® Enterprise Linux®1 (RHEL) 7 (64 bit)

• Red Hat Enterprise Linux 6 (64 bit)
All the following HDL Designer Series tools are true 64-bit applications: HDL Designer
executable (hdldesigner.exe), DesignChecker executable and engines, Register Assistant, and
SystemVerilog-VHDL Assistant.

Platforms Discontinued
Support for Windows 7 will be discontinued starting release 2020.1.

1. Linux® is a registered trademark of Linus Torvalds in the U.S. and other countries.

6 HDL Designer Series™ Release Notes, v2019.4

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 Configuration and Compatibility
System Requirements on Linux

System Requirements on Linux

HDL Designer Series requires minimum system specifications on Linux.
• Approximately 1.2 GB available hard-disk space
• At least 2 GB RAM and 8MB VRAM
• High color (16-bit or 65536 colors) at minimum resolution 1280x1024
Verifying Fonts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Required Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Verifying Fonts
If you are using Red Hat Enterprise Linux 6 or 7, you can encounter errors on the invocation of
HDL Designer Series if some fonts are not found. You must verify that these required fonts are
installed.
• xorg-x11-fonts-ISO8859-1-75dpi
• xorg-x11-fonts-ISO8859-1-100dpi
Procedure
1. Determine the font path:
xset -q

For example, the font path may be as follows:

/usr/share/X11/fonts/misc
Check the font to see if the 75dpi and 100dpi Helvetica fonts are included. If not,
proceed with the next steps.
2. Include the required fonts in the font path:
xset +fp /usr/share/X11/fonts/75dpi
xset +fp /usr/share/X11/fonts/100dpi

3. Rebuild the fonts cache:

xset fp rehash

4. Check the font path again:

xset -q

The new font paths should be as follows:

/usr/share/X11/fonts/100dpi
/usr/share/X11/fonts/75dpi

HDL Designer Series™ Release Notes, v2019.4 7

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Configuration and Compatibility
System Requirements on Linux

/usr/share/X11/fonts/misc
5. Verify that the Helvetica fonts are available:
/usr/bin/xlsfonts | grep adobe-helvetica

6. Verify that the Courier fonts are available:

/usr/bin/xlsfonts | grep courier

Note
If the 75dpi and 100dpi directories are missing, ensure that the fonts installed are of
type ISO. For example:
yum install xorg-x11-fonts-ISO8859-1-75dpi.noarch

Required Libraries
Additional packages are required for running HDL Designer Series on a Linux system. If you
do not have the required packages, you may receive errors related to missing libraries.
The following table lists the required packages and the corresponding sub-tool for which the
package is required, namely HDL Designer (HD), DesignChecker (DC), Register Assistant
(RA), and SystemVerilog-VHDL Assistant (SVA).
Table 1-1. Required Libraries
Package Name HD DC RA SVA
compat-libstdc++.x86_64 Yes
expat.x86_64 Yes Yes
fontconfig.x86_64 Yes Yes
freetype.x86_64 Yes Yes
glibc.x86_64 Yes Yes Yes Yes
gtk2.x86_64 Yes Yes
gtk2-engines.x86_64 Yes Yes
libcanberra-gtk2.x86_64 Yes Yes
libgcc.x86_64 Yes Yes Yes Yes
libICE.x86_64 Yes Yes Yes Yes
libjpeg-turbo.x86_64 Yes Yes
libpng.x86_64 Yes Yes
libpng12.x86_64 (RHEL 7 only) Yes Yes
libSM.x86_64 Yes Yes Yes Yes

8 HDL Designer Series™ Release Notes, v2019.4

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 Configuration and Compatibility
System Requirements on Linux

Table 1-1. Required Libraries (cont.)

Package Name HD DC RA SVA
libstdc++.x86_64 Yes Yes
libuuid.x86_64 Yes Yes Yes Yes
libX11.x86_64 Yes Yes Yes Yes
libXau.x86_64 Yes Yes Yes Yes
libxcb.x86_64 Yes Yes Yes Yes
libXext.x86_64 Yes Yes
libXft.x86_64 Yes Yes
libXmu.x86_64 Yes Yes
libXp.x86_64 Yes Yes
libXrender.x86_64 Yes Yes
libXt.x86_64 Yes Yes Yes Yes
libXtst.x86_64 Yes Yes
motif.x86_64 (RHEL 7only) Yes Yes
nss-softokn-freebl.x86_64 Yes Yes
openmotif.x86_64 (RHEL 6 only) Yes Yes
packagekit-gtk-module.x86_64 Yes Yes
webkitgtk.x86_64 (1.2.x and newer) Yes
xulrunner.x86_64 (1.9.2) Yes
zlib.x86_64 Yes Yes
You can use the yum command to install missing libraries. For example:

yum install glibc.x86_64

Note
If you are using QAS (Quest Authentication Services), you should install libns-vas4.so.
Similarly, if you are using LDAP protocol (Lightweight Directory Access Protocol), you
should install libnss_sss.so.

Missing Libraries Check

HDL Designer Series provides the dep_check.sh utility, which enables you to check the existing
libraries on your Linux system or the dynamic dependencies for HDS executables. These
checks help you identify any missing libraries you need to install from those listed in Table 1-1.

HDL Designer Series™ Release Notes, v2019.4 9

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Configuration and Compatibility
System Requirements on Windows

You can run the script located on the path <HDS_install_dir>/bin/dep_check.sh using one of
the following modes:

• Existing Libraries Check — Run the script using the -c option to check the libraries
already available on your Linux system. This mode requires sudo permission.
dep_check.sh -c

• Dynamic Dependencies Check — Run the script using the -l option to check the
dynamic dependencies for all sub-tools, including HDL Designer, DesignChecker,
Register Assistant, and SystemVerilog-VHDL Assistant.
dep_check.sh -l

You can optionally check dynamic dependencies for a specific sub-tool, for example,
SystemVerilog-VHDL Assistant.
dep_check.sh -l svva

Note
The following command provides details on the available options:

dep_check.sh -help

System Requirements on Windows

HDL Designer Series requires minimum system specifications on Windows.
• Approximately 1.2 GB available disk space
• At least 2 GB RAM and 8MB VRAM
• High color (16-bit or 65536 colors) at minimum resolution 1280x1024

TCP/IP Configuration
TCP/IP networking must be enabled in the Windows control panel if you want to use
downstream tools for compilation and simulation.

Display Configuration
You should set your monitor display properties to use the maximum number of colors (16-bit
high color or better on Windows), small fonts, and the maximum desktop area.

Extended Pathnames
The HDL Designer Series products support extended pathnames. However, if you want to use
an external text editor or downstream tool that does not support spaces in absolute pathnames,
you should ensure that your design data is stored using pathnames without any spaces or
nonstandard characters.

10 HDL Designer Series™ Release Notes, v2019.4

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 Configuration and Compatibility
New Features and Enhancements

Log Window Timeout

Interprocess communication protocol is used to communicate with downstream tools. This
protocol can sometimes be unreliable on a Windows computer and it may not be possible to re-
invoke the downstream simulator from within HDL Designer.

If this problem occurs, you should set the HDS_LOG_TIMEOUT environment variable to a
low value (such as 5 seconds) to ensure that the log displayer process stops after exiting the
simulator and does not prevent the simulator from being re-invoked.

If you specify a very short timeout, some of the output from the downstream tool may be lost. If
you specify a very long timeout, the log displayer process may take a long time to end.

Anti-Virus Software
If you experience problems running downstream tools on a Windows computer, this may be
caused by the anti-virus software treating the communications pipe as a file.

This results in the pipe being opened in a “deny all” mode which prevents client software from
reading or writing to the pipe. You can avoid this problem by configuring the anti-virus
software to scan program files only. Alternatively, contact the vendor of your anti-virus
software for advice on configuring the software so that it does not prevent communications
between client applications.

Some anti-virus programs can change the case of a filename or automatically delete files with
certain file extensions. For example, problems may occur if the virus checker has been
configured to quarantine files with extensions used by HDL Designer resource files such as
visual resource files (.vrf) files.

New Features and Enhancements

The v2019.4 release includes the following new features and enhancements.

HDL Designer
• Simplified Vivado integration flow
o Side data constraint files support
• Missing libraries check support on Linux using dep_check.sh script

SystemVerilog -VHDL Assistant

• High-level Block Diagram visualization
• Visualizer integration
• Multiple simulation configurations

HDL Designer Series™ Release Notes, v2019.4 11

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Configuration and Compatibility
Installation and Licensing

• SystemVerilog Find References support

• SystemVerilog performance improvements
o Scalability mode support

DesignChecker
• General bug fixes

Installation and Licensing

HDL Designer Series provides two installers: HDL Designer and HDL Text. HDL Designer
enables you to install Design Manager, SystemVerilog-VHDL Assistant, DesignPad,
DesignChecker, and Register Assistant. HDL Text enables you to install SystemVerilog-VHDL
Assistant and DesignChecker only.
Note
HDL Author is no longer available in the installer. If you are using HDL Author, you must
do the following to invoke HDL Designer in Author mode:

• For Windows users, create a new shortcut with “target”:<HDS_HOME>\bin\

hdldesigner.exe –authorpro
• For Linux users, copy the hdl_author script from your previous HDL Author tree to the
same location in the new tree.

You can find installation instructions in the HDL Designer Series Installation Instructions
manual, available on Support Center. Licensing information is also available.

https://support.mentor.com

The composite license feature hdldesigner_c contains the following atomic license features. The
composite license can be updated using the mgc.pkginfo file. The license file refers to
hdldesigner_c composite only (not the atomic licenses).

• hdldesignerpro (HDL Designer Series)

• svassist (System Verilog-VHDL Assistant)
• regassistopt (Register Assistant)
• hdlchecker (Design Checker)
Licensing is implemented using the PCLS or MGLS versions of the Macrovision FLEXlm
license manager that are normally used for Mentor Graphics Corporation (MGC) products.

12 HDL Designer Series™ Release Notes, v2019.4

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 Configuration and Compatibility
Installation and Licensing

All required files to license the HDL Designer Series products are included in the installation
and you do not need to explicitly install licensing unless you want to set up a separate license
server.

The licensing systems all support floating licenses on a remote server and node-locked licenses
indexed to a Linux workstation hostid or to a hardware security key (dongle).

The HDL Designer Series products are compatible with existing license server installations
based on FlexNet 11.16.2.1. For more information about FLEXlm including the latest version of
the License Administration Guide, check the Release Information scope in the HDL Designer
Series InfoHub. The vendor daemons and lmgrd that are shipped with this release are FlexNet
version 11.16.2.1.

For floating licenses, it is necessary to verify that the vendor daemon (that is, mgcld) and the
license server (that is, lmgrd) have FlexNet versions equal to or greater than 11.16.2.1. If the
current FlexNet version of your vendor daemon and lmgrd is less than 11.16.2.1, then it is
necessary to stop your license server and restart it using the vendor daemon and lmgrd
contained in this release.

If you use node-locked licenses, you do not need to do anything. This release updates the
licensing to MSL v2019_2 with MGLS v9.21_3.2 (v2019_2) and PCLS vv9.21_3.3 (v2019_2).

PCLS has a new version format to better track with the associated MGLS version.

In summary, this release uses the following license versions:

• FlexNet 11.16.2.1
• MSL v2019_2
• MGLS v9.21_3.2 (v2019_2)
• PCLS v9.21_3.3 (v2019_2)

License File Location

The default license file location on a Linux workstation is as follows:

<install directory>/license/license.dat

The default license file location on a Windows PC is as follows:

C:\flexlm\license.dat

You can use the MGLS_LICENSE_FILE or LM_LICENSE_FILE environment variable to

specify an alternative location for the license file. Both variables are recognized by MGC
licensing. However, the MGLS_LICENSE_FILE variable takes precedence if both variables are
set.

HDL Designer Series™ Release Notes, v2019.4 13

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Configuration and Compatibility
Installation and Licensing

Thus, LM_LICENSE_FILE can be set for applications that use standard FLEXlm licensing,
while the location specified by MGLS_LICENSE_FILE is used for Mentor Graphics
applications.

On windows, these variables are set in the registry when you install licensing. The precedence is
as follows:

MGLS_LICENSE_FILE set in the environment

MGLS_LICENSE_FILE set in the registry
LM_LICENSE_FILE set in the environment
LM_LICENSE_FILE set in the registry

These settings are search paths and can be set to multiple locations by entering multiple
pathnames or port specifications (separated by a colon on Linux or a semi-colon on Windows).
For example:

1700@mylichost:/usr/opt/license.dat

1700@mylichost;C:\license.dat;C:\hds\license.dat

You can check the variable and registry settings on Windows by choosing
Start > HDLDesigner Series <release_number> > Licensing > PCLS_OK.

Note
The PCLS_OK utility has been relocated from the HDS<release_number>\bin directory to
a separate Mentor Licensing Program directory: C:\MentorGraphics\Licensing. You can
uninstall this utility separately from the tool.

Tip
To install the PCLS separately, navigate to the setup files at HDS<release_number>\
license\pcls_setup.exe.

Using a Dongle on a Windows PC

A hardware security key (dongle) is not required if you are using an evaluation license or have
chosen to use a remote license server. A key is required when you install licensing on the local
PC (or on a PC used as a license server).

The dongle is a generic device connected to the USB and can also be used for other products
although a valid license key that matches the unique identifier is required for each product.

Tip
To install the Dongle Drivers separately, navigate to the setup files at
HDS<release_number>\license\dongle_setup.exe.

14 HDL Designer Series™ Release Notes, v2019.4

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 Configuration and Compatibility
Installation and Licensing

You can load the driver during installation, or you can check an existing driver using the
LMTOOLS utility, by choosing Start > HDLDesigner Series
<release_number> > Licensing > LMTOOLS.

Note
The LMTOOLS utility has been relocated from the HDS<release_number>\bin directory to
a separate Mentor Licensing Program directory: C:\MentorGraphics\Licensing. You can
uninstall this utility separately from the tool.

Select the System Settings tab of the LMTOOLS dialog box. If you have the correct driver
loaded, the dongle serial number should be displayed in the FLEXID field. If the displayed
number does not match the serial number on your dongle, re-install the licensing system to load
the correct driver.

License Maintenance Date

Existing licenses enable this version of HDL Designer, provided that the release date of the
software is less than or equal to the exact access date. For example, 2007.030 in the following
example:

INCREMENT hdldesignerpro mgcld 2007.030 19-mar-2007 1 ED3090278DDE24D5BF09

VENDOR_STRING=683AB64D

The version number is also commonly referred to as the license maintenance date or the exact
access date. If your license incorrectly shows an expired maintenance date, please contact your
local sales office.

You can examine the current license information using the FLEXlm license manager on
Windows or you can use the lmutil lmstat -A or lmstat -A commands in a shell on any platform
to report the licensing information in the current license file specified by the
LM_LICENSE_FILE environment variable. For example:

“hdldesignerpro” v2007.010, vendor mgcld

Licensing in a Linux MGC Environment

If you want to use an existing MGLS installation to run an HDL Designer product on Linux,
copy the contents of the mgc.pkginfo file from <install_dir>/bin into the existing file
$MGC_HOME/pkgs/mgls_rgy/lib/mgc.pkginfo and restart the server.

MGLS licensing works in the same way as other MGC tools and if MGC_HOME is set,
MGLS_HOME defaults to $MGC_HOME/pkgs/mgls/, so it need not be set explicitly. You can
access the mgc.pkginfo from $MGLS_HOME/lib/ or $MGC_HOME/lib/ (which are both links
to $MGC_HOME/pkgs/mgls_rgy/lib/).

HDL Designer Series™ Release Notes, v2019.4 15

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Configuration and Compatibility
External Tool Support

The mgc.pkginfo file is required only for use by the client tool that is using a license (in this
case, HDL Designer); it is not required by the server itself.

The following set of environment variables are recommended for using HDL Designer in an
existing MGC environment:

MGLS_HOME unset
MGC_HOME set to the existing MGC tree
MGLS_LICENSE_FILE set as for your other MGC applications
LM_LICENSE_FILE unset unless required for other FLEX applications.

Refer to the HDL Designer Series User Manual for a full list of environment variables.

Detailed information about the Mentor Graphics Licensing System (MGLS) is provided in the
Mentor Standard Licensing Manual which is available in the installed PDF library on
$MGC_HOME/shared/pdfdocs. This directory also includes a copy of the FlexNet License
Administration Guide.

External Tool Support

The HDL Designer Series tool interfaces have been tested with certain external tool versions.
Some tools may not be available on all platforms.

Downstream Tools
Table 1-2. External Tool Support: Downstream Tools
Tool Version
Cadence®
Incisive® 10.2 to 11.10
Intel®
MegaWizard™ Quartus II 13.0 to 14.0
Note: Altera® tools have been Note: Qsys is not supported in the Intel Quartus
acquired by Intel. II flow.

Quartus® Synthesis Quartus II 14.1 to 15.0

Quartus SOPC Builder Quartus II 13.0 to 14.0
Quartus Prime 17.x to 18.x
19.1 and 19.2 Pro Edition
Lattice
Lattice 8.1 to 8.2

16 HDL Designer Series™ Release Notes, v2019.4

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 Configuration and Compatibility
External Tool Support

Table 1-2. External Tool Support: Downstream Tools (cont.)

Tool Version
Mentor Graphics®
I/O Designer™ 8.0
Leonardo Spectrum™ 2017a to 2018a
ModelSim®/Questa® 10.6x to 2019.4
Note: ModelSim/Questa 10.6 is not supported.

Precision® 2018.1 to 2019.1.1

Microsemi®
Libero® IDE 9.1 to 9.2
Libero SoC 12.0 and 12.1
Libero SoC PolarFire® 2.1 to 2.3
Synopsys®
Design Compiler® 2002.05
Synplify® 2018.09 to 2019.09
VCS®/VCSi™ 2010.06 to 2011.03
Xilinx®
CORE Generator™ ISE® 13.1 to 14.7
Platform Studio ISE 13.1 to 14.7
XST Synthesis ISE 13.1 to 14.7
Vivado® 2018.2 and 2019.1

Version Management
Table 1-3. External Tool Support: Version Management
Tool Version
ClioSoft® SOS 3.03
GNU CVS (Concurrent Versions System) 1.11.1p1
GNU RCS (Revision Control System) 5.7
IBM® Rational® ClearCase® 7.0.1
Microsoft® or Mainsoft® Visual 6.0
SourceSafe™

HDL Designer Series™ Release Notes, v2019.4 17

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Configuration and Compatibility
Further Information

Table 1-3. External Tool Support: Version Management (cont.)

Tool Version
Subversion® 1.6x to 1.9.3

Further Information
For the latest information about the HDL Designer Series including other related products, press
releases, brochures, datasheets, presentations, multimedia demonstrations and software
downloads, see the website.
http://www.mentor.com/products/fpga/hdl_design/hdl_designer_series/

For information about the DesignChecker changes in this release, refer to the DesignChecker
Release Notes.

For information about the Register Assistant changes in this release, refer to the Register
Assistant Release Notes.

Support Information
If you have questions about this software release, please log in to Support Center. You may
search thousands of technical solutions, view documentation, or open a Service Request.
https://support.mentor.com/

If your site is under a current support contract but you do not have a Support Center login,
register today:

https://support.mentor.com/register

Tracking Service Requests, Defect Reports (DRs), and Enhancement

Requests (ERs)
If you are a registered Support Center user, you can always view the status of your own Service
Requests, including the detailed status of any attached Defect Report (DR) or Enhancement
Request (ER). You can also view all Service Requests for your site, including all associated
DRs and ERs.

In addition, all publicly accessible DRs and ERs are available on Support Center. If you would
like to know the status of a DR or ER that is not attached to any of your or your company’s
Service Requests, go to the Service Requests page on Support Center and use the search field to
type your product.

https://support.mentor.com/en/service-request

18 HDL Designer Series™ Release Notes, v2019.4

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 Configuration and Compatibility
User Documentation

Note
Some defects may not be made public for various technical or business reasons; this is
determined on a case-by-case basis.

Important Information Before Requesting Support

If you encounter a problem while using HDL Designer Series, choose
Help > Support > Generate Support Info before requesting support. This feature
automatically creates a text file containing information about your HDL Designer Series
environment, which helps support engineers resolve your problem faster.

If the tool exits unexpectedly, the tool issues an error message in an information dialog box.
When you close the dialog box, a transcript is automatically written to a log file. This file
contains additional information that can be useful to diagnose the problem.

If you are an existing customer, enter a Service Request on Support Center and summarize the
operations you attempted before the problem occurred. You can paste the content of the support
information file and the log file, if appropriate, into the long description.

If you are evaluating the product, send the support information file and the log file, if
appropriate, to your support contact.

You can find the log file saved in the following locations:

• Windows — C:\Users\<user>\AppData\Roaming\HDL Designer Series\hds_user\logs\

hds_log.txt
• Linux — $HOME/hdl_designer_series/hds_user/logs/hds_log.txt

User Documentation
Use the InfoHub to access all the product and release documentation for HDL Designer Series.
The InfoHub is available from the Start > HDL Designer Series <release> > Manual menu
and from Help > Help and Manuals menu in the tool. You can also use the InfoHub to search
across the documentation, or submit a search directly to Support Center to search additional
resources, such as Knowledge Base Articles.

HDL Designer Series™ Release Notes, v2019.4 19

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Configuration and Compatibility
User Documentation

Figure 1-1. InfoHub

Refer to “Browser Settings” in the Mentor Documentation System manual to verify that your
browser version is supported and that you have the required browser settings for accessing and
viewing the InfoHub, and Support Center. Click “Browser Settings” at the bottom of the
InfoHub for details.

Required PDF Plug-In for SystemVerilog-VHDL Assistant

To open PDF documents from the Help > Help and Manuals menu in SystemVerilog-VHDL
Assistant on Linux, you must download a PDF reader plug-in for the web browser.

20 HDL Designer Series™ Release Notes, v2019.4

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 Chapter 2
Known Problems and Workarounds

Refer to the list of known problems, limitations, and workarounds for the release.
List of Problems and Workarounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Broken Links in PDF Documentation (MG595892) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

List of Problems and Workarounds

Consult the list of problems, limitations, and workarounds.
• In the Allowed Types rule in DesignChecker, regarding user-entered values, if you
manually enter a type name which already exists within one of the package options in
the parameter list, the entry will be regarded as a duplicate and will not be retained when
you close the tool.
Workaround: To check specific types from within one of the listed packages, please
prefix the type with the appropriate package name. For example, to check for type
“real”, enter “std.real”. Similarly for “time”, “string” or “integer” enter “std.time”,
“std.string” or “std.integer”.
• On generating VHDL for a block diagram that has been created while having the option
“Convert to Graphics” set, component declarations may not be generated.
Workaround: In VHDL, there are basically two styles of instantiations for design units:
component instantiations and entity instantiations.
Component instantiations require that a component declaration be present prior to the
component instantiation. On the other hand, entity instantiations require that the entity
be visible at some point before the entity is instantiated, but a component declaration is
not required. HDL Designer always creates component instantiations in the VHDL
generated for a block diagram or IBD. In addition, by default, it also creates component
declarations in the generated code. HDL Designer currently does not give the option to
generate entity instantiations.
If you wish to supply your own component declarations in a package, HDL Designer
enables you to control whether or not component declarations are created. This is
affected by three factors that apply to both block diagrams and IBDs:
o The “Create component declarations” option under the Options > VHDL > Style
menu.
This option only affects the VHDL generated for new block diagrams that you draw
manually.

HDL Designer Series™ Release Notes, v2019.4 21

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Known Problems and Workarounds
List of Problems and Workarounds

o The “Create component declarations” option under the HDL menu in an existing
block diagram.
This option toggles whether or not component declarations will be generated for this
particular diagram. This setting enables you to change how the VHDL is generated
for the diagram.
o The presence of component declarations in existing source code that you convert to a
block diagram through the “Convert to Graphics” option.
If you use the “Convert to Graphics” option to convert existing structural code into a
block diagram, the presence or absence of component declarations in the source
code determines the initial setting in the block diagram that is created. Regardless of
whether you create a block diagram by drawing it manually or by using the “Convert
to Graphics” option, you can use the setting under the HDL menu in the diagram, to
control whether component declarations are created in the generated VHDL for that
diagram.
• It is not recommended to install HDL Designer Series in a long path, because this may
lead to errors. The overall number of characters in the installation path is recommended
to be a maximum of 80 characters. This applies to Windows only.
• If you are using Xilinx Vivado 2016.1 with the “Non-Project” mode and “Compile
Simulation Libraries” option selected, then it is not recommended to compile an HDS
project through the FPGA Technology Setup dialog box with “Xilinx-Vivado” set, as
this raises an error.
Workaround: Invoke the Xilinx Vivado plug-in from the Tasks browser directly, instead
of invoking it through the FPGA Technology Setup task.
You may encounter the following problems can be when using SystemVerilog-VHDL
Assistant:

• The “Import from Questa” feature in SystemVerilog-VHDL Assistant can be used to

import a design which has been previously compiled and simulated using Questa. This
mechanism also imports the same Questa settings that were used in the compilation and
simulation of the design including the default library search path.
Questa 10.3 contains a new “infact” library in the default library path within the
modelsim.ini file. SystemVerilog-VHDL Assistant, therefore, automatically adds the
“infact” library to the “Linked Libraries” setting in the Edit Build Library dialog box,
which causes the simulation to fail on Windows if there is no C compiler configured
with the following message:
Can’t locate a C/C++ compiler for ‘DPI Export Compilation’.

Workaround: Workarounds for this issue are as follows:

o If the “infact” library is not required, remove the “infact” entry from the Linked
Libraries field in the Edit Build Library dialog box.

22 HDL Designer Series™ Release Notes, v2019.4

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 Known Problems and Workarounds
List of Problems and Workarounds

o If the “infact” library is required, make sure you have a C compiler correctly
configured for use with Questa.
• HDL Designer installation paths should not contain special characters like ( ) \ / : * < > |
to ensure successful operation of the SV Assistant build manager.
• On Windows, a Verilog include using a relative path can be very slow to resolve.
Workaround: When using Verilog includes on Windows, type the full path.
• On Windows, Verilog files with include statements which start with “/” (for example, /
inc_dir/my_include.svh) may take a significant time to analyze.
• In order to extract or visualize UVM/OVM objects, the UVM/OVM library source must
be added to your project.
• Visualizations can only be cross-referenced during the session in which they are created.
Saved visualizations are purely pictures and have no link to original code.
• Some UVM/OVM code components may not appear in the visualized testbench view
when their parent classes are not referenced in a package that imports UVM/OVM.
Workaround: Add the problematic classes to a package that imports UVM/OVM.
• If you try to add a path to any location preference on Windows using the Linux format
(for example \net\egcfs4\vol), SystemVerilog-VHDL Assistant resolves this path
(understands it as a relative path) and adds the installation drive before it.
• The SystemVerilog-VHDL Assistant “Search” operation will search within files located
under the project’s directory even if they are not part of the SystemVerilog-VHDL
Assistant project. Consequently, the “Open Resource” dialog box (Alt-Shift-R) displays
files that are not part of the SystemVerilog-VHDL Assistant project, just because they
are under the project’s directory.
• When compiling/simulating test benches, SystemVerilog-VHDL Assistant
automatically detects whether the Questa used is 32-bit or 64-bit. Sometimes,
SystemVerilog-VHDL Assistant does not detect that the Questa used is 64-bit.
Workaround:
• Set the environment variable ‘x86_64’ to any positive value.
• Simulating UVM designs generally requires using the uvm_dpi shared library; when
running Questa vsim, it automatically passes the right dpi options to Questa. In some
rare cases, SystemVerilog-VHDL Assistant does not correctly identify the uvm_dpi
library location.
Workaround: You can edit the command template of Questa vsim from the Project
Settings to append to it the missing options “-sv_root <Questa_uvm_dpi_library
directory> -sv_lib uvm_dpi”.

HDL Designer Series™ Release Notes, v2019.4 23

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Known Problems and Workarounds
Broken Links in PDF Documentation (MG595892)

• When you using the precompiled version of OVM 2.1.2 that is shipped with Questa,
dynamic visualization of your simulated design might not work if your test bench has
OVM components that are not registered with a factory.
Workaround: Adding the factory registration solves the issue. Alternatively, you can
choose to compile the OVM source from within SystemVerilog-VHDL Assistant.
However, in this case, you are prompted to perform some extra steps to successfully
visualize your simulated design. Detailed steps are displayed in the Console tab when
you issue the dynamic visualization command. You may also refer to the “Dynamically
Visualizing UVM/OVM Testbenches” topic under the “Understanding UVM/OVM
Designs” section in the SystemVerilog-VHDL Assistant Reference Manual you can by
choosing Help > SystemVerilog-VHDL Assistant > SystemVerilog-VHDL Assistant
Reference Manual..

Broken Links in PDF Documentation

(MG595892)
Due to enhanced security restrictions with web browser PDF plug-ins, some links do not
function. Links in HTML documentation are fully functional.
Clicking a link within a PDF viewed in a web browser may result in no action, or it may load the
title page of the current PDF manual (instead of the intended target in the PDF manual). The
unresolved link behavior occurs in all web browsers on Windows and Linux platforms. Because
of this behavior, the navigational experience of PDF manuals is compromised. PDF is ideal for
printing because of its page-oriented layout.

Use the HTML manuals to search for topics, navigate between topics, and click links to
examples, videos, reference material, and other related technical content.

For information about Adobe’s discontinued support of Adobe Reader on Linux platforms and
your available options, refer to Knowledge Article MG596568 on Support Center.

24 HDL Designer Series™ Release Notes, v2019.4

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 Chapter 3
Corrected Problems

This chapter lists the fixed defect reports in software versions v2019.4 and earlier of the HDL
Designer Series tools.
For information about new features, refer to What’s New in the HDL Designer Series.

Note
Fixed defects prefixed with HDS-, DC-, SVVA-, or RA- are issues reported using Atlassian
JIRA®.

Software Version 2019.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Software Version 2019.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Software Version 2019.4

Refer to the list of issues and enhancements that have been addressed in the v2019.4 release.

HDL Designer
• HDS-12274 — Request to support side data constraint files, such as .xdc and .sdc files,
in the Xilinx Vivado flow.
• HDS-21105 — Request to provide a script that checks the libraries required to use HDS
on Linux.
• HDS-21128 — Request to fix an error raised on selecting Intel® Stratix® 10 devices.
• HDS-21143 — Request to update the device list for Quartus Prime Pro Edition version
18.0.
• HDS-21144 — Request to fix the generation of the launch_simulation.tcl script for
Quartus Prime Pro Edition version 18.0.
• HDS-21177 — Request to fix an incorrect behavior in the Xilinx Vivado flow that
occurs when the “Point to Files” option is selected. HDS incorrectly adds the simulation
wrapper files from the IP on updating the Vivado project.
• HDS-21187 — Request to enhance the Xilinx Vivado flow to enable setting up the
simulation library path in a team environment.
• HDS-21188 — Request to enhance the Xilinx Vivado flow to copy the entire IP
directory instead of copying only the .xci files.

HDL Designer Series™ Release Notes, v2019.4 25

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Corrected Problems
Software Version 2019.4

• HDS-21194 — Request to support a simplified Xilinx Vivado flow.

• HDS-21204 — Request to restore the ability to instantiate components using drag and
drop.
• HDS-21219 — Request to fix the operation of renaming instanced design units in the
Block Diagram.
• HDS-21220 — Request to fix errors raised on copying some design units in the Library
Browser.

DesignChecker
• DC-2215 — Request to fix the Register Reset Control base rule to raise violations for
variables instead of signals.
• DC-2220 — Request to modify a violation raised by the Unused Declarations base rule.
The violation is required to specify the instance names when there are multiple instances
of the same design unit.
• DC-2232 — Request to fix a syntax error raised on generating missing declarations.
• DC-2233 — Request to eliminate a syntax error that stops DesignChecker analysis.

SystemVerilog-VHDL Assistant
• SVVA-1283 — Request to preserve the text file encoding option.
• SVVA-3362 — Request to add an option in project preferences for editor encoding.
• SVVA-3535 — Request to stop opening the Clear Lock dialog box while running
SystemVerilog-VHDL Assistant in batch mode.
• SVVA-3631 — Request to support finding Verilog and SystemVerilog references.
• SVVA-3687 — Request to enhance the performance of opening VHDL files in the text
editor.
• SVVA-3765 — Request to support high-level Block Diagram visualization.
• SVVA-3847 — Request to support the “Unhide All” feature in RTL visualization.
• SVVA-3862 — Request to enhance the performance of the Makefile generation.
• SVVA-3894 — Request to support the API command importFileListIntoLibraries.
• SVVA-3906 — Request to fix the extraction of files included in the project using
relative paths.
• SVVA-3914 — Request to parse all .svh files correctly to avoid reloading the unparsed
files.

26 HDL Designer Series™ Release Notes, v2019.4

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 Corrected Problems
Software Version 2019.4

• SVVA-3928 — Request to enhance the performance of opening a Questa Verification

IP (QVIP) project.
• SVVA-3937 — Request to keep hidden objects after updating the block diagram
visualization.
• SVVA-3939 — Request to modify the Visualization view to show names and IDs in a
transparent frame.
• SVVA-3950 — Request to support multiple simulation configurations.
• SVVA-3951 — Request to support finding Verilog and SystemVerilog references.
• SVVA-3952 — Request to provide an API command that reports SVA project build
macro defines.
• SVVA-3955 — Request to fix an exception raised on modifying only the Port Clause
VHDL formatting options.
• SVVA-3956 — Request to support SystemVerilog scalability mode.
• SVVA-3958 — Request to disable the hide feature for nets in visualization views when
multiple objects are selected.
• SVVA-3974 — Request to display Verilog ports of unknown direction in RTL
visualization.
• SVVA-3976 — Request to remove extra nodes in the Outline browser in the Tree View
mode.
• SVVA-3979 — Request to fix the name of the folder grouping visualization instances.
• SVVA-3981 — Request to fix an exception raised on instantiating a specific
architecture.
• SVVA-3986 — Request to open the Help menu manuals in an external HTML viewer.
• SVVA-3995 — Request to update the label of the Linked Libraries field in the New
Build Library dialog Box.
• SVVA-4100 — Request to support tracing nets down in Block Diagram visualization.
• SVVA-4106 — Request to support automatic cross-referencing between RTL
visualization and the text editor.

Register Assistant
• RA-457 — Request to fix an exception raised on importing registers from an IP-XACT
1.4 file.

HDL Designer Series™ Release Notes, v2019.4 27

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Corrected Problems
Software Version 2019.3

Software Version 2019.3

Refer to the list of issues and enhancements that have been addressed in the 2019.3 release.

HDL Designer
• HDS-5189 — Request to provide a 64-bit application for HDL Designer.
• HDS-18445 — Request to fix an issue in which a port in a generated component
declaration has a missing range.
• HDS-21125 — Request to support Libero SoC 12.0.
• HDS-21137 — Request to fix an issue in running Libero interface with a specific
package.
• HDS-21139 — Request to make .vm the default Verilog file type for Libero SoC
PolarFire.
• HDS-21140 — Request to fix an issue in which a design imported using Libero SoC
PolarFire 2.3 has missing files.
• HDS-21142 — Request to add the top-level flag to top-level design units imported
using Libero.
• HDS-21147 — Request to support binary format values in Block Diagram API
commands.
• HDS-21165 — Request to enhance the performance of Block Diagram API commands
with large designs.
• HDS-21170 — Request to include “derived” .sdc files in the Libero IP import operation.
• HDS-21175 — Request to fix a false syntax error raised for a valid Vivado 2019.1 IP
file.

DesignChecker
• DC-2203 — Request to fix the “importDesignFromQuestaIniFile” API command to
support backslash characters (\) in Windows paths.
• DC-2204 — Request to fix an issue in which a sub-program body incorrectly identifies
a function call as recursive.
• DC-2205 — Request to fix a hang in DesignChecker batch flow.
• DC-2206 — Request to fix a false violation for enum comparison raised by the
Matching Range base rule.
• DC-2209 — Request to enhance the display of some syntax error.
• DC-2222 — Request to add a “reject” value to the Allowed Constructs base rule.

28 HDL Designer Series™ Release Notes, v2019.4

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 Corrected Problems
Software Version 2019.3

SystemVerilog-VHDL Assistant
• SVVA-3656 — Request to support RTL Block Diagram visualization.
• SVVA-3685 — Request to load .bld files only on demand instead of loading them while
invoking the tool or on creating a new project.
• SVVA-3737 — Request to support automated bundling for downstream tools.
• SVVA-3766 — Request to support autowrapping on specific user-defined tokens.
• SVVA-3790 — Request to fix an issue in which the project is saved twice if you close it
from the popup menu.
• SVVA-3815 — Request to fix an issue in which an extra VHDL Architecture is
produced on parsing if the Architecture contains a subtype.
• SVVA-3817 — Request to enhance the documentation of External Tools.
• SVVA-3822 — Request to add the ability to remove multiple selections of external
libraries when using the build management feature.
• SVVA-3830 — Request to enable VHDL browsers to create nodes for VHDL Generate
statement branches.
• SVVA-3836 — Request to remove Vivado and Checks sub-menus from the popup
menu when selecting files from various projects.
• SVVA-3889 — Request to fix an issue in which the tool does not detect top units
consistently when there are redefined modules.
• SVVA-3892 — Request to fix an issue in which the Questa import operation imports
libraries as external libraries despite setting “Don’t Import”.
• SVVA-3897 — Request to add Mark as Top to the popup menu of program statements.
• SVVA-3898 — Request to improve the performance of Questa import operation.
• SVVA-3925 — Request to fix the auto-complete feature to show the correct options
within the function’s scope.

HDL Designer Series™ Release Notes, v2019.4 29

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Corrected Problems
Software Version 2019.3

30 HDL Designer Series™ Release Notes, v2019.4

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 End-User License Agreement
with EDA Software Supplemental Terms
Use of software (including any updates) and/or hardware is subject to the End-User License Agreement together with the
Mentor Graphics EDA Software Supplement Terms. You can view and print a copy of this agreement at:

mentor.com/eula