1. The number of pins 8085 microprocessor has 40 pins.

2. HLT in 8085 microprocessor is used for End of program.

Using this particular instruction, 8085 enters into the halt state

3. Which of the followings is/are 16 bit register in a 8085 microprocessor?

Stack Pointer

Detailed Answer: 8085 microprocessor has 6 8bit general purpose registered B,C,D,E,H,L which
are combined as register pairs BC,DE,HL to perform 16 bit operations, and has two 16 bit
memory registers which are stack pointer and program counter.

4. The program counter in a 8085 microprocessor is a 16-bit register, because

There are 16 address lines.

Which, helps it to access 2^16 i.e. 65536 memory locations.

5. Bootstrap program is used for

loading first instruction

 When a computer system is started, the bootstrap program is the first code to be executed. The
bootstrapping process involves self-tests, loading BIOS, configuration settings, hypervisor,
operating system etc. in a chain.

6. What is the most significant use of stack in 8085 microprocessors?

Subroutine call

Stack is most commonly used to execute subroutine calls and to handle interrupt. During a
subroutine call the current program information (return address) is stored in the stack and then
the subroutine call information is executed. After a subroutine call completes execution, the
saved return address is popped from the stack to continue execution of the previous
programme from where it was stopped.

7 Which type of hardware organization does zero address instructions use?

Stack

Zero address instructions uses stack for execution. consider the following example to evaluate
S=(A+B)*(C+D), the zero address instructions are as follows whose postfix expression is
S=AB+CD+*

8 A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). What number of 2 × 4 decoders
with enable line needed to construct a 64K × 16 RAM from 1K × 8 RAM is required?

RAM chip size = 1k ×8[1024 words of 8 bits each]

RAM to construct =64k ×16

Number of chips required = (64k x 16)/ ( 1k x 8) = (64 x 2)

[64 chips vertically with each having 2 chips horizontally]

So to select one chip out of 64 vertical chips,

we need 6 x 64 decoder.

Available decoder is 2 x 4 decoder

To be constructed is 6 x 64 decoder

Hence 1+4+16= 21 decoders are required.

9. In 8085 microprocessor, data-bus and address bus are multiplexed in order to

a. Reduce the number of pins.

b. Reduce hardware cost

 c. execution of instructions is sequential

d. All of the above

Ans. d. All of the above.

The main reason of multiplexing address and data bus is to reduce the number of pins for
address and data and dedicate those pins for other several functions of microprocessor. These
multiplexed set of lines used to carry the lower order 8 bit address as well as data bus. Thus
reducing the hardware cost too and as the execution of instructions is sequential. That is, no
two instructions can be executed at the same instance or clock pulse. This means data loading
and address loading always occurs at different clock pulses. It simplifies the hardware because
now the bus can be time shared for address loading and data loading

10. The correct sequence of steps in the instruction cycle of a basic computer is

Fetch, Decode Read effective address and Execute

When an instruction is executed, at first the opcode of the given instruction is fetched. Next the
instruction is decoded. Then the effective addresses of the operands are calculated. In the last
stage the instruction is executed.

11. The field is not present in an assembly language statement is

Continue

continue statement is not present in assembly level language.

12. The efficiency of fetching data neither increases nor decreases using LRU principle in direct
mapping as in direct mapping LRU principle is not applicable. Increasing the number of blocks
does not necessarily increase the efficiency of fetching data but will decrease it and can be
commonly observed while using FCFS principle. This is known as Belady’s anomaly.

13. How many flags are implemented by status register in 8085 microprocessor

The Status register can have a total of eight flags.

Thus a flag can be represented by 1 bit of information. But only five flags are implemented in
8085. And they are:

● Carry flag (Cy),

● Auxiliary carry flag (AC),

● Sign flag (S),

 ● Parity flag (P), and

● Zero flag (Z).

14. How many flip flops are required for implementing mod n counter.

ceil(log2(n))

Number of bits required to represent a n digit number must be greater than equal to log2(n)
thus we take the least whole number greater than log2(n)

15. Which is responsible for all the outside world communication by the microprocessor

BIU (BUS INTERFACE UNIT)

The Bus Interface unit handles all transfer of data and addresses on the buses for the EU
(execution unit). This unit sends out addresses, fetches instructions from memory, reads data
from ports and memory and writes data to ports and memory
 WEEK 1

1. Apart from Embedded systems being programmable an Embedded system can also be
hardwired.
2. Take for example an car (larger system) can have multiple embedded systems present in it
for example - Antilock Braking System (ABS), Engine Control Unit (ECU), Traction Control
System etc.

3. An Embedded System differs from General Purpose system in which of the following
factor(s)

I. Lower Power Consumption

II. Lower Cost
III. Portable

An Embedded system is used for single purpose whereas a General-Purpose System is used
for General purpose. Embedded system is tightly constrained in terms of low cost, low
power consumption, portable and sometimes it must be Realtime.

4. Boiler of a Thermal Power Plant is equipped with embedded systems which control and
maintain the temperature and pressure inside the boiler. The Embedded systems must be
Hard Realtime systems

Overshooting deadline to complete a task of controlling temperature and pressure can lead
to major catastrophe, that’s why stringent time constraints are present and embedded
systems in the above case must be Hard Realtime embedded system

5. The design activity where operations are mapped to hardware or software is

Hardware-Software Co-Design

The hardware/software Co-Design is the activity which is in charge of mapping operations to

the software or to the hardware

6. If a component is implemented in software, then

It will be Slower

Designing any component in software leads to the system to be slower as the system has to
process it separately by allocating separate CPU time but on the other hand it leads to the
system to be more flexible as it would able to perform more functions on the programmer’s
side.
7. If a component is implemented in hardware, then. It will be faster

Designing a specific component in hardware helps in making that component fast but leads
to more time consumed in designing the hardware parts and hence the increase in cost
related to it, and makes the system less flexible too on programmer’s side.

8. Placement and Routing task comes under which design step

Geometrical Design

Placement and Routing task is a part of Geometrical design step as we need to place and
route the structure of circuit obtained in structural design step.

9. There is no distinction in between data memory and program memory in Von-Neumann

Architecture but in Harvard architecture they are separate.

10. A Counter is set to zero and at every clock pulse it counts up and at any point of time we can
find out the time elapsed.

11. A timer is set with a preset time and at clock it counts down and gives a pulse when it
becomes zero

12. Digital Signal Processor (DSP)’s application(s) is(are)

a. Discrete Fourier Transforms

b. Fast Fourier Transform

c. Parallel addition of arrays

d. All of the Above

13. Intellectual Properties IPs can be customized for example we can take an IP core and we can
customize its control Path or data path or add a couple of hardware or even we can add
couple of new instructions.
14. The minimum number of bits required for representing each of the 53 sates of a Finite State
Machine is 6

2 n >= 53, where n is the number of bits and 2 n gives the total number of combination
possible using n bits, on solving the above we get n>=6, therefore he smallest value of n is 6.
 WEEK-2

1. The possible ways to optimize a single-purpose processor is:

One can optimize single purpose processor by optimizing the original program, optimizing the
FSMD by eliminating or merging the states. But parallel execution of similar operations is not
possible because it will need more hardware support which is not optimal.

2. Optimization of data path can be done with:

Reducing one to one mapping and effectively using the hardware.

One to one mapping is not necessary. If similar operations take place in different stages, they
can share same functional unit.

3. States can only be merged if they are equivalent states. Equivalent states are:

For all possible input combinations states generate the same output and transitions to the same
next state.

States can only be merged if, for all possible input combinations states generate the same
output and transitions to the same next state. These states are called equivalent states.

4. The embedded systems using general purpose processors are more versatile.
Single purpose processors are designed considering a single type of tasks.

5. Field programmable gate arrays (FPGA) consists of:

FPGAs consists of an array of Configurable logic blocks (CLB).

6. State which is true among the statements about antifuse connection.

Antifuse connections are permanent and hence can not be further used and once it is done, it
cannot be redone.
7. Combinational logic can be implemented by

Combinational logic can be implemented either byusing a multiplexer or a decoder and a look-
up table.

8. In SRAM a pass transistor is used. It can be programmed and when the value is 1 it conducts and
creates the connection and when value is 0 the connection is off.

9. The D flipflop is used in configurable logic block because

To use the previous state result from look-up table

 In configurable logic block a d flipflop is used so that the value of look-up table can be
used in next state so that a delay can be induced.

V 10. 3 part of a port of VHDL is

Name, mode, datatype

Justification: 3 part of port in VHDL are name (identifier is used), mode (input, output or
buffer), datatype (declared or predefined type).

11. A unit that has been modelled using VHDL is known as

Design entity
A unit modelled in VHDL is known as design entity.

13. Which of the following is VHDL standard for one dimensional bit type array?
BIT_VECTOR is used for one dimensional bit type array in VHDL.

Even if a program of the processor is fully optimized, the FSMD can be optimized by merging
the stages or eliminating the unnecessary stages. This will effectively lower the number of flip
flops used.

A multiplexer alone can implement any Boolean function. No encoder is needed.

A FPGA board can be divided into multiple slices and each slice can perform different function
parallelly. But a sequential general purpose processor can not parallelly do as many tasks as
an FPGA.

To introduce a delay in the circuit the D flipflop is used. To take the result from the D flipflop,
the input of the MUX should be 1.

When a variable is declared in VHDL it may or may not be initialized

.
 Week 3 Embedded system design

1. Behavioral Description of a system include(s)

Ans - Operations, Functions, Processes

Behavioral description of a system includes Operations, Function, Processes etc that are
required to convert input to output.
2. A system designed in VHDL consists of modules

A system designed in verilog consists of module where as a system designed in VHDL is

composed of entities each of which can have multiple architecture and a configuration
chooses what architecture is used for a given instance of an entity.
5. Given 2 statements

Functional Design is also Known as Front-End Design whereas Physical Design is also known as
Back-End Design

4. We cannot design a memory element using a data flow model because in dataflow model
outputs are defined in terms of input signal transformation i.e. only combinational elements can be
deigned.
5. assign statements are concurrent in nature and thus are executed when there is an change in a
variable on the right hand side of statement.

6. Parameters are runtime constants, are declared within a module, their scope lies within a
module, can be overwritten during component instantiation and are used to make code scalable.
7. Which type of device FPGA are?

PLD

Field-Programmable Gate Arrays (FPGAs) are reprogrammable silicon chips. In contrast to

processors that you find in your PC, programming an FPGA rewires the chip itself to implement
your functionality rather than run a software application. Thus, FPGAs are PLD devices.
 Week 4 Embedded system design

1. The number of distinct levels in which a 16bit sensor produces information upon sensing an
input is

Ans – d. 65536

Explanation – The total number of levels in which a 16bit sensor can produce data is 2 16=65536

2. A Capacitor can hold Information.

Explanation – A capacitor can hold charge, thus the charge stored can be treated as information.
For example, Capacitor with charge stored in it can be treated as 1 and an empty capacitor can be
treated as 0.

3. To reduce quantization noise (difference in original signal value and sampled signal value) we
should (considering the detectable range for the sensor remains same)

Ans – b. Select a sensor which gives more no of bits as output

Explanation – A sensor with more number of bits as output means it can distinguish between more
number of discrete level withing the same range, thus resolution increases and the difference between
original signal value and samples signal value decreases and hence quantization noise decreases

4 As per Nyquist criterion the minimum rate at which a finite bandwidth signal needs to be
sampled to retain all information and avoid aliasing during faithful reconstruction is when
the sampling frequency is greater than twice the maximum frequency of the incoming
signal.

5. An Antialiasing filter is effectively an

Ans – a. Low Pass filer

Explanation – An Antialiasing filter is a low pass filter so that any frequency above half of sampling
rate are effectively cutoff thus eliminating Asialing which occurs during reconstruction.

7. Speed of Flash ADC(Analog to Digital Converter) is

Ans – a. O(1)

Explanation – whenever a Flash ADC samples input, it does it in parallel and takes constant
time irrespective of input value, therefore O(1),

8. Hardware Complexity of Flash ADC(Analog to Digital Converter) is

Ans – b. O(n)
Explanation – Since output of a Flash ADC depends on number of bits, therefore its hardware
complexity is O(n).

9. A successive Approximation ADC

Ans – b. Is slower than Flash ADC, c. Has more resolution than Flash ADC

Explanation –According to the construction a Successive approximation ADC is slower but has
more resolution than Flash ADC.

10. Speed of Successive Approximation ADC (Analog to Digital Converter) is

Ans – c. O(logn)

Explanation – As we are effectively implementing binary search in order to sample input signal,
therefore the speed of a Successive Approximation ADC is O(logn).
11. Signal to Noise ratio of an ideal 10bit ADC is

Ans – d. 61.96 dB

Explanation – The signal to noise ratio can be calculated using the formulae n*6.02+1.76 dB,
where n is the number of bits of converter.

Therefore, for a 10-bit converter we have 10*6.02+1.76dB=61.96dB

12. What will be the appropriate duty cycle to produce a 2V average output from 10V input?

Ans – d. 20%
Explanation – To get the output voltage we have the formulae as
Output voltage = duty cycle * Input Voltage
Therefore 20% * 10V = 0.2*10V=2V
 1. In a pulse width modulated system avg. voltage is changed by

Ans. Changing the duty cycle

Justification: In pulse width modulated system the analog signals are represented into
digital signal by varying the time duration of high and low (0, 1) voltage. Changing the duty
cycle the avg. voltage of the system is changed.

2. The receiver gets informed about the serial incoming message from the
transmitter by:

Ans. A start bit denoted by 1 bit of 0 and end bit is denoted by 2 bits of 0.
Justification: Data is transmitted from sender to receiver through a TTL line which is in
high level in default state. The start bit is denoted by 1 bit of 0 and stop bit is 2 bit of 0.

3. The value of the key pressed is parsed in Arduino by which command

Ans. Serial.parseInt

Justification: Serial.parseInt command is used to perse the value when a key press event
occurs.

4. The components of interrupt function (attachInterrupt) in Arduino are

Ans. Interrupt pin, interrupt function and interrupt mode

Justification: The interrupt function contains three components which are Interrupt pin,
interrupt function and interrupt mode. Example: attachInterrupt (0, deEncode, FALLING).
Here 0 is the pin number, deEncode is the function and FALLING is the mode of interrupt
that means interrupt will work on falling edge.

V 5. The keyword used in Arduino to execute a periodic function is:

Ans. every

Justification: The keyword used to execute a periodic function in Arduino is every

Example: int every (long period, p)

6. In oscillating pulse function (int oscillate ()) the advantage of using

‘repeatCount’ parameter
 Ans. It will determine how many times the oscillation will repeat else the oscillation will
continue forever

Justification: The ‘repeatCount’ parameter gives the count of oscillation as input so it does
not continue oscillating forever.

8. The function that is used to get the analog signal in Arduino is:

Ans. analogRead

Justification: The function ‘analogead’ reads the value from the specified analog pin. Arduino
boards contain a multichannel, 10-bit analog to digital converter. This means that it will map
input voltages between 0 and the operating voltage (5V or 3.3V) into integer values between
0 and 1023.

9. In proportional control, the target value can never be achieved due to an error called:

Ans. steady-state error

Justification: In proportional control, the error is known as steady-state error. The

magnitude of the error depends on the system gain and will be never zero.

10. Arduino ATmega328 uses the following hardware architecture:

Ans. RISC architecture

Justification: Arduino ATmega328 uses 8-bit RISC architecture

11. An Arduino ATmega328 has:

Ans. 14 digital I/O pins of which 6 provide PWM output

Justification: An Arduino ATmega328 has 14 digital I/O pins of which 6 provide PWM
output.

12. Basic Arduino program components are

Ans. Setup and loop

Justification: Void setup() is used to initialize the variables, pin modes, baud rate

Void loop() is the part of the code that loops back to itself and is main part of the code.

2. The printed circuit expansion boards used by Arduino is called:

 Ans. Shield

Justification: The printed expansion board that is placed on top the Arduino board for
executing different function is called shield.

13. The power consumption in a CMOS circuit decreases when:

Ans. The switching activity decreases

The power consumption in a system depends upon switching activity, square of voltage,
frequency and load capacitance. When switching activity decreases the power
consumption decreases.

14. The delay of the CMOS circuit increases when:

Ans. The voltage decreases

Justification: The delay depends upon capacitive load and inverse of the voltage. So when
the voltage decreases the delay of CMOS circuit increases.

15. With increase in supply voltage the power consumption increases quadratically.

More power consumption will take place if we try to finish the job as early as possible
because in that case the voltage needed will be more which will increase the power
consumption.

16. In a power aware system:

The components are provided with only required value of frequency to finish the task in time
and all components work with different frequency according to their requirement.

Justification: As the frequency is directly proportional to the voltage of the system, so the
frequency is set to be only the required frequency to finish a work within deadline and not
more than that. All the components in the processor works with different frequency
according to their requirement.

17. In a power aware system, the energy per cycle depends upon

Ans. The clock frequency

 Week 6 Embedded system design

1. Processor using a single supply voltage V completes a task T just at its deadline , then V is the
unique supply voltage that maximizes power consumption of T

According to lemma given by Ishihara and Yasuura. Processor using a single supply voltage V completes
a task T just at its deadline , then V is the unique supply voltage that minimizes power consumption of T.

2. Considering tighter time constraints, Energy Consumption

Ans – Increases

Explanation – If the time constraint is tight more energy is consumed because we need to push more
cycles at higher voltage which leads to increased energy consumption

3. Power consumption depend(s) on

Explanation – Power consumption depends on Supply Voltage, Lower Capacitance and Switching (of
bits)

4. Decision in voltage scheduling in Static Voltage Scheduling is carried out

Ans – At Compile time

Explanation – The Voltage scheduling in Static Scheduling algorithm is taken at compile time, where
deadline of each task is known and linear Programming problem is formulated and thus voltage levels
are scheduled.

5. Accessing registers uses less power than accessing primary memory

Explanation - Accessing registers consumes less power than accessing primary memory, that’s why
various measures are taken to reduce access to primary memory.

6. In VLIW (Very Long Instruction Word) four independent instructions are clubbed together to
form an Instruction word, the task of finding out Independent Instruction is carried out by

Ans- c. Compiler

Explanation- the four independent instructions clubbed together in VLIW (Very Long Instruction Word) is

performed by the compiler.

7. In EPIC (Explicitly Parallel Instruction Code) Architecture which bit position is used to encode the
end of parallel execution?

Ans – LSB (Least Significant Bit)

Explanation – as In EPIC (Explicitly Parallel Instruction Code) Architecture LSB (Least Significant Bit) bit
position is used to encode the end of parallel execution.

8. How many bit instructions are used in thumb mode of operation in ARM

Ans – 16

Explanation – In Thumb Mode operation processor works with 16bit instructions whereas in normally in
expanded mode ARM can work with 32-bit instructions.

9. Dictionary approach to attain code efficiency is based on the use of some kind of dictionary that
contains parts of input sequence that frequently appears.

Explanation – Dictionary approach or two-level control store approach helps in attaining code efficiency
which is based on the use of dictionary that contains parts of input sequence that frequently appears.

10. The factors achieved in VLIW (Very Long Instruction Word) is/are

Ans – Reduces the number of accesses to memory, b. Increases Parallelism, c. Pushing some overhead to
compiler

Explanation - VLIW reduces the total number of accesses to memory for fetching instructions, increases
parallelism and pushes overhead to compiler for clubbing together four independent instructions.
 Week 7

1. In saturation arithmetic if the result is restricted to unsigned 8 bits in binary, then which of the
following is correct

Ans – 17*17=255

Explanation- 17*17 gives 289 which is 0001 0010 0001 in binary and since it is 8 bit saturation
arithmetic and the output is greater than 8 bits therefore the maximum value represented by 8 bits
in binary i.e. 1111 1111 which is 255 in decimal, which is the output

2. DSP (Digital Signal processor) has/have

a. Specific hardware for performing multiplication and addition operations in same cycle

b. Saturation Arithmetic

c. Zero Loop Overheard (hardware /Software)

d. All of the above

Ans – d. All of the Above

Explanation – DSP follows Saturation arithmetic and has special memory architectures that
can fetch multiple data or instruction at the same time to reduce the overall execution time
and has special hardware for performing multiplication and addition operation in same cycle
and has zero loop overhead, thus all these together helps to make DSPs more efficient.

3. Reuse of components helps in reducing time to market and can only be done in Hardware.

Explanation - Reuse of components helps in reducing time to market and can only be both done in

Hardware as well as Software.

4 Which of the following data structure falls under the category of Static Data Structure

Ans – Arrays

Explanation: Array is classified under static data structure whereas linked list, trees and graphs
falls under dynamic data structure.

5. In Standard operating system Application layer can access device drivers.

Explanation – In Standard operating system Application Layer has to access device drivers via
Operating system whereas in RTOS (Real Time Operating System) supports direct access of device
drivers from application layer.

6. RTOS requires files to be contiguous because

Ans –it makes system predictable

Explanation – RTOS requires files to be contiguous. If a file is not contiguous it may lead
to varying access times due to unpredictable head movements.

7. Total number of semaphore variable required for an unit resource to be accessed in a

mutually exclusive fashion by N number of processes

Ans – 1

Explanation - Only one Binary Semaphore is sufficient to guarantee mutually exclusive access to a
unit resource.

Every process need to follow the following sequence to access

resource R Let the semaphore be named S

1. P(S)

2. Resource

3. V(S)

Where P() and V() are atomic in nature.

8. When several processes access and manipulate same data concurrently and the
outcome doesn’t depend on the particular order in which access has taken place is
known as race condition.

Explanation –Race condition is when multiple processes access and manipulates data concurrently
and the output depends on the particular order in which access has taken place.

9. A cyclic dependency of resources among processes will always lead to deadlock.

Explanation – A cyclic dependency of resources may not always lead to deadlock as there
may me multiple resources of the same type.

10. Rate Monotonic Scheduling uses which of the following approach(es)

Ans – preemptive

Explanation – rate monotonic scheduling algorithm schedules periodic tasks using static
priority along with preemption i.e. it gives higher priority to tasks with smaller time period.

11. Given tasks in the form Tn(x,y), where n stands for nth task, x stands for time period, y
standing for execution time

T1(10,3)

T2(17,5)

T3(20,2)

Can the above tasks be scheduled so that none of the misses deadline?

Ans – Yes

Explanation:

Considering the stability check equation

Where n=number of tasks, c=execution time, p=period
i i

We have,

= 0.694117647
= 0.77976313

As the above inequality holds, therefore the tasks can be scheduled.

1. The property of dynamic scheduling that makes it different from static scheduling is
Ans. It reschedules every time when a new process enters the queue.

Justification: Dynamic scheduling reschedules the task every time a new task enters
the queue and, in this process, it may pre-empt a task.

2. Suppose 3 repetitive tasks be (4,1), (6,3), (9,3) (Consider period and deadline is same
for these tasks) following earliest deadline first. All of them start at timestamp 0. When
the timestamp 4 ends the following will take place

Ans. Task 1 will start executing

Justification: At time stamp 0 task 1 will start executing and will carry on for 1 unit. At
time stamp 2 task 2 will start executing and will continue for 3 unit. Now after end of
timestamp 4, task 1 reappears and its deadline is 4. The new deadline of task 3 is 5. So,
task 1 will be assigned to be executed as its deadline is the earliest.

3. Schedulability check condition in earliest deadline first rule is

Ans. Both sufficient and necessary condition to check whether tasks can be scheduled)
Justification: Schedulability check in earliest deadline first scheduling is both necessary
and sufficient condition.

4 Suppose 3 task be (3,1), (5,3), (7,3). Can they be scheduled using earliest deadline
first rule? (Period and deadline are same for these tasks)

Ans. no

Justification: According to schedulability check ((1/3) + (3/5) + (3/7)) > 1. The condition is
sufficient and necessary for tasks to be schedulable. As the condition fails, these tasks
can not be scheduled.

5. Suppose two task T1 and T2 where the priority of T1 is greater than T2, have critical section
for same resource starts executing at different time. T2 starts executing first and enters
critical section and then the T1 enters the queue. The following will take place:

Ans. T1 will start executing and when critical section of T2 comes, T2 will stop and T1
will start executing till its critical section ends.

Justification: When T1 enters the queue the critical section of T2 will stop and T1 will
execute till its critical section arrives. Then T1 will be halted and T2 will be executed till
its critical section is completed executing and next T1 will be executed.

6. Justification: For three or more than processes having critical section for same
resources, the blocking time of a process may even exceed the time required to
compute critical section.
 In case of RMS the condition for schedulability was sufficient but not necessary, i.e. if
the test fails, it does not make sure that no scheduling is possible.

7. The disadvantage of priority inversion protocol is:

Ans. When there are more than two process, the higher priority process which needs to
access the critical section may starve.

Justification: In priority inversion protocol the priority changes when some higher priority
process asks for shared resource that is being accessed by lower priority process. So, one
process may take long time due to access of critical section by other lower priority
process which will hamper the real time system.

8. The disadvantages of priority inversion protocol can efficiently be overcome by

Ans. Priority inheritance protocol

Justification: Priority inheritance protocol is used to overcome the disadvantages

of priority inversion protocol.

9. Justification: Disallowing pre-emption may cause starvation of higher priority process

without critical section. As in that case when a lower priority process enters into
critical section, higher priority process without even need of the critical section waits
for lower priority process to finish its critical section.

In priority inversion protocol the priority changes when some higher priority process
asks for shared resource that is being accessed by lower priority process. Only after
critical section finished being executed, the higher priority process starts executing.

10. Suppose 3 tasks are following priority inheritance protocol and Pr(T1)> Pr(T2) > Pr(T3).
Now T3 starts executing and enters critical section. Then T2 enters and pre-empts T1
and next T1 enters and pre-empts T2. Now when the T1 will require critical section
following will take place:

Ans. T3 will inherit the priority of T1 and it will execute its critical section and then T1
will start execution

Justification: In this case priority inheritance protocol will be followed and T3 will
inherit the priority of T1 as priority inheritance is transitive property. After T3
completes execution of critical section, T1 will start executing the critical section.

11. The disadvantage of priority inheritance protocol is

Ans. When working with multiple critical section dead-lock may occur

Justification: The disadvantage of priority inheritance protocol is that when working with
multiple critical section, deadlock may take place if it happens that one process that is
 currently working on a critical section ‘A’ requires access of another critical section ‘B’
that is being locked by another task T2.

12. In priority ceiling protocol, the priority ceiling of each semaphore defines:

Ans. Highest priority of all tasks that may lock it.

Justification: For each semaphore a priority ceiling is defined whose value is the highest
priority of all task that may lock it. The ceiling value is the priority value of highest
priority task that uses the resource.
13. Suppose, there are two task T1 and T2 where Pr(T2) > Pr(T1). There are two shared
resources protected by two semaphore S1 and S2 which will be used by both task T1
and T2. Following priority ceiling protocol T1 starts executing and starts executing S1.
Next T2 enters the queue and pre-empts T1 and then it tries to access S2. The following
will take place:

Ans. T2 will be pre-empted and T1 will start executing S1.

Justification: The priority ceiling value of both the semaphore is priority of T2. Now when T2
asks to access S2 but its priority is same as S1 and so not higher than the ceiling of all other
semaphores those are locked. So T2 will pre-empted and T1 will start executing S1.

14. The requirements of modelling system are:

a. Supports for design of large systems.

b. Specific termination condition

c. Adequate model of computations

d. All of the above

And. all of the above

Justification: The modelling system requires all of the above requirements.

15. In a hierarchical model:

a. Behavioural hierarchy describes states, processes and procedures

b. Structural hierarchy describes the processors and printed circuit boards

c. The concurrency between two components can be shown explicitly.

d. All of the above

Ans. all of the above

Justification: In a hierarchical model behavioural hierarchy describes states, processes and

procedures, structural hierarchy describes the processors and printed circuit boards. The
explicit concurrency between two components can be shown using hierarchical model.

16. To model continuous behaviour the model used is:

Ans. Differential model

Justification: Differential equation is used to model continuous behaviour.

17. In asynchronous message passing:

Ans. The sender does not wait for receiver to receive the message.
Justification: In asynchronous transmission the sender does not wait for receiver to
receive the message. In this case if the speed of sender and receiver are different, then
buffer overflow takes place.
18. The disadvantage of synchronous message passing is:

Ans. The speed of transmission may decrease if the speed of sender and receiver is not
the same

Justification: In synchronous message passing the sender waits until the receiver
receives the message. So, if the speed of sender is greater than the speed of receiver,
the sender needs to wait and sits idle.
 WEEK-9

1. The output value of mealy state machine depends upon

Ans. The input value and the current state

Justification: The output value in mealy state machine depends upon the current state and
the input value.

2. The disadvantages of finite state machine are:

Ans. Lack of hierarchy and concurrency

Justification: The finite state machines are suitable for displaying temporal behavior explicitly
and for control dominated systems. But when it tries to represent complex systems, lack of
hierarchy and concurrency becomes the disadvantage of finite state machine as number of
states and arcs increases greatly.

3. In a super state, whenever super state is entered the default state to enter is called:

Ans. Default state

Justification: In a super state, unless specified otherwise, the default state to enter is
called default state or entry state.

4 Justification: A history node keeps track of the last active substate from which superstate was
exited so that when entering into the superstate the system can enter into the state from which it
exited.
A history node can be combined with the default entry node.

5. In an AND-Super state:

Ans. All the substates run concurrently.

Justification: In an AND-Super state all the substates works concurrently and executes
different functions.
6. Timer in in a state chart representation does the following:

Justification: When a timer state is entered, upon receiving input the control goes to
respective states and if no input value is received within certain time, it enters to a
predefined state.

7. Justification: An event exist only until the model is revaluated.

A condition consists of variable which can be reassigned and until reassignment occurs
the variables keep their value.

8. The phases of evaluation of edge models are:

Ans. Evaluation of effect of external change on event and condition, computation of

transitions and changing of values of variables

Justification: The three phases of evaluation of an edge of the model is:

1. Effect of external changes on events and condition is evaluated.

2. The set of transitions to be made in current state and right-hand sides of

assignment are computed

3. The transition becomes effective and variables obtain new values.

10. In state chart the mode of communication used is:

Ans. Broadcast

Justification: In state chart broadcast mode of communication is used. It means if from a

state an action generates an event, that event is visible to all other states.
 11. In the following figure when event e occurs in state A the following will take place:
Ans. A conflict scenario will be generated

Justification: When the event shows in the picture occurs, a conflict scenario arises and
a deterministic overcome is not possible in this case

11. A state chart:

Ans. All of the above

Justification: A state chart enables hierarchy which allows arbitrary nesting of states.
State chart has backend also which can convert a state diagram to a software or
hardware language. Also, the semantics in a state chart are well defined.

12. The disadvantage of state chart is:

Ans. The programming constructs are not present.

Justification: The disadvantage of state chart is that there is no programming construct

present in it. But in some cases, programming constructs becomes really helpful to represent
a system than a state chart

13. The processes for data dependent synchronization are

Ans. Shared memory and message passing

Justification: The processes used for data dependent synchronization are shared memory
and message passing.
14. The advantage of program state machine over state chart is:

Ans. Procedures could be included

Justification: In program state machine procedures or programs can be included which was
one of the disadvantages of state chart. The codes can be added at leaf level of hierarchy.

15. Types of transition possible in a program state machine are

Ans. Transition on completion and transition immediate

Justification: Two types of transitions possible in a program state machine are transition on
completion which takes place only after a state is completed and transition immediate
which takes pace immediately.

16. Justification: Functional timing is reflected during the simulation of the system as through
functional timing the delay between the steps or states are declared.

In Spec Chart the code can be embedded at the leaf level of hierarchy. It is a form of
program state machine.

17. The types of timing constraints are:

a. Execution time constraint

b. Data rate time constraint

c. Inter event timing constraint

d. All of the above

Ans. All of the above

Justification: The types of timing constraints are execution time constraint, data rate time
constraint, inter event time constraint. Execution time constraint ensures to complete a task
with specified time. Data rate time constraint ensures two the transmission delay between
two devices. The inter event timing constraint ensures the interval between two events.
18. Behavioural hierarchy is partially present in VHDL and behavioural completion feature is
fully supported in VHDL.

19. Behavioural completion and exception handling both features are present in SpecChart

20. In state chart exception handling is present.

 WEEK-10

1. In SDL the mode of communication used is:

Ans. Asynchronous message passing

Justification: In state chart Asynchronous message passing is use for communication.

2. The advantage of SDL over state chart is:

Ans. State chart is not suitable for distributed systems

Justification: As SDL follows asynchronous message passing for communication, it is

more suitable for distributed systems than state charts

3. The root block in hierarchy of SDL is called:

Ans. System
Justification: The root block in hierarchy of SDL is called system.

4 The construct that is used in SDL to fetch current time is:

Ans. Now
Justification: The construct used in SDL to fetch current time is now.
Example: set (now +p, T) will set a timer t that is the current time + p unit

5. A data flow model consists of:

Ans. Process, data store, external entities and data flow

Justification: A data flow model consist of process, data store, external entities and data
flow. Process corresponds to activities that transform data. Data flows are routes
though which data flows, data stores hold or stores the data.

6. The tasks in KAHN processing networks communicate between themselves using:

Ans. FIFO

Justification: In KAHN processing network, the tasks communicate between themselves

using FIFO where it is assumed that there will be no overflow. There is one sender and
one receiver per FIFO.

7. In KPN the channels transmit message in:

Ans. Unpredictable but finite amount of time

 Justification: In KAHN processing network the transmit messages for unpredictable
but finite amount of time. So the execution time becomes unknown.

8. The disadvantage of KPN is

a. The number of processes is static

b. It is difficult to analyze

c. All of the above

d. None of the above

Ans. All of the above

Justification: The disadvantages of KPN is that the number of processes is static so

whenever new tasks arrives it cannot be handles by KPN. Also, it’s also difficult to analyze
because of buffering and accumulation of tokens

9. In synchronous data flow the mode of message passing is:

Ans. Asynchronous message passing

Justification: In synchronous data flow, the mode of message passing is asynchronous

message passing. In this case the tasks do not have wait for the output to be accepted.

10. In synchronous data flow the global clock is used for:

Ans. The nodes are fired at the clock tick

Justification: In SDF (synchronous data flow) the global clock is used and at the tick of
the clock the nodes are fired

11. The actors in SDF are ready when:

 Ans. When the required number of input tokens are available and there is enough
buffer space

Justification: The nodes or actors in SDF are ready in SDF if and only if the required
number of input tokens are available and enough buffer space is available at output.

12. The difference between homogeneous and non-homogeneous SDF is:

Ans. In homogeneous SDF same numbers of token is generated per firing.

Justification: In homogeneous SDF numbers of token generated in each firing is
same which is not the case in non-homogeneous SDF.

13. In a petri net the transitions take place when:

Ans. When the input tokens are available

Justification: The petri nets are asynchronous and in this case the transmission takes p

14. Through profiling we estimate:

Ans. The number steps, operator and register needed to carry out the task)
Justification: Using profiling we estimate the number of steps, registers and
operators needed to complete a task

15. Datapath synthesis can be achieved by:

a. Variable merging

b. Operation merging

c. Chaining and multi cycling

d. All of the above

Ans. All of the above

Justification: Datapath synthesis can be achieved by variable merging, operation

merging, bus sharing, register merging, chaining and multi cycling and by data and
control pipelining.

16. The possibility of merging of registers is checked by:

Ans. Compatibility graph

Justification: The possibility of merging the registers is checked by compatibility graph

which checks whether they are non-overlapping in time during execution and does not
use same resource.
17. Two registers can be merged together when:

Justifications: Two registers can be merged together if they are non-overlapping in time
during execution and does not use same resource.

18. Justification: The analyzability of SDF is better than KPN but its expression power is more
restricted than KPN.
 Week 11

1. Since all registers are not being used in same state, therefore connectivity costs can be
reduced by combining the registers together.

2. We cannot merge two connections if they are active at the same time because a connection
cannot carry 2 separate data value at the same time.

3. In Resource Constrained Scheduling we have resources specified to us and we need to minimize

metrics like time, power etc.

4. Windowing is a technique used to concentrate the processing in a desired part of image

and also ignoring the non-desired part or non-interested part of the image. In this, an electronic mask is

created around a small area of an image.

5. In Huffman Coding, we traverse the tree from root to leaf to obtain binary code of leaf’s
value, we append 0 for left traversal and 1 for right traversal.

6. 011

recording the path of the node from root to leaf, the code word for character ‘a’ is found to

be 011.

8. CCD is an example of dynamic memory because contents of it changes with time.

9. Zero Bias Adjustment falls under pre-processing, it is done due to the reason that no
manufacturing process is perfect so a pixel in CCD sensor being black may give a non zero value
reading, thus to take corrective measure for the image captured Zero Bias Adjustment is
performed.

10. Log2(N)
we need to satisfy the equation 2x>=N where value of x is smallest. As each bit in binary has 2
values thus x bits can produce 2x discrete combination.
10. What is the codeword for ‘c’
Ans – c110

Explanation - recording the path of the node from root to leaf, the code word for character ‘a’ is found to

be 110.