Low Power - High Speed Magnitude Comparator

Circuit Using 12 CNFETs

Jitendra Kumar Saini1,*, Avireni Srinivasulu2,†, SM-IEEE Renu Kumawat3,‡, SM-IEEE

1, 3
Dept. of Electronics & Communication Engineering 2
Dept. of Electronics & Communication Engineering
Manipal University Jaipur JECRC University
Jaipur-303007, Rajasthan, INDIA Jaipur-303905, Rajasthan, INDIA
*
[email protected], †[email protected] ‡
[email protected]

Abstract—In VLSI domain there is an unending demand for low layered or multi-layered, the single layered structure is referred
power, high speed and smaller chip area based circuits. Under to as single-walled and multi-layered structure is referred to as
these constraints, 1-bit magnitude comparator circuit (1B-MCC) multi-walled CNT. This ability to form single-walled or multi-
is proposed using 12 Carbon Nanotube Field Effect Transistor walled structure enables CNT to possess characteristics of
(CNFET). However, the proposed analysis processes have been metals and semiconductors both [3-4].
conducted in terms of power, delay and power-delay product The single-walled or multi-walled CNT when roll-up to
(PDP). In order to arrive at a fair comparison between earlier form a cylindrical or concentric cylindrical structure, it further
designs and the proposed design, 2-bit magnitude comparator enhances the properties of CNT sheets. The connections
circuits (2B-MCC) are favored as they are designed in 45 nm
between these sheets binding them together are measured by
CMOS technology at supply voltage (VDD) of 0.7 V. Later on the
proposed design was extended to CNFET technology at 32 nm
Chirality Vector (C) shown in Figure 1 and is represented as
with VDD of 0.7 V to gain the benefits of CNFET technology. C = na1 + ma2 (1)

Keywords; CNFET; magnitude comparator; high speed;

I. INTRODUCTION
Ubiquitous demand to shrink the IC form-factor (high-
density) and to scale it as per demand (integrity) is the
challenge every company needs to deal with on daily basis.
Other essential considerations are low power consumption and
higher operational speeds. CMOS came in with a promise to
deal with these issues but with recent technological
advancements we see a new player in the market i.e. CNFET
[1-2].
Figure 1. Representation of Chiral vector [3]
The aim of this paper is to demonstrate the improvement in
circuit performance of 2-bit magnitude comparator by reducing The type of CNT will depend on the n and m factor, i.e. If n
the number of transistors and length of the critical path. 1-bit = m, then type of CNT will be Armchair. If m = 0, then type of
magnitude comparator circuit designed using 12 CNFETs CNT will be Zigzag. If m < n or m > n, then type of CNT will
(denoted as 1B-MCC) has been proposed in this paper, which be Chiral. Here a1, a2 are unit vectors in equation (1) [5-6].
is further extended to 2-bit magnitude comparator circuit (2B-
MCC). We have also tried to enhance the overall circuit The characteristics like mobility, drive current and current
performance, when compared with existing 2B-MCC designs. voltage of CNFET are same as of MOSFET. The CNFET is a 4
terminal device with heavily doped CNT acting as the drain /
The remaining part of the paper is organized as follows: source while lightly doped CNT acts as the gate. Considering
Introduction of CNFET in Section 2. Section 3, discusses the the performance as a vector, the CNFET is segregated into
structural implementations of 1B-MCC, while simulation Schottky Barrier or MOSFET. The threshold can be measured
results of 1B-MCC and comparisons of 2B-MCC with earlier by dividing the band-gap of CNFET by a factor of 2e,
designs are summarized in Section 4. Section 5 covers the represented as:
conclusion drawn. Vth = Ebg/2e = 0.436/DCNT (nm) (2)
II. CARBON NANO TUBE FIELD EFFECT TRANSISTOR Here Vth is the threshold Voltage, Ebg is the energy band-
Carbon Nano Tubes (CNT) are structurally nano scale ( gap of CNFET, e is the electron charge and DCNT is the
10-9) uniaxial honeycomb lattice with benefits of graphite i.e. diameter of the rolled-up CNT [7].
carbon. They can have structural variations characterized as DCNT = d = 0.0783 m 2 + n 2 + mn
Armchair, Zigzag and Chiral. Further they can either be single (3)

978-1-5386-7960-9/18/$31.00 ©2018 IEEE 145 ISOCC 2018

 III. PROPOSED 1-BIT MAGNITUDE COMPARATOR CIRCUIT delay product is significantly lower for the proposed 2B-MCC
The proposed 1B-MCC consists of 2 inputs (A and B) and as compared to other 2B-MCC designs.
three outputs (A < B, A = B, A > B) as shown in Figure 2. The
proposed circuit uses only 12 transistors for the implementation TABLE I. COMPARATIVE ANALYSIS OF CANDIDATE DESIGNS
of 1B-MCC. The relation between inputs and outputs of 1B- 2 Bit MC, VDD=0.7V, Transistors Power Delay PDP
MCC is given in the form of equations (4), (5), (6) respectively Technology (nm) Count (µW) (ns) (fJ)
Conventional CMOS [5]
(A < B) = AB 54 0.62 8.4 5.208
(4) CMOS 45 nm
TGL Based [6]
( A = B) = A + B 74 0.47 8.49 3.990
(5) CMOS 45 nm
P. TGL Based [7]
( A > B ) = AB CMOS 45 nm
30 0.28 7.63 2.136
(6)
X-E Logic Based [7]
25 0.33 7.96 2.626
C1 C9 CMOS 45 nm
C5 Proposed with CMOS
24 0.09 4.73 0.425
A<B CMOS 45 nm
A C2 C10 Proposed with CNFET
24 0.02 2.08 0.041
CNFET 32
A=B
C6 C12 V. CONCLUSION
We have proposed low power, high speed magnitude
B C3 C11
C7 comparator circuit using 12 CNTFETs. The performance of
A>B the proposed 2-bit magnitude comparator and earlier 2-bit
C4 magnitude comparator circuits are compared based on
C8 transistor count, power, delay and power-delay product.
Among all these design structures, the proposed magnitude
Figure 2. Proposed 1-Bit magnitude comparator circuit comparator has yielded the best performance and hence it can
be used to design N-Bit magnitude comparator. It can thus be
IV. SIMULATION RESULTS concluded that by using proposed magnitude comparator for
The proposed 1B-MCC are simulated on 32 nm CNFET implementing high performance complex structures, such as,
technology using Cadence Virtuoso CAD Tool at supply multipliers, arithmetic logic unit, and mobile communication
voltage of +0.7 V, threshold Vth = 0.289 V with Chirality vector devices, etc. the intrinsic benefits of proposed magnitude
(19, 0). Figure 3 depict the simulation waveforms of 1B-MCC comparator could be fully exploited.
for all the test cases. Simulation results shows that the proposed
design provides full output swing. REFERENCES
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978-1-5386-7960-9/18/$31.00 ©2018 IEEE 146 ISOCC 2018