ISO1540

ISO1541
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Low-Power Bidirectional I2C Isolators

Check for Samples: ISO1540, ISO1541

1FEATURES SAFETY AND REGULATORY

2• 2
Isolated Bidirectional, I C Compatible, APPROVALS
Communications • 4000-VPK Isolation per DIN EN 60747-5-2
• Supports up to 1 MHz Operation (VDE 0884 Part 2) (Approved)
• 3-V to 5.5-V Supply Range • 2500-VRMS Isolation for 1 minute per UL 1577
• Open Drain Outputs with 3.5-mA Side 1 and (Approved)
35-mA Side 2 Sink Current Capability • CSA Component Acceptance Notice 5A
• -40°C to 125°C Operating Temperature (Approved)
• ±50 kV/µs Transient Immunity (Typical) • IEC 60950-1 and IEC 61010-1 End Equipment
Standards (Approved)
• HBM ESD Protection of 4 kV on All Pins;
8 kV on Bus Pins ISO1540 ISO1541

VCC1 1 8 VCC2 VCC1 1 8 VCC2

APPLICATIONS

Isolation

Isolation
SDA1 2 7 SDA2 SDA1 2 7 SDA2
• Isolated I2C Bus
SCL1 3 6 SCL2 SCL1 3 6 SCL2
• SMBus and PMBus Interfaces
• Open-drain Networks GND1 4 5 GND2 GND1 4 5 GND2
Side 1 Side 2 Side 1 Side 2

• Motor Control Systems

• Battery Management
• I2C Level Shifting

DESCRIPTION
The ISO1540 and ISO1541 are low-power, bidirectional isolators that are compatible with I2C interfaces. These
devices have their logic input and output buffers separated by TI’s Capacitive Isolation technology using a silicon
dioxide (SiO2) barrier. When used in conjunction with isolated power supplies, these devices block high voltages,
isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging
sensitive circuitry.
This isolation technology provides for function, performance, size, and power consumption advantages when
compared to opto-couplers. The ISO1540 and ISO1541 enable a complete isolated I2C interface to be
implemented within a small form factor.
The ISO1540 has two isolated bidirectional channels for clock and data lines while the ISO1541 has a
bidirectional data and a unidirectional clock channel. The ISO1541 is useful in applications that have a single
Master while the ISO1540 is ideally fit for multi-master applications.
Isolated bidirectional communications is accomplished within these devices by offsetting the Side 1 Low-Level
Output Voltage to a value greater than the Side 1 High-Level Input Voltage thus preventing an internal logic latch
that otherwise would occur with standard digital isolators.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 I2C is a trademark of NXP B.V Corporation.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PIN FUNCTIONS
ISO1540 and
I/O DESCRIPTION
ISO1541
NAME PIN ISO1540 ISO1541 ISO1540 ISO1541
VCC1 1 - - Supply Voltage, Side 1 Supply Voltage, Side 1
SDA1 2 I/O I/O Serial Data, Side 1 Input/Output Serial Data, Side 1 Input/Output
SCL1 3 I/O I Serial Clock Input/Output, Side 1 Serial Clock Input, Side 1
GND1 4 - - Ground, Side 1 Ground, Side 1
GND2 5 - - Ground, Side 2 Ground, Side 2
SCL2 6 I/O O Serial Clock Input/Output, Side 2 Serial Clock Output, Side 2
SDA2 7 I/O I/O Serial Data Input/Output, Side 2 Serial Data Input/Output, Side 2
VCC2 8 - - Supply Voltage, Side 2 Supply Voltage, Side 2

AVAILABLE OPTIONS
PRODUCT RATED ISOLATION PACKAGE CHANNEL DIRECTION MARKED AS ORDERING NUMBER
Both SDA and SCL ISO1540D (rail)
ISO1540 IS1540
are Bidirectional ISO1540DR (reel)
4000-VPK and
D-8
2500-VRMS (1) ISO1541D (rail)
SDA is Bidirectional
ISO1541 IS1541
SCL is Unidirectional ISO1541DR (reel)

(1) See the Regulatory Information table for detailed Isolation specifications.

Table 1. FUNCTION TABLE (1)

POWER STATE INPUT OUTPUT
VCC1 or VCC2 < 2.1 V X Z
VCC1 and VCC2 > 2.8 V L L
VCC1 and VCC2 > 2.8 V H Z
VCC1 and VCC2 > 2.8 V Z (2) ?

(1) H = High Level; L = Low Level; Z = High Impedance or Float; X = Irrelevant; ? = Indeterminate
(2) Invalid input condition as an I2C system requires that a pull-up resistor to VCC is connected.

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(1) (2)
ABSOLUTE MAXIMUM RATINGS
VALUES UNIT
MIN MAX
VCC1, VCC2 –0.5 6 V
Supply voltage SDA1, SCL1 –0.5 VCC1 + 0.5 V
SDA2, SCL2 –0.5 VCC2 + 0.5 V
SDA1, SCL1 ±20 mA
Output current
SDA2, SCL2 ±100 mA
Bus Pins ±8 kV
Human Body Model ESDA, JEDEC JS-001-2012
All Pins ±4
Electrostatic
Discharge Field-Induced-Charged
JEDEC JESD22-C101E ±1.5 kV
Device Model All Pins
Machine Model JEDEC JESD22-A115-A ±200 V
TJ(MAX) Maximum junction temperature 150 °C
TSTG Storage temperature range –65 150 °C

(1) Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under RECOMMENDED
OPERATING CONDITIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device
reliability.
(2) All voltage values here within are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.

THERMAL INFORMATION
ISO1540
THERMAL METRIC (1) ISO1541 UNITS
D (8 PINS)
θJA Junction-to-ambient thermal resistance 114.6
θJCtop Junction-to-case (top) thermal resistance 69.6
θJB Junction-to-board thermal resistance 55.3
°C/W
ψJT Junction-to-top characterization parameter 27.2
ψJB Junction-to-board characterization parameter 54.7
θJCbot Junction-to-case (bottom) thermal resistance n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
VCC1, VCC2 Supply Voltage 3 5.5
VSDA1, VSCL1 Input/Output Signal Voltages, Side 1 0 VCC1
VSDA2, VSCL2 Input/Output Signal Voltages, Side 2 0 VCC2
VIL1 Low-Level Input Voltage, Side 1 0 0.5 V
VIH1 High-Level Input Voltage, Side 1 0.7 x VCC1 VCC1
VIL2 Low-Level Input Voltage, Side 2 0 0.3 x VCC2
VIH2 High-Level Input Voltage, Side 2 0.7 x VCC2 VCC2
IOL1 Output Current, Side 1 0.5 3.5
mA
IOL2 Output Current, Side 2 0.5 35
Cb1 Maximum Capacitive Load, Side 1 40
pF
Cb2 Maximum Capacitive Load, Side 2 400
(1)
fMAX Maximum Operating Frequency 1 MHz
TA Ambient Temperature –40 125 °C
TJ Junction Temperature –40 136 °C
TSD Thermal Shutdown 139 171 °C

(1) This represents the maximum frequency with the maximum bus load (Cb) and the maximum current sink (IO). If the system has less bus
capacitance, then higher frequencies can be achieved.

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ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (3V ≤ VCC1, VCC2 ≤ 3.6V)
ISO1540 2.4 3.6
ICC1 Supply Current, Side 1 VSDA1,
ISO1541 VSCL1 = GND1; 2.1 3.3
VSDA2,
ISO1540 and
ICC2 Supply Current, Side 2 VSCL2 = GND2 See Figure 1; 1.7 2.7
ISO1541
R1,R2 = Open, mA
ISO1540 C1,C2 = Open 2.5 3.8
ICC1 Supply Current, Side 1 VSDA1,
ISO1541 VSCL1 = VCC1; 2.3 3.6
VSDA2,
ISO1540 and
ICC2 Supply Current, Side 2 VSCL2 = VCC2 1.9 3.1
ISO1541
SUPPLY CURRENT (4.5 V ≤ VCC1, VCC2 ≤ 5.5 V)
ISO1540 3.1 4.7
ICC1 Supply Current, Side 1 VSDA1,
ISO1541 VSCL1 = GND1; 2.8 4.4
VSDA2,
ISO1540 and
ICC2 Supply Current, Side 2 VSCL2 = GND2 See Figure 1; 2.3 3.7
ISO1541
R1,R2 = Open, mA
ISO1540 C1,C2 = Open 3.1 4.7
ICC1 Supply Current, Side 1 VSDA1,
ISO1541 VSCL1 = VCC1; 2.9 4.5
VSDA2,
ISO1540 and
ICC2 Supply Current, Side 2 VSCL2 = VCC2 2.5 4
ISO1541
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SIDE 1 (Only)
Voltage Input Threshold “Low”,
VILT1 500 550 660
Side 1 (SDA1, SCL1)
Voltage Input Threshold “High”,
VIHT1 540 610 700
Side 1 (SDA1, SCL1)
Voltage Input Hysteresis,
VHYST1 40 60
Side 1 VIHT1- VILT1 mV
(1) Low-Level Output Voltage,
VOL1 650 800
Side 1 (SDA1,SCL1)
0.5 mA ≤ (ISDA1 and
Low-Level Output Voltage to High-Level Input Voltage ISCL1) ≤ 3.5 mA
ΔVOIT1 (1) (2) Threshold Difference, 50
Side 1 (SDA1, SCL1)
SIDE 2 (Only)
Voltage Input Threshold “Low”, 0.3 x 0.4 x
VILT2
Side 2 (SDA2, SCL2) VCC2 VCC2
Voltage Input Threshold “High”, 0.4 x 0.5 x
VIHT2
Side 2 (SDA2, SCL2) VCC2 VCC2
mV
Voltage Input Hysteresis, 0.05 x
VHYST2
Side 2 VIHT2 - VILT2 VCC2
Low-Level Output Voltage, 0.5 mA ≤ (ISDA2 and
VOL2 400
Side 2 (SDA2, SCL2) ISCL2) ≤ 35 mA
BOTH SIDES
Input Leakage Currents VSDA1, VSCL1 = VCC1;
|II| 0.01 10 µA
(SDA1, SCL1, SDA2, SCL2) VSDA2, VSCL2 = VCC2
Input Capacitance to Local Ground VI = 0.4 x sin(2E6πt) +
CI 7 pF
(SDA1, SCL1, SDA2, SCL2) 2.5 V
CMTI Common-Mode Transient Immunity See Figure 3 25 50 kV/µs
VCC Undervoltage Lockout Threshold
VCCUV (3) 2.1 2.5 2.8 V
(Side 1 and Side 2)

(1) This parameter does not apply to the ISO1541 SCL1 line as it is uni-directional.
(2) ∆VOIT1 = VOL1 – VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage
Threshold to prevent a permanent latch condition that would otherwise exist with bi-directional communication.
(3) Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages above the maximum will prevent
device lockout.

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SWITCHING CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3 V ≤ VCC1, VCC2 ≤ 3.6 V
See Figure 1 0.7 x VCC1 to 0.3 x VCC1 8 17 29
Output Signal Fall Time
tf1 R1 = 953 Ω, ns
(SDA1, SCL1) 0.9 x VCC1 to 900 mV 16 29 48
C1 = 40 pF
See Figure 1 0.7 x VCC2 to 0.3 x VCC2 14 23 47
Output Signal Fall Time
tf2 R2 = 95.3 Ω, ns
(SDA2, SCL2) 0.9 x VCC2 to 400 mV 35 50 100
C2 = 400 pF
Low-to-High Propagation
tpLH1-2 0.55 V to 0.7 x VCC2 33 65 ns
Delay, Side 1 to Side 2
High-to-Low Propagation
tPHL1-2 0.7 V to 0.4 V 90 181 ns
Delay, Side 1 to Side 2
Pulse Width Distortion See Figure 1
PWD1-2 55 123 ns
|tpHL1-2 – tpLH1-2| R1 = 953 Ω,
Low-to-High Propagation R2 = 95.3 Ω,
tPLH2-1 (1) C1, C2 = 10 pF 0.4 x VCC2 to 0.7 x VCC1 47 68 ns
Delay, Side 2 to Side 1
High-to-Low Propagation
tPHL2-1 (1) 0.4 x VCC2 to 0.9 V 67 109 ns
Delay, Side 2 to Side 1
Pulse Width Distortion
PWD2-1 (1) 20 49 ns
|tpHL2-1 – tpLH2-1|
See Figure 2;
Round-trip propagation
tLOOP1 (1) R1 = 953 Ω, C1 = 40 pF 0.4 V to 0.3 x VCC1 100 165 ns
delay on Side 1
R2 = 95.3 Ω, C2 = 400 pF
4.5V ≤ VCC1, VCC2 ≤ 5.5V
See Figure 1 0.7 x VCC1 to 0.3 x VCC1 6 11 20
Output Signal Fall Time
tf1 R1 = 1430 Ω, ns
(SDA1, SCL1) 0.9 x VCC1 to 900 mV 13 21 39
C1 = 40 pF
See Figure 1 0.7 x VCC2 to 0.3 x VCC2 10 18 35
Output Signal Fall Time
tf2 R2 = 143 Ω, ns
(SDA2, SCL2) 0.9 x VCC2 to 400 mV 28 41 76
C2 = 400 pF
Low-to-High Propagation
tpLH1-2 0.55 V to 0.7 x VCC2 31 62 ns
Delay, Side 1 to Side 2
High-to-Low Propagation
tPHL1-2 0.7 V to 0.4 V 70 139 ns
Delay, Side 1 to Side 2
Pulse Width Distortion See Figure 1
PWD1-2 38 80 ns
|tpHL1-2 – tpLH1-2| R1 = 1430 Ω,
Low-to-High Propagation R2 = 143 Ω,
tPLH2-1 (1) C1, 2 = 10 pF 0.4 x VCC2 to 0.7 x VCC1 55 80 ns
Delay, Side 2 to Side 1
High-to-Low Propagation
tPHL2-1 (1) 0.4 x VCC2 to 0.9 V 47 85 ns
Delay, Side 2 to Side 1
Pulse Width Distortion
PWD2-1 (1) 8 21 ns
|tpHL2-1 – tpLH2-1|
See Figure 2;
Round-trip propagation
tLOOP1 (1) R1 = 1430 Ω, C1 = 40 pF 0.4 V to 0.3 x VCC1 110 180 ns
delay on Side 1
R2 = 143 Ω, C2 = 400 pF

(1) This parameter does not apply to the ISO1541 SCL1 line as it is uni-directional.

TIMING CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSP Input Noise Filter 5 12 ns
See Figure 4
tUVLO Time to recover from Undervoltage Lock-out 30 50 110 µs
2.7 V to 0.9 V

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PARAMETER MEASUREMENT INFORMATION

VCC1 - - VCC2
+ +

R1 R1 R2 R2

SDA1 SDA2
ISO1540/1
SCL1 SCL2

C1 C1 C2 C2

Figure 1. Test Diagram

VCC1 VCC2

VCC1
R1 R2
GND1
Isolation

+
SDA1 or tLOOP 1
SCL1 C1 C2 SDA1 0.3VCC1
Output SCL1 [ISO1540 Only]
- 0.4V

GND1 GND2

Figure 2. tLoop1 Setup and Timing Diagram

VCCx VCCy

2 kW 2 kW

Input
Isolation

Output

-
GNDx GNDy

VCMTI

Figure 3. Common-Mode Transient Immunity Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

VCCx VCCy
Side x, Side y Vccx, Vccy Ry
1, 2 3.3V, 3.3V 95.3Ω
VCCx
Ry 2, 1 3.3V, 3.3V 953Ω
0V
SDAx or
SCLx

Isolation
+

Output

-
GNDx GNDy

or
VCCx VCCy

Ry VCCy

SDAx or 0V
SCLx
Isolation

Output

-
GNDx GNDy

VCCx or
2.7V VCCy

tUVLO

0.9V
Output

Figure 4. tUVLO Test Circuit and Timing Diagrams

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DEVICE INFORMATION

Table 2. IEC INSULATION AND SAFETY-RELATED SPECIFICATION FOR D-8 PACKAGE

Over recommended operating conditions, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Shortest terminal-to-terminal distance
L(I01) Minimum air gap (Clearance) 4.8 mm
through air
Minimum external tracking Shortest terminal-to-terminal distance
L(I02) 4.3 mm
(Creepage) across the package surface
Tracking resistance (comparative
CTI DIN IEC 60112 / VDE 0303 Part 1 >400 V
tracking index)
Minimum internal gap (internal
Distance through the insulation 0.014 mm
clearance)
Isolation resistance, input to VIO = 500 V, TA < 100°C >1012 Ω
RIO
output (1) VIO = 500 V, 100°C ≤ TA >1011 Ω
Barrier capacitance, input to
CIO VIO = 0.4 x sin(2E6πt) 1 pF
output (1)
CI Input capacitance (2) See Electrical Characteristics pF

(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.

spacer

NOTE
Creepage and clearance requirements should be applied according to the specific
application isolation standards. Care should be taken to maintain these distances on a
board design to ensure that the mounting pads for the isolator do not reduce this distance.
Creepage and clearance on the printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on the printed circuit board are used to
help increase these specifications.

Table 3. IEC 60747-5-2 INSULATION CHARACTERISTICS (1)

Over recommended operating conditions, unless otherwise noted
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
Maximum working insulation
VIORM 566
voltage
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 sec, 906
Partial Discharge < 5 pC
Method b1, After environmental tests subgroup 1,
Input-to-Output test voltage per IEC
VPR VPR = VIORM x 1.875, t = 1 sec (100% production), 1062
60747-5-2 VPEAK
Partial Discharge < 5 pC
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 sec, 680
Partial Discharge < 5 pC
VTEST = VOITM
Transient overvoltage per IEC
VIOTM t = 60 sec (qualification) 4000
60747-5-2
t = 1 sec (100% production)
RS Insulation resistance VIO = 500 V at TS >109 Ω
Pollution degree 2

(1) Climatic Classification 40/125/21

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Table 4. IEC 60664-1 RATINGS TABLE

PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Rated mains voltage ≤ 150 VRMS I–IV
Installation classification Rated mains voltage ≤ 300 VRMS I–III
Rated mains voltage ≤ 400 VRMS I–II

Table 5. REGULATORY INFORMATION

VDE CSA UL
Certified according to DIN EN 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under UL 1577
(VDE 0884 Part 2) and EN 61010-1 5A, CSA/IEC 60950-1 and CSA/IEC 61010-1 Component Recognition Program
Basic insulation per CSA 60950-1-07 and IEC 60950-1
(2nd Ed), 390 VRMS maximum working voltage
Basic Insulation
Basic insulation per CSA 61010-1-04 and IEC 61010-1
Maximum Transient Overvoltage, 4000 VPK Single Protection Isolation Voltage,
(2nd Ed), 300 VRMS maximum working voltage
Maximum Surge Voltage, 4000 VPK 2500 VRMS (1)
Reinforced insulation per CSA 61010-1-04 and IEC
Maximum Working Voltage, 566 VPK
61010-1 (2nd Ed), 150 VRMS maximum working
voltage
File number: 40016131 File number: 220991 File number: E181974

(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Safety input, output, or supply θJA = 114.6°C/W, VI = 5.5V, TJ = 150°C, TA = 25°C 198
IS D-8 mA
current θJA = 114.6°C/W, VI = 3.6V, TJ = 150°C, TA = 25°C 303
TS Maximum case temperature 150 °C

The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.

ISO154x THERMAL DERATING

350
VCC1 = VCC2 = 3.6 V
300
Safety Limiting Current (mA)

250

200
VCC1 = VCC2 = 5.5 V
150

100

50

0
0 50 100 150 200
o
Case Temperature ( C)

Figure 5.

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APPLICATION INFORMATION

I2C™ Bus Overview

The I2C (Inter-Integrated Circuit) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC
communication in half-duplex mode.
I2C uses open-drain technology, requiring two lines, Serial Data (SDA) and Serial Clock (SCL), to be connected
to VDD by resistors (see Figure 6). Pulling the line to ground is considered a logic Zero while letting the line float
is a logic One. This is used as a channel access method. Transitions of logic states must occur while SCL is
Low, transitions while SCL is high indicate START and STOP conditions. Typical supply voltages are 3.3 V and 5
V, although systems with higher or lower voltages are permitted.
VDD

RPU RPU RPU RPU RPU RPU RPU RPU

SDA

SCL

SDA SCL SDA SCL SDA SCL SDA SCL

GND GND GND GND

μC ADC DAC μC
Master Slave Slave Slave

Figure 6. I2C BUS

I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112
nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified,
total bus capacitance of 400 pF, which restricts communication distances to a few meters.
The specified signaling rates for the ISO1540 and ISO1541 are 100 kbps (Standard mode), 400 kbps (Fast
mode), 1 Mbps (Fast mode plus).
The bus has two roles for nodes: master and slave. A master node issues the clock, slave addresses, and also
initiates and ends data transactions. A slave node receives the clock and addresses and responds to requests
from the master. Figure 7 shows a typical data transfer between master and slave.

7-bit 8-bit 8-bit ACK /

SDA ADDRESS
R/W ACK
DATA
ACK
DATA NACK

SCL 1 -7 8 9 1 -8 9 1 -8 9
S P
START STOP
Condition condition

Figure 7. Timing Diagram of a Complete Data Transfer

The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave it
wishes to communicate with. This is followed by a single Read/Write bit, representing whether the master wishes
to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the slave to
acknowledge the receipt of data.
The slave responds with an acknowledge bit (ACK) by pulling SDA low during the entire high time of the 9th
clock pulse on SCL, after which the master continues in either transmit or receive mode (according to the R/W bit
sent), while the slave continues in the complementary mode (receive or transmit, respectively).
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The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a
high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of SDA
while SCL is high.
If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the
master is in master-transmit mode and the slave is in slave-receive mode.
If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the
receipt of every byte but the last one (see Figure 8). In this situation the master is in master-receive mode and
the slave is in slave-transmit mode.
The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for
further transfers.

S Slave Address W A DATA A DATA AP A = acknowledge

A = not acknowledge
From Master to Slave Master Transmitter writing to Slave Receiver
S = Start
From Slave to Master P = Stop
S Slave Address R A DATA A DATA AP R = Read
W = Write
Master Receiver reading from Slave Transmitter

Figure 8. Transmit or Receive Mode Changes During a Data Transfer

When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when
receiving acknowledgment from the slave.
When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending
a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a
transaction.
Note, that the master ends a reading sequence by not acknowledging (NACK) the last byte received. This
procedure resets the slave state machine and allows the master to send the STOP command.

Isolator Functional Principle

To isolate a bidirectional signal path (SDA or SCL), the ISO1540 internally splits a bidirectional line into two
unidirectional signal lines, each of which is isolated via a single-channel digital isolator. Each channel output is
made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1540 connects to a low-
capacitance I2C node, while Side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF
capacitance.

VCC1 VCC2
A
RPU1 RPU2 VC-out
B

SDA1 SDA2
ISO1540
Cnode Cbus 40mV 50mV
C
GND1 D VSDA1
GND2 VILT1 VIHT1 VOL1
VREF

Figure 9. SDA Channel Design and Voltage Levels at SDA1

At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up.
However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode
drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The
comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V
maximum driven directly by SDA1 and the buffered output low-level of B.

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Product Folder Links: ISO1540 ISO1541
ISO1540
ISO1541
SLLSEB6B – JULY 2012 – REVISED MAY 2013 www.ti.com

Figure 10 demonstrate the switching behavior of the I2C isolator, ISO1540, between a master node at SDA1 and
a heavy loaded bus at SDA2
VCC2 VCC2 VCC1 VCC1

VOL1
SDA2 50% SDA1
30% VIHT1

receive
receive transmit delay
delay delay
receive
VCC1 delay VCC1 VCC2 VCC2
transmit VIHT2
delay
SDA1 50% SDA2
30%

Figure 10. SDA Channel Timing in Receive and Transmit Directions

Receive Direction (left diagram)

When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. Its output low will be
the buffered output of VOL1 = 0.75 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a
minimum input-low voltage of VIL = 0.9 V at 3 V supply levels.
Once SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by RPU2
and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the time-constant
RPU1 x Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2 reaches
VCC2 potential.
Transmit Direction (right diagram)
When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns
low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be observed
immediately as it is overwritten by the master’s lower low-level.
However, when the master releases SDA1, its voltage potential increases and first must pass the upper input
threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered
output level of VOL1 = 0.75 V, maintained by the receive path. Once comparator C turns high, SDA2 is released
after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases
SDA1 to move towards VCC1 potential.

12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

Product Folder Links: ISO1540 ISO1541

 ISO1540
ISO1541
www.ti.com SLLSEB6B – JULY 2012 – REVISED MAY 2013

Typical Application Circuit

VS

3.3V 0.1μF
2 1:2.2 MBR0520L 5VISO 0.1μF
Vcc D2 3 1
IN OUT
5
8
LP2981-50 10μF
SN6501 10μF 0.1μF 9 VDD 4
3 2 SDA AIN0
1 ON GND
10 4 Analog
GND D1 1Ω SCL ADS1115
Inputs
10μF MBR0520L 1
4,5 ADDR AIN3
GND RDY 7
3 2
5VISO
ISO-BARRIER 5VISO 6 2

SDA

SCL
5VISO VOUT VIN
22μF 1μF
0.1μF REF5040
4
GND
0.1μF 0.1μF 15 4 12 3
0.1μF
1.5k 1.5k 1.5k 1.5k 11 A2 VDD IOVDD VREFH
SDA 1
2 1 8 VOUTA
10
DVcc VCC1 VCC2 SCL 4 Analog
5 9 2 7 9 DAC8574
XOUT MSP430 SDA SDA1 SDA2 LDAC Outputs
6 8 3 ISO1541 6 14
XIN G2132 SCL SCL1 SCL2 A1 VOUTD
A0 A3 GND VREFL 8
DVss GND1 GND2
13 16 6 5
4 4 5

Figure 11. Isolated I2C Data Acquisition System

In Figure 11, the ultra low-power micro controller, MSP430G2132, controls the I2C data traffic of configuration
data and conversion results for the analog inputs and outputs. Low-power data converters build the analog
interface to sensors and actuators. The ISO1541 provides the necessary isolation between different ground
potentials of the system controller, remote sensor, and actuator circuitry to prevent ground loop currents that
otherwise may falsify the acquired data.
The entire circuit operates from a single 3.3 V supply. A low-power push-pull converter, SN6501, drives a center-
tapped transformer whose output is rectified and linearly regulated to provide a stable 5 V supply for the data
converters.

Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: ISO1540 ISO1541
ISO1540
ISO1541
SLLSEB6B – JULY 2012 – REVISED MAY 2013 www.ti.com

TYPICAL CHARACTERISTICS
SIDE 1 OUTPUT LOW VOLTAGE SIDE 1 OUTPUT LOW CURRENT
vs FREE-AIR TEMPERATURE vs SDA1 or SCL1 APPLIED VOLTAGE
0.800 3.0
o
TA = 25 C
0.780
2.5
0.760

Output Current, IOL1 (mA)

Output Voltage, VOL1 (V)

IOL1 = 3.5 mA
0.740
2.0

0.720 1.5
0.700 IOL1 = 0.5 mA
1.0
0.680

0.660 0.5
0.640
0.0
0.620
0.600 -0.5
−40 −25 −10 5 20 35 50 65 80 95 110 125 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Free−Air Temperature (°C)
Applied Voltage, VSDA1, VSCL1 (V)
Figure 12. Figure 13.

SIDE 1 OUTPUT FALL TIME SIDE 1 OUTPUT FALL TIME

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
20 20
18 18
16 16
14 14
Fall Time, tf1 (ns)

Fall Time, tf1 (ns)

12 12
10 10
8 8
6 6
VCC1 = 3.3 V VCC1 = 5 V
4 C1 = 40 pF 4 C1 = 40 pF
Fall Time measured from R1 = 953 Ω Fall Time measured from R1 = 1430 Ω
2 2
70% to 30% VCC1 R1 = 2.2 kΩ 70% to 30% VCC1 R1 = 2.2 kΩ
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G001
Free-Air Temperature (°C) G002

Figure 14. Figure 15.

SIDE 2 OUTPUT FALL TIME SIDE 2 OUTPUT FALL TIME

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
30 30

25 25
Fall Time, tf2 (ns)

Fall Time, tf2 (ns)

20 20

15 15

10 10
VCC2 = 3.3 V VCC2 = 5 V
C2 = 400 pF C2 = 400 pF
5 5
Fall Time measured from R2 = 95.3 Ω Fall Time measured from R2 = 143 Ω
70% to 30% VCC2 R2 = 2.2 kΩ 70% to 30% VCC2 R2 = 2.2 kΩ
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G003
Free-Air Temperature (°C) G004

Figure 16. Figure 17.

14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

Product Folder Links: ISO1540 ISO1541

 ISO1540
ISO1541
www.ti.com SLLSEB6B – JULY 2012 – REVISED MAY 2013

TYPICAL CHARACTERISTICS (continued)

tPLH1-2 PROPAGATION DELAY tPHL1-2 PROPAGATION DELAY
vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
45 120
C2 = 10 pF C2 = 10 pF
40
Propagation Delay, tPLH1−2 (ns)

Propagation Delay, tPHL1−2 (ns)

100
35
30 80

25
60
20
15 40

10
20
5 VCC1 and VCC2 = 3.3 V, R2 = 95.3 Ω VCC1 and VCC2 = 3.3 V, R2 = 95.3 Ω
VCC1 and VCC2 = 5 V, R2 = 143 Ω VCC1 and VCC2 = 5 V, R2 = 143 Ω
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G005
Free-Air Temperature (°C) G006

Figure 18. Figure 19.

tPLH1-2 PROPAGATION DELAY tPHL1-2 PROPAGATION DELAY

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
1050 90
1045 80
Propagation Delay, tPLH1−2 (ns)

Propagation Delay, tPHL1−2 (ns)

1040 70
1035
60
1030
50
1025
40
1020
30
1015
1010 20
R2 = 2.2 kΩ VCC1 and VCC2 = 3.3 V 10 R2 = 2.2 kΩ VCC1 and VCC2 = 3.3 V
1005
C2 = 400 pF VCC1 and VCC2 = 5 V C2 = 400 pF VCC1 and VCC2 = 5 V
1000 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G007
Free-Air Temperature (°C) G008

Figure 20. Figure 21.

tPLH2-1 PROPAGATION DELAY tPHL2-1 PROPAGATION DELAY

vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
70 80
C1 = 10 pF C1 = 10 pF
60 70
Propagation Delay, tPLH2−1 (ns)

Propagation Delay, tPHL2−1 (ns)

60
50
50
40
40
30
30
20
20
10 VCC1 and VCC2 = 3.3 V, R1 = 953 Ω 10 VCC1 and VCC2 = 3.3 V, R1 = 953 Ω
VCC1 and VCC2 = 5 V, R1 = 1430 Ω VCC1 and VCC2 = 5 V, R1 = 1430 Ω
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G009
Free-Air Temperature (°C) G010

Figure 22. Figure 23.

Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: ISO1540 ISO1541
ISO1540
ISO1541
SLLSEB6B – JULY 2012 – REVISED MAY 2013 www.ti.com

TYPICAL CHARACTERISTICS (continued)

tPLH2-1 PROPAGATION DELAY tPHL2-1 PROPAGATION DELAY
vs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
148 80
R1 = 2.2 kΩ
146 C1 = 40 pF 70
Propagation Delay, tPLH2−1 (ns)

Propagation Delay, tPHL2−1 (ns)

144 60

142 50

140 40

138 30

136 20

134 VCC1 and VCC2 = 3.3 V 10 R1 = 2.2 kΩ VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V C1 = 40 pF VCC1 and VCC2 = 5 V
132 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G011
Free-Air Temperature (°C) G012

Figure 24. Figure 25.

tLOOP1 vs FREE-AIR TEMPERATURE tLOOP1 vs FREE-AIR TEMPERATURE

140 600
C1 = 40 pF R1 = 2.2 kΩ
120 C2 = 400 pF C1 = 40 pF
595 R2 = 2.2 kΩ
100 C2 = 400 pF
tLOOP1 (ns)

tLOOP1 (ns)
590
80

60
585

40
580
20 VCC1 and VCC2 = 3.3 V, R1 = 953Ω, R2 = 95.3Ω VCC1 and VCC2 = 3.3 V
VCC1 and VCC2 = 5 V, R1 = 1430Ω, R2 = 143Ω VCC1 and VCC2 = 5 V
0 575
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G013
Free-Air Temperature (°C) G014

Figure 26. Figure 27.

CMTI vs FREE-AIR TEMPERATURE

70

60

50
CMTI (kV/µs)

40

30

20

10 VCC1 and VCC2 = 3.3 V

VCC1 and VCC2 = 5 V
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
Free-Air Temperature (°C) G015

Figure 28.

16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

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 ISO1540
ISO1541
www.ti.com SLLSEB6B – JULY 2012 – REVISED MAY 2013

TYPICAL CHARACTERISTICS (continued)

SIDE 1 LOW-TO-HIGH TRANSITION

o
TA = 25 C
VCC1 = 3.6 V

500 mV/div

900 mV
VOL1

GND1

Time - 50 ns/div
Figure 29.

Spacer
REVISION HISTORY

Changes from Original (July 2012) to Revision A Page

• Changed From: CSA Component Acceptance Notice 5A (Pending) To: CSA Component Acceptance Notice 5A
(Approved) ............................................................................................................................................................................ 1
• Changed From: IEC 60950-1 and IEC 61010-1 End Equipment Standards (Pending) To: IEC 60950-1 and IEC
61010-1 End Equipment Standards (Approved) ................................................................................................................... 1
• Changed Table 5, CSA column From: File number: 220991 (pending) To: File number: 220991 ....................................... 9

Changes from Original (October 2012) to Revision B Page

• Change Safety Feature From: (VDE 0884 Part 2) (Pending) To: (VDE 0884 Part 2) (Approved) ....................................... 1
• Changed, VDE column From: File number: 40016131 (pending) To: File number: 40016131 ............................................ 9

Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: ISO1540 ISO1541
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Sep-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

ISO1540D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1540
& no Sb/Br)
ISO1540DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1540
& no Sb/Br)
ISO1541D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1541
& no Sb/Br)
ISO1541DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1541
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Sep-2014

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Nov-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1540DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO1541DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Nov-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO1540DR SOIC D 8 2500 367.0 367.0 35.0
ISO1541DR SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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