288 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO.

2, APRIL 1999

Operation of the LCC-Type Parallel Resonant

Converter as a Low Harmonic Rectifier
Vijayakumar Belaguli, Member, IEEE, and Ashoka K. S. Bhat, Fellow, IEEE

Abstract— A 1- high-frequency transformer isolated single- switching frequency required at lower load currents will be
stage ac-to-dc controlled rectifier with low line current harmonic lower, resulting in an increase in the size of the transformer,
distortion using a variable-frequency controlled LCC-type (or while retaining all the well-known disadvantages of leading
series–parallel) resonant converter (SPRC) is presented. A simple
analysis and design procedure is used for designing the converter PF operation [10]. Also, no voltage regulation loop was
for low line current harmonic distortion and high power factor incorporated.
operation. The converter performance characteristics have been The desirable features of LCC-type (or series–parallel)
verified with SPICE3 simulations (without active control) and resonant converter (SPRC) are well established [10]. Variable-
experimental prototype SPRC (rated at 150 W, with and without frequency operation of the SPRC on the utility line (without
active control) for variation in load as well as line voltage. When
operated with active current shaping, this converter operates active control) has been discussed briefly in [4]. However,
in zero-voltage-switching mode for complete range, maintaining the major problems were the requirement to keep the ratio
power factor close to unity with low line current distortion and of switching frequency to series resonance frequency high to
low peak current compared to the parallel resonant converter. maintain lagging PF (ZVS) mode of operation, resulting in
Index Terms— AC-to-DC power converter, frequency control, higher switch peak currents.
HF transformer, power factor, resonant power conversion, zero- In this paper, operation of the full-bridge SPRC with high
voltage switching. PF and reduced line current THD is presented. It is shown that,
with a proper design, it is possible to get reduced line current
I. INTRODUCTION THD, even without active control of line current. However,
at full load, the converter operates in leading PF mode near

R ECENTLY, operation of ac-to-dc converters with high

power factor (PF) and low line current total harmonic
distortion (THD) has formed an active research area [1]–[9].
zero crossings of line voltage. To reduce THD further, an
active current waveshaping feedback circuit is used to vary the
switching frequency. This method also keeps the converter in
This is due to the enforcement (either already existing or ZVS mode for the complete line cycle. An additional feedback
being proposed) of strict harmonic regulations (e.g., IEC555). circuit is used to regulate the output load voltage, also. Some
Advantages of high-frequency (HF) resonant converters have other main features of the proposed converter are single-stage
been utilized in ac-to-dc converters [1]–[7], [9] for realizing power conversion, HF isolation, leakage inductance is part of
power conversion with improved performance (high efficiency, resonant circuit, and lower peak current stresses.
high PF, and low line current THD, etc.) while reducing the
size, weight, and cost. Active line current control has been
used for a single-ended resonant converter to reduce the THD II. CIRCUIT DESCRIPTION AND OPERATION
in [2]. The HF transformer isolated ac-to-dc converter using the
In [1] and [4], operation of resonant converters with high variable-frequency full-bridge SPRC is shown in Fig. 1. A
line PF has been reported. The line current THD was very small dc-link capacitor is used to filter only the switching
high (18% around half load to about 48% at full load) and the frequency components [1], [4], [7], [9]. The resonant tank cir-
switch peak currents did not decrease with the load current cuit is formed by the components (leakage inductance
since a parallel resonant converter (PRC) was used [4]. The of the HF transformer), , and placed on the secondary
line current THD has been reduced by utilizing active current side of the HF transformer. In the output section, and
control scheme in a variable-frequency controlled PRC [5], are designed to filter the switching frequency current ripple
[6]. It was operated in leading PF [zero-current switching and the 120-Hz voltage ripple, respectively. The converter
(ZCS)] mode and results were given only for full load and is designed for continuous current mode (CCM), to operate
at rated line voltage. In addition, due to ZCS operation, at rated minimum input ac voltage and maximum rated
Manuscript received October 12, 1997; revised August 21, 1998. Abstract load current . The output voltage regulation is achieved
published on the Internet January 18, 1999. An earlier version of this paper by increasing the switching frequency for both reduced load
was presented at the 1996 IEEE Applied Power Electronics Conference, San currents and higher input voltages. In open-loop operation,
Jose, CA, March 3–9, 1996.
V. Belaguli is with the Department of Electrical Engineering, Singapore the frequency is varied to regulate the output voltage (no
Polytechnic, Singapore 139651. current control), while for closed-loop operation (i.e., with
A. K. S. Bhat is with the Department of Electrical and Computer Engi- active control), the switching frequency is varied all along
neering, University of Victoria, Victoria, B.C., V8W 3P6 Canada (e-mail:
[email protected]). the ac cycle to draw nearly sinusoidal line current, as well as
Publisher Item Identifier S 0278-0046(99)02707-0. for voltage regulation. As the switching frequency, , is very
0278–0046/99$10.00  1999 IEEE
BELAGULI AND BHAT: OPERATION OF THE LCC-TYPE PARALLEL RESONANT CONVERTER AS A LOW HARMONIC RECTIFIER 289

(a)

Fig. 1. HF transformer isolated ac-to-dc converter employing SPRC bridge

for variable-frequency CCM operation. This converter is operated with or
without active control. For active control, the control circuit schematic shown
in Fig. 7 is used.

high as compared to the frequency of the 120-Hz pulsating

dc-link voltage , the converter can be considered to have
reached steady state for each HF switching cycle to simplify
the analysis presented in Section III.

III. CONVERTER ANALYSIS AND DESIGN OF

SPRC FOR LOW LINE CURRENT THD

A. Analysis
Making simplified assumptions for the analysis of the SPRC (b)
and using complex ac circuit analysis method for an SPRC Fig. 2. DC voltage gain, M , for CCM operation of the SPRC: (a) for
[4], [7], [10] operated with variable-frequency control, the dc Cs =Ct =
0:5 and (b) for Cs =Ct = 1.
converter gain can be shown to be
voltage and is defined as (referred to primary side)

(2)

(1) where .
Also, the series resonant is given by
where is the rated minimum peak input ac voltage,
is the output voltage referred to primary, (3)
is the series resonant frequency,
, is the
where ,
transformer leakage inductance, and is the
HF transformer turns ratio. .
Fig. 2(a) and (b) shows the plot of the voltage gain as a The ac analysis required to determine the ZVS condition and
function of normalized switching frequency , for capacitance the component stresses is given in the Appendix. Using the
ratios of 0.5 and 1, respectively. converter gain relation given in (1), one can plot the required
For sinusoidal line current operation, the current through variation in converter gain , switching frequency ratio
the output inductor is double-frequency sinusoid (on 60- and as shown in Fig. 3, over the 60-Hz ac cycle
Hz scale) [4], [7] with peak value being equal to twice to draw nearly sinusoidal line current from the utility line
the average current delivered to the load at constant output when active control is used. The sharp dip in the curve
290 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 2, APRIL 1999

, the design values were , .

The above design values for the converter will ensure ZVS
operation, in addition to generating the required voltage gain
for most of the ac voltage cycle, while delivering rated output
power at rated minimum input voltage.
B. Design Example
Design procedure is illustrated using a design example for
a converter having the following specifications:
average output power W;
input rms voltage 85–110 V;
output voltage V dc;
(a) output current ripple
(peak-to-peak of ) 20% of ;
output voltage ripple
(peak-to-peak of 120 Hz) 1% of ;
switching frequency 50 kHz.
The design calculations are done for an SPRC delivering
a peak power of by choosing the and at the
peak of the ac line cycle for low line condition (i.e.,
V rms). Using the relations for and , the following
component values are obtained for the two cases.
Case 1— : , ,
V, ,
H, F, and F.
(b) Case 2— : , ,
Fig. 3. Variation of series Qs (t), required converter gain M (t), and nor- V, , ,
malized switching frequency ratio ys (t), to get sinusoidal line current over H, F, and F.
ac half cycle at rated minimum input ac voltage and rated maximum load
conditions: (a) for Cs =Ct = 0:5 and (b) for Cs =Ct = 1. For the output section, for the specified ripple, using the
equations given in [4] and [7], the filter components (for Case
1) were found to be H and F.
around the region below 30 and above 150 in Fig. 3 is
due to insufficient gain near the zero crossings at chosen IV. SPICE SIMULATION RESULTS
operating point. From this curve, it is evident that, for the The 150-W 120-V output 50-kHz converter designed in
chosen variation in , it is not possible to derive the the earlier section was simulated in SPICE3 to evaluate the
required gain from the converter and, hence, discontinuity in converter performance without active current control.
the input current, as well as in the output inductor current For a capacitance ratio of , the harmonic
waveform, is expected beyond this point, even with active distortion in the line current waveform [Fig. 4(a)-(i)] is 14.1%
control irrespective of . at full load and rated minimum input voltage. The SPRC
However, if no active control is used, one has to choose operates in lagging PF mode near the peak, and leading PF
the operating point very carefully to satisfy all the design mode near the zero crossings of the ac voltage cycle, as shown
constraints, such as reduced peak current stresses, small vari- in Fig. 4(a)-(ii) and (a)-(iii), respectively. At full load, the
ation in frequency for output voltage regulation, and required SPRC operates in continuous capacitor voltage mode (CCVM),
converter gain for at least 30 –150 of ac line cycle (as the as shown in Fig. 4(a)-(iv). The line current waveform for 53%
most part of total output power is delivered in this range) load shown in Fig. 4(b) has a THD of 15.5%. The SPRC
to obtain low line current distortion. Even though higher operated fully in lagging PF mode for decreased load currents
will be the obvious choice to reduce the rms current, due to increased for regulated output.
it increases the peak current stresses beyond a certain value, Similarly for a capacitance ratio , at full load
due to the decrease in converter gain and increase in with minimum input voltage, the line current THD is 19.8%
output current for the same rated power output. For variable- [Fig. 4(c)-(i)]. The converter operated in lagging PF mode
frequency CCM operation, choosing the closer to the [Fig. 4(c)-(ii)] near peak of line cycle and in discontinuous
load-independent point on the gain curve reduces the range capacitor voltage mode (DCVM) [Fig. 4(c)-(iii)], while deliv-
of variation in frequency required from full load to light load, ering rated output power at rated minimum input ac voltage.
in addition to reduction in inverter peak current stresses. Since the converter operated in DCVM at full load and in
From the ac analysis given in (1)–(3) and the Appendix CCVM at reduced load, the range of variation in switching
[7], it was found that, for a given peak value of frequency to regulate the output was larger for a capacitance
, good compromised design values obtained were ratio of 1. In all these simulations, the switching frequency
, for . Similarly, for was increased to regulate the output voltage at reduced loads.
BELAGULI AND BHAT: OPERATION OF THE LCC-TYPE PARALLEL RESONANT CONVERTER AS A LOW HARMONIC RECTIFIER 291

(a)-(i) (b)

(a)-(ii) (c)-(i)

(a)-(iii) (c)-(ii)

(a)-(iv) (c)-(iii)
=
Fig. 4. SPICE3 simulation waveforms for 150-W (full load) 50-kHz variable-frequency SPRC bridge operating on the utility line (Vac 85 V rms) without
active control (Cs =Ct = 0:5 and Vo0 = 120 V). (a) At full load: (a)-(i) line voltage vac and line current iac ; (a)-(ii) lagging PF mode (near peak of line cycle);
(a)-(iii) leading PF mode (near valleys of line cycle); (a)-(iv) vab ; vCt ; vCs (near peak). (b) At 53% load: vac ; iac . (c) Full load (Cs =Ct = 1; Vo0 = 90
V): (c)-(i) vac ; iac ; (c)-(ii) lagging PF (near peak); (c)-(iii) vab ; vCs ; vCt (near peak).
292 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 2, APRIL 1999

(a)-(i) (b)-(i)

(a)-(ii) (b)-(ii)

(a)-(iii) (c)-(i)

(a)-(iv) (c)-(ii)
Fig. 5. Experimental waveforms and line current harmonic spectra for different load conditions for a variable-frequency SPRC bridge operating on the
utility line (Fig. 1) without active control (Cs =Ct = 0:5, Ld = 500 H, Cd = 1000 F, Vo0 = 120 V). Minimum input voltage, Vac = 85 V rms:
(a) full load (RL = 96
); (b) 53% load (RL = 180
). Maximum input voltage, Vac = 110 V rms: (c) full load (RL = 96
). (a)-(i) vac ; iac ; id ,
and Vo ; (a)-(ii) vab ; iL ; vCt , and vCs (near peak); (a)-(iii) vab ; iL ; vCt , and vCs (near valleys); (a)-(iv) harmonic spectra of iac . (b)-(i) vac and iac ;
(b)-(ii) harmonic spectra of iac . (c)-(i) vac and iac ; (c)-(ii) harmonic spectra of iac .
BELAGULI AND BHAT: OPERATION OF THE LCC-TYPE PARALLEL RESONANT CONVERTER AS A LOW HARMONIC RECTIFIER 293

(d)-(i) (d)-(ii)
Fig. 5. (Continued.) Experimental waveforms and line current harmonic spectra for different load conditions for a variable-frequency SPRC bridge operating
=
on the utility line (Fig. 1) without active control (Cs =Ct 0:5, Ld = 500 H, Cd = 1000 F, Vo0 = 120 V). Maximum input voltage, Vac = 110
V rms: (d) 53% load (RL = 180
). (d)-(i) vac and iac ; (d)-(ii) harmonic spectra of iac .

TABLE I
EXPERIMENTAL RESULTS FOR A 150-W AC-TO-DC VARIABLE-FREQUENCY SPRC WITHOUT ACTIVE CONTROL

It must also be noted that the line current waveforms shown predominant harmonic components are the fifth and seventh.
in Fig. 4(a)-(i), (b), and (c)-(i) are unfiltered and include HF The THD reached a minimum of 11.9% at 53% load, as
ripple. shown in the harmonic spectra [Fig. 5(b)-(ii)] of line current
[Fig. 5(b)-(i)]. The maximum distortion occurred at an operat-
V. EXPERIMENTAL RESULTS ing frequency of 54.5 kHz, at 80% load, due to overboosting
effect at all points along the ac cycle. At 10% load, the
Based on the design presented in Section III-B, a breadboard
PF decreased due to increased magnitude of third harmonic
model of the SPRC rated at 150 W, operating on a 60-Hz,
component, with a THD of 22.3%. The switch peak switch
85–110 V utility line was built using IRF640 MOSFET’s
current reduced from 4.54 A (1.816 p.u.) at full load to 3.75 A
in a bridge configuration using readily available 1 : 1 HF
(1.5 p.u.) at 10% load. At full load, the peak voltages across
transformer having 12 turns each. The SPRC was controlled
and are 628 V (5.233 p.u.) and 218 V (1.817 p.u.),
using a high-speed UC2825 pulsewidth modulation (PWM)
respectively.
controller, configured for variable-frequency operation.
For an input voltage of 110 V rms, the line current wave-
forms obtained are presented in Fig. 5(c)-(i) and (d)-(i). The
A. Without Active Control THD reached a maximum (due to square waveform) of 34.5%
The various waveforms and line current harmonic spectra at full load and a minimum of 12.8% at 53% load, as shown
obtained from the prototype model are presented in Figs. 5 in Fig. 5(c)-(ii) and (d)-(ii), respectively. At 53% load, the
and 6 for different loading conditions and ratios of 0.5 third harmonic component is negligible. For regulated output,
and 1, respectively. the required variation (increase) in switching frequency for the
1) For —Fig. 5: The THD [harmonic spectra complete load and line variation is 50–63.93 kHz, as shown in
shown in Fig. 5(a)-(iv)] obtained for the line current waveform Table I(a). The switch peak current reduced from 4.9 A (1.96
(full load, rated minimum input voltage) shown in Fig. 5(a)-(i) p.u.) at full load to 3.5 A (1.4 p.u.) at 10% load.
is 13.5%. The lagging PF and leading PF operation along with 2) For —Fig. 6: At full load and rated min-
the resonant capacitor voltage waveforms at full load, near imum input voltage, the line current waveform shown in
the peak and the valleys of the ac voltage cycle are shown Fig. 6(a)-(i) has a THD of 18.9% [Fig. 6(a)-(ii)]. The THD
in Fig. 5(a)-(ii) and (a)-(iii), respectively. At full load, the reached a maximum of 37.47% [Fig. 6(b)] and 37.35%, at 60%
294 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 2, APRIL 1999

(a)-(i) (b)-(i)

(a)-(ii) (b)-(ii)

(c)-(i) (d)-(i)

(c)-(ii) (d)-(ii)
Fig. 6. Experimental waveforms and line current harmonic spectra for the ac-to-dc converter (Fig. 1) without active control (Cs =Ct = 1, Ld = 500 H,
Cd = 1000 F, Vo0 = 90 V). (i) Waveforms vac and iac ; (ii) harmonic spectra of iac , for the following operating conditions. Vac = 85 V rms: (a) full load
(RL = 54
); (b) 60% load (RL = 90
). Vac = 110 V rms: (c) full load (RL = 54
); (d) 50% load (RL = 108
).

and 80% rated load, for rated minimum and maximum input (1.114 p.u.) at full load to 3.3 A (0.742 p.u.) at 11.25% load.
voltage, respectively. This phenomenon occurs approximately Selected experimental results are given in Table I(b).
at 60 kHz due to overboosting effect all along the valleys The overboosting effect observed in variable-frequency op-
of the ac voltage and, hence, quasi-square waveform of line eration of the SPRC is due to the converter operating point
current. The switch peak current reduced from 5.28 A (1.188 (switching frequency ratio ) being close to the resonant peak
p.u.) at full load to 3.2 A (0.72 p.u.) at 11.25% load, with rated point, where the achieve their maximum at their respective
minimum voltage (85 V rms). At full load, the peak voltages . For example, Fig. 2(a) shows that achieves its maxi-
across and are 377 V (3.14 p.u.) and 198 V (1.65 mum, at a switching frequency ratio , approximately
p.u.), respectively. Fig. 6(c) and (d) shows the waveforms and for all values of . The same explanation holds good
harmonic spectra of line current for full load and half load for ratio of 1 [Fig. 2(b)] and occurs at .
with 110-V input. With rated maximum input voltage, the All these experimental waveforms and the results are in
peak current carried by the switches reduced from 4.95 A good agreement with the SPICE3 simulation results. The line
BELAGULI AND BHAT: OPERATION OF THE LCC-TYPE PARALLEL RESONANT CONVERTER AS A LOW HARMONIC RECTIFIER 295

Fig. 7. Active current control scheme block diagram for SPRC bridge (Fig. 1) operating on the utility line.

(a)-(i) (b)-(i)

(a)-(ii) (b)-(ii)

(a)-(iii) (c)-(i)

(a)-(iv) (c)-(ii)
=
Fig. 8. Experimental waveforms for a variable-frequency SPRC bridge operating on the utility line with active current control (Cs =Ct 0:5, Ld = 500 H,
Cd = 1000 F, Vo0 = 120 V). Vac = 85 V rms: (a) full load (RL = 96
); (b) 53% load (RL = 180
). Vac = 110 V rms: (c) full load
(RL = 96
). (a)-(i) vac and iac ; (a)-(ii) harmonic spectra of iac ; (a)-(iii) vab and iL (near peak); (a)-(iv) vab and iL (near valleys). (b)-(i) vac and
iac ; (b)-(ii) harmonic spectra of iac . (c)-(i) vac and iac ; (c)-(ii) harmonic spectra of iac .

PF is maintained in the upper 90’s, for the entire load range active control. It is shown in the next section that, by using
with variable-frequency operation of the SPRC, even without active line current control, the THD is further reduced.
296 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 2, APRIL 1999

(c)-(iii) (d)-(i)

(c)-(iv) (d)-(ii)
=
Fig. 8. (Continued.) Experimental waveforms for a variable-frequency SPRC bridge operating on the utility line with active current control (Cs =Ct 0:5,
Ld = 500 H, Cd = 1000 F, Vo0 = 120 V). Vac = 110 V rms: (c) full load (RL = 96
); (d) 53% load (RL = 180
). (c)-(iii) vab and iL
(near peak); (c)-(iv) vab and iL (near valleys). (d)-(i) vac and iac ; (d)-(ii) harmonic spectra of iac .s

B. With Active Current Control block K4 is used to obtain the additional dc offset voltage so
In order to reduce the line current THD, a variable- that the controller input voltage for VCO section does not go
frequency active current control scheme has been imple- below a lower limit (which decides the lowest frequency of
mented, and the details are given below. operation) at any point of time and for changes in load, thus
1) Implementation of Active Current Control Scheme: The avoiding below resonance operation.
block schematic of the active current control scheme imple- The various waveforms obtained from variable-frequency
mented with the breadboard model is shown in Fig. 7. In order active control scheme are presented in Figs. 8 and 9, corre-
to keep the output voltage constant for varying input voltage sponding to capacitance ratios 0.5 and 1, respectively.
and output load, and also to keep the input line current close 2) For —Fig. 8: The THD at full load
to sinusoidal and in phase with the line voltage, the proposed [Fig. 8(a)-(i)] and 53% load [Fig. 8(b)-(i)] are 8% and 9.61%,
control scheme is equipped with two control loops. at rated minimum input voltage, as shown in the harmonic
a) The outer voltage feedback loop: The outer output spectra of Fig. 8(a)-(ii) and (b)-(ii), respectively. The converter
voltage loop forces the ac-to-dc converter to work as a dc operated with ZVS for all the switches throughout the ac cycle
voltage source at its output. This is a slow-varying loop with active control at full load, as shown on the HF scale in
consisting of output voltage sensing amplifier, proportional Fig. 8(a)-(iii) and (a)-(iv). The switching frequency variation
integral (PI) compensator-1, and a multiplier. The output is from 50 kHz (near peak of line voltage) to about 55 kHz
voltage is sensed by a voltage divider ( ) and compared (near valleys of line voltage) at full load. The switch peak
with a set reference signal ( ) using a PI compensator. The current variation is from 4.8 A (1.92 p.u.) at full load to
error signal in combination with sinusoidal reference 3.7 A (1.48 p.u.) at 10% load with rated minimum input
is used to generate the varying amplitude sinusoidal reference voltage.
current for referencing the inner current control loop. Corresponding to an input voltage of 110 V rms, the THD
b) The inner current control loop: The current-control- for the line current waveforms shown in Fig. 8(c)-(i) and (d)-
ling feedback loop is used to monitor the mains current (i) were 9.2% [Fig. 8(c)-(ii)] and 14.36% [Fig. 8(d)-(ii)], at
and force it to follow the mains voltage. This control loop full load and 53% load, respectively. The switch peak current
consists of a PI compensator-2, with inputs as conditioned reduced from 5.04 A (2.016 p.u.) at full load to 3.5 A (1.4
line current waveform to be shaped and the reference p.u.) at 40% rated load.
current . The reference current signal has quick control 3) For —Fig. 9: Corresponding to a capaci-
of the line current, while the output voltage error has a tance ratio of 1 with rated minimum input voltage, the line
slow control over the line current. The result is that the dc-link current waveforms shown in Fig. 9(a)-(i) and (b)-(i) have a
current varies as a rectified sinusoid and the voltage regulation distortion figure of 7.4% [Fig. 9(a)-(ii)] and 11.33% [Fig. 9(b)-
is achieved by adjusting the amplitude of the voltage error (ii)], at full load and 50% load, respectively. As shown in
signal . Finally, the control voltage to the UC2825 Fig. 9(a)-(iii) and (a)-(iv) for full load, the switching frequency
controller is generated by summation of error and after near the peak and valleys of line voltage are 51.28 and 58.82
proper scaling and limiting circuits. Note that the attenuator kHz, respectively. The inductor peak current carried by the
BELAGULI AND BHAT: OPERATION OF THE LCC-TYPE PARALLEL RESONANT CONVERTER AS A LOW HARMONIC RECTIFIER 297

(a)-(i) (b)-(i)

(a)-(ii) (b)-(ii)

(a)-(iii) (c)-(i)

(a)-(iv) (c)-(ii)
Fig. 9. Experimental waveforms for a variable-frequency SPRC bridge operating on the utility line with active current control (Cs =Ct = 1, Ld = 500 H,
Cd = 1000 F, Vo0 = 90 V). Vac = 85 V rms: (a) full load (RL = 54
); (b) 50% load (RL = 108
). Vac = 110 V rms: (c) full load
(RL = 54
). (a)-(i) vac and iac ; (a)-(ii) harmonic spectra of iac ; (a)-(iii) vab and iL (near peak); (a)-(iv) vab and iL (near valleys). (b)-(i) vac and
iac ; (b)-(ii) harmonic spectra of iac . (c)-(i) vac and iac ; (c)-(ii) harmonic spectra of iac .

switch reduced from 4.75 A (1.068 p.u.) at full load to 2.9 load. At full load, the peak voltages across and are 325
A (0.65 p.u.) at 22.5% load. At full load, the peak voltages V (2.71 p.u.) and 205 V (1.708 p.u.), respectively.
across and are 270 V (2.25 p.u.) and 190 V (1.583 The key results have been tabulated in Table II(a) and (b),
p.u.), respectively. for ratios of 0.5 and 1, respectively. The utility line
For an input voltage of 110 V rms, the THD for the line cur- voltage had 2% THD.
rent waveforms at full load and half load shown in Fig. 9(c)-(i) The 150-W experimental converter was built only to demon-
and (d)-(i) are 13% [Fig. 9(c)-(ii)] and 12.11% [Fig. 9(d)-(ii)], strate the principles of operation. This converter can be used
respectively. In all these line current waveforms presented, the for power levels of the order of 500 W–1 kW. It can easily be
third harmonic component is either absent or reduced to less verified that the proposed converter satisfies the line current
than 3%. Also, the converter operates in ZVS mode for the total harmonic distortion specified in the IEC 1000-3-2 stan-
complete operating range [refer to Fig. 9(a)-(iii), (a)-(iv), (c)- dards [11]. Referring to Fig. 3 of [11], it can be concluded
(iii), and (c)-(iv)]. The switch peak current reduces from 4.4 that, for power levels less than 1.5 kW, the most stringent
A (0.99 p.u.) at full load to 3.15 A (0.709 p.u.) at 22.5% rated class C standard is satisfied, even without active control.
298 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 2, APRIL 1999

(c)-(iii) (d)-(i)

(c)-(iv) (d)-(ii)
Fig. 9. Fig. 9. (Continued.) Experimental waveforms for a variable-frequency SPRC bridge operating on the utility line with active current control
(Cs =Ct = 1, Ld = 500 H, Cd = 1000 F, Vo0 = 90 V). Vac = 110 V rms: (c) full load (RL = 54
); (d) 50% load (RL = 108
). (c)-(iii)
vab and iL (near peak); (c)-(iv) vab and iL (near valleys). (d)-(i) vac and iac ; (d)-(ii) harmonic spectra of iac .

TABLE II
EXPERIMENTAL RESULTS FOR A 150 W, AC-TO-DC VARIABLE FREQUENCY SPRC WITH ACTIVE CONTROL

VI. CONCLUSIONS APPENDIX

The SPICE3 simulation and experimental results show that, AC ANALYSIS FOR ZVS AND COMPONENT STRESSES
by proper converter design, one can get low line current The impedance (in per unit) looking into the terminals
THD and high PF ( ) with a full-bridge SPRC, even and is
without active control. The capacitance ratio 0.5 is preferred p.u. (A1)
as the THD figures, the peak current stresses, and range of
where
variation in frequency from full load to light load are lower as
compared to those figures obtained for ratio 1, when
no active control is used. With the implementation of active (A2)
control scheme, the PF is maintained close to unity ( 0.99)
with further reduction in THD. For active current control, a (A3)
capacitance ratio of 1 is recommended as the THD figures Peak inductor current or transistor peak current,
are lower (8% at full load). Switch peak current stresses are
p.u. (A4)
also lower for ratio of 1. Due to DCVM operation, the
rectifier diode voltage stresses are slightly higher and require The initial inductor current (at ) is given by
larger variation in frequency to regulate the output voltage. The p.u. (A5)
experimental converter built had a switching frequency of 50
kHz at full load and this was used only to demonstrate the high where
PF, low THD that can be obtained with variable-frequency rad (A6)
operation of SPRC. However, higher switching frequency can
be used with active control scheme, as ZVS operation is For above resonance (or lagging PF) operation, i.e., for ZVS,
maintained over the entire 60-Hz ac cycle. must be negative.
BELAGULI AND BHAT: OPERATION OF THE LCC-TYPE PARALLEL RESONANT CONVERTER AS A LOW HARMONIC RECTIFIER 299

Peak voltage across the series capacitor , Vijayakumar Belaguli (S’93–M’95) received the
M.E. degree from the Indian Institute of Science,
p.u. (A7) Bangalore, India, and the Ph.D. degree from the
University of Victoria, Victoria, B.C., Canada, in
Peak voltage across the parallel capacitor , 1986 and 1996, respectively, both in electrical en-
gineering.
From 1986 to 1991, he was a Software/Hardware
V (A8) Design Engineer in the Switching Research and De-
velopment Department, Indian Telephone Industries,
REFERENCES Bangalore, India. Since 1996, he has been a Lecturer
in the Electrical Engineering Department, Singapore
[1] D. Chambers, “A new high frequency resonant technique for dynamic Polytechnic, Singapore. His areas of interest include modeling, analysis, and
correction of off-line converter input current waveforms,” in Proc. design of switch-mode resonant power supplies, power factor correction,
Powercon-10, 1983, pp. 1–7. microprocessor application in power electronics, and drives for EV’s.
[2] J. He and N. Mohan, “Input-current shaping in line-rectification by
resonant converters,” in Conf. Rec. IEEE-IAS Annu. Meeting, 1987, pp.
990–995.
[3] E. B. G. Nijhof, “Resonant power supply (RPS) converters: The solution
for mains/line pollution problems,” PCI, pp. 104–139, June 1986.
[4] M. J. Schutten, R. L. Steigarwald, and M. H. Keraluwala, “Character-
istics of load resonant converters in high power factor mode,” in Conf.
Ashoka K. S. Bhat (S’82–M’84–SM’87–F’98) re-
Rec. IEEE APEC’91, 1991, pp. 5–16.
[5] J. Hong, E. Ismail, I. Khan, and R. Erickson, “Design of the parallel ceived the B.Sc. degree in physics and mathematics
resonant converter as a low harmonic rectifier,” in Conf. Rec. IEEE from Mysore University, India, in 1972, the B.E.
APEC’93, 1993, pp. 833–840. degree in electrical technology and electronics and
[6] J. Hong, D. Maksimovic, R. Erickson, and I. Khan, “Half cycle the M.E. degree in electrical engineering from the
control of the parallel resonant converter operated as high power factor Indian Institute of Science, Bangalore, India, in
rectifier,” in Conf. Rec. IEEE APEC’94, 1994, pp. 556–562. 1975 and 1977, respectively. and the M.A.Sc. and
[7] V. Belaguli, “Series-parallel and parallel series resonant converters Ph.D. degrees in electrical engineering from the
operating on the utility line—Analysis, simulation and experimental University of Toronto, Toronto, Ont., Canada, in
results,” Ph. D. dissertation, Dep. Elect. Comput. Eng., Univ. Victoria, 1982 and 1985, respectively.
Victoria, B.C., Canada, Jan. 1996. From 1977 to 1981, he was a Scientist in the
[8] G. Rim and R. Krishnan, “AC to DC power conversion with unity power Power Electronics Group, National Aeronautical Laboratory, Bangalore, In-
factor and sinusoidal input current,” in Conf. Rec. IEEE APEC’91, 1991, dia, and was responsible for the completion of a number of research and
pp. 400–406. development projects. He was also a Research Scholar at the Indian Institute
[9] H. Seidel, “A high power factor tuned class D converter,” in Conf. Rec. of Science during 1980–1981. After working as a Postdoctoral Fellow for a
IEEE Power Electronics Specialists Conf., Apr. 1988, pp. 1038–1042. short time, he joined the Department of Electrical Engineering, University of
[10] R. L. Steigerwald, “A comparison of half-bridge resonant converter Victoria, Victoria, B.C., Canada, where he is currently a Professor of Electrical
topologies,” IEEE Trans. Power Electron., vol. 3, pp. 174–182, Apr. Engineering and is engaged in teaching and conducting research in the area
1988. of power electronics. He has been responsible for the development of the
[11] R. Redl, A. S. Kislovski, and B. P. Erisman, “Input-current clamping: Electromechanical Energy Conversion and Power Electronics Laboratories.
An inexpensive novel control technique to achieve compliance with Dr. Bhat is a Fellow of the Institution of Electronics and Telecommunication
harmonic distortion,” in Conf. Rec. IEEE APEC’96, San Jose, CA, 1996, Engineers (India) and a member of the Association of Professional Engineers
pp. 145–151. of British Columbia, Canada.