Digital Microelectronic

Circuits
(361-1-3021 )
Presented by: Adam Teman

Lecture 9:

Pass Transistor
Logic
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 1
 Motivation
 In the previous lectures, we learned about Standard CMOS
Digital Logic design.
 CMOS is unquestionably the leading design family in use
today, do to its many advantages and relative simplicity.
However, it has a number of drawbacks that have led to the
development of alternative solutions.
 The main drawback of Standard CMOS is its relatively large
area (2N transistors to implement an N-input gate).
 In this lecture, we will learn about an alternative logic
family that tries to reduce the number of transistors
needed to implement a logic function, and achieve faster
switching times.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 2
 What will we learn today?
9.1 Pass Transistor Logic

9.2 Extending the PTL Concept

9.3 Transmission Gates

9.4 PTL Logical Effort

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 3
 9.1
9.1 Pass Transistor Logic

9.2 Extending the

PTL Concept

9.3 Transmission Gates

9.4 PTL Logical Effort

What happens if we look at a

MOSFET from the diffusions,
instead of through the gate?

PASS TRANSISTOR LOGIC (PTL)

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 4
 PTL Concept
 A popular and widely-used alternative to Standard CMOS is
Pass Transistor Logic (PTL).
 PTL attempts to reduce the number of transistors required
to implement logic by allowing the primary inputs to drive
source and drain terminals in addition to the gate terminals.
 Using PTL, we can reduce the number of transistors to
implement a 2-input AND gate to 4 (instead of 6 for Standard
CMOS).
 Broadening the PTL Concept, we can make some more
interesting gates.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 5
 Relay Multiplexers
 The Pass Transistor concept is based on the use of relay
switches.
 A number of inputs are connected to switches and only one
of the switches is chosen to be transferred to the output.
 In essence, we have created a Multiplexer:
B

Switch Out A
Inputs

Network B
B

Digital Microelectronic Circuits

• N transistors
The VLSI Systems Center - BGU Pass Transistor Logic 6
 PTL Concept
 A simplification of the relay multiplexer would be to connect
two inputs to a single nmos transistor – one to the gate and
the other to one of the diffusions (source/drain):

Y  A B

 It looks like we got an AND gate with a single transistor:

» When B=‘1’, it passes A to the output.
» When B=‘0’ it blocks the output.
 But this is incorrect, as when the nMOS is switched off and
the output node stays floating, its value depends on its
previous state.
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 7
 PTL AND Gate
 In fact, this type of a switch is often used in digital and
analog circuits, but it is not an AND gate.
 We’ll take this basic operation and produce an AND gate by
adding a path to GND when B=‘0’.

 We can get this by adding an nMOS

with its gate connected to B_ and its
source connected to GND.
 This is a basic PTL AND Gate!

 It’s comprised of a total of 4 transistors

because we need an inverter to get B_. Y  A B
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 8
 Example – tpd of PTL AND Gate
 Let’s find the delay of a ‘0’’1’ transition from the diffusion
input.
 Assume that at t<0, B=‘1’, A rises and Vout=0V
B
A
M1 Out
B
M2

 Since M2 is cut-off, we can just remove it from our

equivalent model:

A M1 Out

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 9
 Example – tpd of PTL AND Gate
 Now let’s mark the source and drain and the bias voltages:

G VGS=VDD-Vout(t)
A M1 Out
D S
 We see that:
VDS=VDD-Vout(t)
» The gate’s overdrive (VGS-VT)
is a function of the output voltage. VSB=Vout(t)
» VDS is a function of the output voltage.
» VSB is non-zero, so we have to
regard the body effect.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 10
 Example – tpd of PTL AND Gate
 We’ll check two points for delay, t=0 and t=tpd:
» At t=0:
VGS  VDD  0  VDD 

VDS  VDD  0  VDD Vel.Sat
VDSeff  min VDS ,VDSAT ,VGT   VDSAT 
VSB  0  VT  VT 0 G VGS=VDD-Vout(t)
A M1 Out
» At t=tpd: D S
VGS  VDD 
VDD

VDD 
2 2  VDS=VDD-Vout(t)
VDD VDD 
VDS  VDD   VDD 
2 
Sat * VSB=Vout(t)
2

VDSeff  min VDS , VDSAT , VGT   VGT 

V
VSB  DD  VT  VT 0 *Depending on given values…
2
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 11
 Example – tpd of PTL AND Gate
 To find tpd, we need to solve an integral on the current:
dvc dv
ic  c  dt  c c
dt ic G VGS=VDD-Vout(t)
t pd
VDD
 VGT VDSAT VDD
 A
2
c
dvc  c  
dv 2
dvc  M1 Out
 dt   ic  0
c
 
ic VGT VDSAT ic  D S
 
0 0

ic  kn VGTVDSeff  0.5VDSeff  1  VDS 

2 VDS=VDD-Vout(t)

 
VSB=Vout(t)
VT  VT 0   2 F  VSB  2 F

 But since this is “long and ugly”, we can probably just take
average currents.
VDD
vc 2
c c
 
t pd
iavg 0.5 it 0  it t pd
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 12
 Cascading PTL AND Gates
 This AND gate has a big drawback...
 Remember that nMOS transistors pass
a Weak ‘1’?
Y  A B
 Well, we can see that VOHmax of this gate
is only VDD-VTn, at which point the switch
will turn off.

 This means that we cannot drive

another PTL gate input with this output.

Y  VDD  2  VTn

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 13
 Cascading PTL AND Gates
 However, we can connect the output
to the next gate’s diffusion input:

Y  A B
Y  VDD  VTn

 There is some signal degradation, so we need to add a

CMOS Inverter every few gates to replenish the level.

 While this gate requires less power than a CMOS AND

(lower capacitance, reduced swing), it may cause static power
on the partially on inverters it drives.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 14
 Static Power Problem
 For example, let us cascade an inverter after a PTL AND
gate and drive the input high. VSGp=VTn
 The output will be pulled up to B
VDD-VTn, but due to the body M3
A Vx=VDD-VTn
effect,VTn>VTn0. M1
 The input to the next stage B
M2 M4
providesVSGp=VDD-(VDD-VTn).
If this is larger than VTp, then
the pmos is conducting and static
current will flow freely.
 Even if it VSGp<VTp, this transistor is in weak inversion and
dissipates substantial static power.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 15
 PTL AND VTC
 To analyze the static properties of the PTL AND gate, we
will draw its VTC.
B
 We’ll start with the VTC from A to Out with B=‘1’ M1
A Out
 In this case, the output simply Out B
M2
follows the input until the pass
transistor closes at VDD-VT.
VDD-VT

 In other words, this input doesn’t

have the required regenerative
property for a digital gate!
A
VDD-VT

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 16
 PTL AND VTC
 What about the VTC from B to Out with A=‘1’? This case is
more complex. B

 Starting at B<VT, M1 is off and M2 is on.

A M1 Out
We get Vout=0. Out
B M2
 M2 is on until B=VDD/2, but when
B=VT, M1 turns on. Therefore
Vout will slowly rise with B. VDD-VT

 At B=VDD/2, M2 turns off and

M1 has no contention. VDD/2-VT
 Therefore, Vout will “jump” to
VDD/2-VT and rise linearly until
VOHmax=VDD-VT B

VDD/2
Digital Microelectronic Circuits The VLSI Systems Center - BGU VT Pass Transistor Logic 17
 PTL AND Gate Summary
 PTL gates are non-regenerative and therefore not digital.
» To use them as digital gates they must be followed by a CMOS
buffer!

 PTL gates do not present a rail-to-rail swing

» Therefore cascaded stages may dissipate static power.
» Cascading PTL gates through gate inputs causes loss of signal and
is therefore not allowed.

 However, certain functions can be implemented with fewer

transistors than CMOS
» And in certain cases, specific transitions may be faster.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 18
 Level Restoration
 One of the options to solve the problem of the Weak ‘1’ is
Level Restoration.
 This can be achieved by using a PTL AND gate, followed by
an inverter with a feedback loop to a pMOS transistor.
» When node X is high (VDD-VTn), the
Inverter outputs a ‘0’, opening the
pMOS “bleed” transistor.
» This restores the level at X to VDD.
» When node X makes a ‘1’ to ‘0’
transition there is a “fight” between
the bleed transistor and the low input.

 This means we need careful Ratioed Sizing to make the

circuit work properly.
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 19
 Level Restorer Sizing
 The level restorer “fights” the pass transistor when pulling
down through the diffusion input.
 Therefore the pass transistor must be strong enough to flip
the cascaded inverter.
 We will solve this problem by disconnecting the feedback
loop:

B P1 P1
AA
M1 Vx Out
M1
B
M2

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 20
 Level Restorer Sizing
 Now we just have to make sure that the stable
state of VX is lower than the inverter’s VM.

I DSn  sat   I SDp  vel.sat 

kn VDD
find  Vx  VSGp=VDD
kp 2
VSDp=VDD-Vx
P1
M1

• Advice from the guys VGSn=VDD

who write the test… VDSn=Vx
Solve this problem at home!

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 21
 9.2
9.1 Pass Transistor Logic

9.2 Extending the

PTL Concept

9.3 Transmission Gates

9.4 PTL Logical Effort

So based on the pass transistor

concept, let’s try to compose
some useful circuits

EXTENSION OF THE PTL CONCEPT

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 22
 CPL
 Using the PTL concept, we can assemble an interesting
highly modular gate family called Differential or
Complementary Transmission Logic (DPL or CPL).
» These gates inherently create differential
outputs, in other words, both a logic function
and its complement.
» These can reduce the overall transistor
count, as the extra inverters aren’t needed.

 CPL gates enable us to efficiently realize some complex

gates, such as XORs and Adders with a relatively small
number of transistors.
 All CPL gates have the same topology, using 4 pass transistors
and complementary inputs.
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 23
 CPL
 If we take the basic topology and connect different inputs,
we can make many different functions:
B B
A B f
0 0
0 1
A N1 1 0
1 1
B N2
AB
A B f
0 0
A N3
0 1
1 0

B N4 AB 1 1

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 24
 CPL
 If we take the basic topology and connect different inputs,
we can make many different functions:
B B
A B f
0 0
0 1
A N1 1 0
1 1
B N2
A+B
A B f
0 0
A N3
0 1
1 0

B N4 A+B 1 1

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 25
 CPL
 If we take the basic topology and connect different inputs,
we can make many different functions:
B B
A B f
0 0
0 1
A N1 1 0
1 1
A N2
A^B
A B f
0 0
A N3
0 1
1 0

A N4 A^B 1 1

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 26
 Solving the Weak ‘1’ Problem in CPL

N1

N2

N3

N4

• Doesn’t load the output.

• Less of a ratio problem
(the restorer is turned off by the opposite circuit).
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 27
 9.3
9.1 Pass Transistor Logic

9.2 Extending the

PTL Concept

9.3 Transmission Gates

9.4 PTL Logical Effort

So PTL has its drawbacks, but we will often find the

concept used as part of the

TRANSMISSION GATE
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 28
 Transmission Gates
 The most commonly used implementation
of PTL architecture is in Transmission Gates.
 These gates use an nMOS and a pMOS
connected in parallel, utilizing the
advantages of each.
 In this way, we can get both a Strong ‘1’
and a Strong ‘0’, thus achieving a full swing. B  A, if C  '1'

 The basic Transmission Gate is a

bidirectional switch, passing a signal
through when the control signal is on.
 The symbolic representation of a
Transmission Gate is shown here:
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 29
 Transmission Gates
 The Transmission Gate uses 4 transistors
(the inverted control signal is needed to
control the pMOS).
 This means that it doesn’t necessarily
reduce the area to implement logic
functions, but in certain cases, very
efficient functions can be easily realized. B  A, if C  '1'

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 30
 Transmission Gate Example
 During a transmission gate transition, both transistors are
on during the operation.
 One transistor passes a “strong signal” with maximum
overdrive, while the other passes a much weaker signal.
 Let’s take a ‘0’ to ‘1’ transition as an example:

N1
Vin Vout
P1

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 31
 Transmission Gate Example
 As usual, we will mark the sources and drains.

VGSn=VDD-Vout
VDSn=VDD-Vout
N1
Vin Vout
P1
VSGp=VDD
VSDp=VDD-Vout

 At the beginning of the transition, Vout=0, so both transistors

are strongly velocity saturated.
 But as the output is charged, the resistance of the nMOS
rises, while the resistance of the pMOS stays relatively
constant.
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 32
 Transmission Gate Example
 At t=0:
I out  I n  I p  kn  VDD  VTn VDSat ,n  0.5VDSat
2
,n   k p VDD VTp  VDSat , p  0.5V 2
DSat , p 
 At t=tpd:
2

I out
 VDD
 kn 
 2



 VTn   k p VDD  VTp VDSat , p  0.5VDSat
2
,p 
VGSn=VDD-Vout
 At Vout=VDD-VTn: VDSn=VDD-Vout
N1


I out  k p VDD  VTp VDS  0.5V 2
DS  Vin
P1
Vout

VSGp=VDD
VSDp=VDD-Vout

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 33
 Resistance of Transmission Gate
30

2.5 V
Rn Rn
Resistance, ohms

20 Rp
2.5 V Vou t

Rp
0V
10
Rn || Rp

0
0.0 1.0 2.0
Vou t , V

Almost constant resistance!

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 34
 Delay of TG Chain
 An interesting question is what happens if we cascade
several Transmission Gates in series.
 So assuming one gate gives tpd=0.69ReqCdTG, we can draw
the chain of gates as an RC chain.
 Given N gates and using the Elmore Delay, we get:
 N  C1 Req  C2  2 Req  C3  3Req  ...  CN  NReq
 N  N  1 
 Req Cd ,TG 1  2  ..  N   Req Cd ,TG  
 2 

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 35
 Delay of TG Chain
 Delay of 16 TGs comes out 2.7 ns (for 0.25um technology)
 The transition (rise time) is slow.

t pd  N 2

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 36
 Optimizing a TG Chain
 To optimize this problem, we will insert a buffer every m
TGs.

 But what is the correct value of m?

 We already know how to optimize this tbuffered
type of problem… 0
 m  m  1   N  m
N
tbuffered  0.69   Req Cd ,TG      1 tbuf
m  2  m 
 N  m  1   N 
 0.69 Req Cd ,TG      1 tbuf
 2  m 
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 37
 Optimizing a TG Chain
 N  m  1   N 
tbuffered  0.69 Req Cd ,TG      1 tbuf
 2  m 
tbuffered
0
m

tbuf
mopt  1.7
CdTG Req
3 t pd  N

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 38
 2-Input MUX
 The 2-input Multiplexer is a Universal gate
that is very commonly used in digital circuits,
especially for signal selection.
F  A S  B  S

 Let’s inspect its implementation

in Standard CMOS:
» PDN: F  A  S  B  S

» PUN: F  A  S  B  S  A  S  B  S   A  S    B  S 

 This implementation requires 10 or 12 transistors:

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 39
 2-Input MUX
 Using Transmission Gates, we can make the
same circuit with only 6 transistors:

F  A S  B  S

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 40
 2-Input XOR
 Another example of an efficient
Transmission Gate is the XOR function.
 This function is very useful, for instance
in parity calculations. F  A B  A  B

 With Standard CMOS:

» PUN: F  A  B  A  B

» PDN: F  A  B  A  B  A  B  A  B   A  B   A  B 

 Here we’ve reached a whopping

12 transistors!

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 41
 2-Input XOR
 With Transmission Gates, we can do it with only 6!

» When B=‘1’, the input stage is a CMOS

inverter and the Transmission Gate is
closed. Hence:
Y  A B
» When B=‘0’, the input stage closes both
transistors, but the Transmission Gate is
now open, so we get:
Y  A B
 Together, we get our XOR function: Y  A  B  A B

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 42
 Last Lecture
 Pass Transistor Logic

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 43
 Last Lecture
 Transmission Gates

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 44
 9.4
9.1 Pass Transistor Logic

9.2 Extending the

PTL Concept

9.3 Transmission Gates

9.4 PTL Logical Effort

Okay, now let’s go way beyond

and figure out

PTL LOGICAL EFFORT

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 45
 PTL Logical Effort

 How do we go about calculating the LE of PTL?

» Let’s take a PTL AND gate. B
» We will arbitrarily size the gate with
minimum transistors for calculation. A W Out
» Now we need to differentiate
B W
between the various inputs,
transitions, and also recognize
what makes up the entire circuit.
 Essentially, we have to recognize that:
» Input A is driven through a Buffer.
» Input B drives a gate.
B! is a different signal on a different path.
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 46
 PTL Logical Effort

 So let’s start with input B (with A=‘1’):

» When B=‘1’’0’ we get: B=0
» The output discharges through
the nMOS, so: W Out
Req  Rmin Rgate Cd , gate 2 2
p   1  W
Cg  B   Cg min Rinv 3Cd ,min 3 3
Cd  2Cd min Rgate Cg , gate 1 1
LE    1 
Rinv 3Cg ,min 3 3

» It looks as if the PTL gate is a great driver!

 But that was only one of numerous transitions…

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 47
 PTL Logical Effort

 Now when B=‘0’’1’: The only relevant

transition is when A=1
» The output charges through the 2W
series connection of the buffer’s A=0 W Out
pMOS and the PTL nMOS:
W W
Req  0.5R p  Rn  2 Rmin Rgate Cd , gate 2 4
p   2 
Cg  B   Cg min Rinv Cd ,min 3 3

Cd  2Cd min Rgate Cg , gate 1 2

LE    2 
Rinv Cg ,min 3 3
* The buffer’s output
was already charged.

» So driving a PTL through the gate input (B) is pretty

good!
Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 48
 PTL Logical Effort

 But what about the diffusion input (A)?

» When B=‘1’ and A=‘0’’1’ we 2W
have the same model, but now A=0 W Out
the input is A.
W W
» Therefore the gate capacitance is that
of an inverter = 3W.
» Plus, the buffer’s capacitance is initially discharged.
Rgate Cd , gate 5
Req  0.5R p  Rn  2 Rmin p   2   10
Rinv Cd ,min 3 3
Cg  A   Cg ,inv  3Cg min Rgate Cg , gate 3
Cd  Cd ,inv  Cout   3  2  Cd min LE    2  2
Rinv Cg ,min 3

» So we get really bad performance.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 49
 PTL Logical Effort

 The opposite transition is similar: 2W

» Now A=‘1’’0’. W Out
A=1
W W
Req  Rn  Rn  2 Rmin
Cg  A   Cg ,inv  3Cg min Rgate Cd , gate 5 10
p   2 
Cd  Cd ,inv  Cout   3  2  Cd min
Rinv Cd ,min 3 3
Rgate Cg , gate 3
LE    2  2
Rinv Cg ,min 3

 So, using a PTL gate through the diffusions is

really bad.

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 50
 PTL Logical Effort

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 51
 Summary
 Pass transistor logic is a low transistor count CMOS
alternative, but:
» It is non-digital, so every few stages we must insert a CMOS gate.
» It suffers from depleted high levels, so we should consider using a
level-restorer.
» It is very asymmetric, so we should carefully analyze each path
before using it.
 However, the concept of a pass transistor can be very
useful:
» We can build special gates (transmission gate, XOR, MUX).
» We can use it as a switch.
» We can build interesting logic families (CPL, GDI, etc.)

Digital Microelectronic Circuits The VLSI Systems Center - BGU Pass Transistor Logic 52