Digital Systems and Computer Organization

4. The comparator compares VAX with the analog input VA. As long as
VAX < VA1 the comparator output stays HIGH. When VAX exceeds VA
by at least an amount = VT ( threshold voltage), the comparator
output goes LOW and stops the process of modifying the register
number. At this point, VAX is a close approximation to VA. The digital
number in the register, which is the digital equivalent of VAX, is also
the approximate digital equivalent of VA1 within the resolution and
accuracy of the system.
5. The control logic activates the end-of-conversion signal, EOC, when
the conversion is complete.

3.3. Digital-Ramp ADC

One of the simplest versions of the general ADC of Fig. 7.7 uses a
Operation procedure of a binary counter as the register and allows the clock to increment the
digital-ramp ADC.
counter one step at a time until VAX ≥ VA. It is called a digital-ramp
ADC because the wave form at VAX is a step-by-step ramp (actually a
staircase) like the one shown in Fig. 7.7. It is also referred to as a
counter-type ADC. Fig. 7.7 is the diagram for a digital-ramp ADC. It
contains a counter, a DAC, an analog comparator, and a control AND
gate. The comparator output serves as the active-LOW end-of-
conversion signal, EOC . If we assume that VA, the analog voltage to be
converted, is positive, the operation proceeds as follows :

1. A START pulse is applied to reset the counter to zero. The HIGH at

START also inhibits clock pulse form passing through the AND gate
into the counter.
2. With all 0’s at its input, the DAC’s output will be VAX = 0V.
3. Since VA > VAX, the comparator output, EOC , will be HIGH.
4. When START returns LOW, the AND gate is enabled and clock
pulses get through to the counter.
5. As the counter advances, the DAC output, VAX, increases one step at
a time as shown in Fig. 7.7.
6. This continues unit VAX reaches a step that exceeds VA by an amount
equal to or greater than VT (typically 10 to 100 µV). At this point,
EOC will go LOW and inhibit the flow of pulses into the counter
and the counter will stop counting.
7. The conversion process is now complete as signaled by the HIGH-to-
LOW transition at EOC , and the contents of the counter are the
digital representation of VA.
8. The counter will hold the digital value until the next START pulse
initiates a new conversion.

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Clock

VA +
EOC
OP amp
-

Comparator START

VA
RESET
VAX
Conversion
complete.
VAX CLOCK counter stops
D/A .
Counter counting
converter
.
.
.
.
EOC

Digital
result tc
Start
Time
(a) (b)

Fig. 7.7 : Digital-ramp ADC.

Problem 8

Assume the following values for the ADC clock frequency = 1 MHz; VT
= 0.1 mV; DAC has F.S. output = 10.23 V and a 10-bit input. Determine
the following values.

Problem 8 and Solution a. The digital equivalent obtained for VA = 3.728 V.

b. The conversion time.
c. The resolution of this converter.

Solution

a. The DAC has a 10-bit input and a 10.23-V F.S. output. Thus, the
number of total possible steps is 210 - 1 = 1023, and so the step size is
10.23V
= 10mV
1023

This means that VAX increases in steps of 10 mV as the counter counts

up from zero. Since VA = 3.728 V and VT = 0.1 mV, VAX has to reach
3.7281 V or more before the comparator switches LOW. This will
require.

3.7281V
= 372.81 = 373 steps
10mV

At the end of the conversion, then, the counter will bold the binary
equivalent of 373, which is 0101110101. This is the desired digital
equivalent of VA = 3.728 V, as produced by this ADC.

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b. Three hundred seventy-three steps were required to complete the

conversion. Thus, 373 clock pulses occurred at the rate of one per
microsecond. This gives a total conversion time of 373 µs.
c. The resolution of this converter is equal to step size of the DAC,
which is 10mV. In percent it is 1/1023 × 100% ≈ 0.1%.

Problem 9

For the same ADC of problem 8 determine the approximate range of

Problem 9 and Solution analog input voltages that will produce the same digital result of
01011101012 = 37310.

Solution

Table 7.2 shows the ideal DAC output voltage, VAX, for several of the
steps on and around the 373rd. If VA is slightly smaller than 3.72 V (by
an amount < VT),

Step VAX (V)

371 3.71
372 3.72
373 3.73
374 3.74
375 3.75
Table 7.2

Then EOC won’t go LOW when VAX reaches the 3.72-V step, but will
go LOW on the 3.73-V step. If VA is slightly smaller than 3.73 V (by an
amount < VT), then EOC won’t go LOW until VAX reaches the 3.74-V
step. Thus, as long as VA is between approximately 3.72 V and 3.73-V,
EOC will go LOW when VAX reaches the 3.73-V step. The exact range
of VA values is

3.72 V - VT to 3.73 V - VT

but since VT is so small, we can simply say that the range is

approximately 3.72 V to 3.73 V - a range equal to 10 mV, the DAC’s
resolution.

3.4. A/D Resolution and Accuracy

Resolution of the ADC is equal to the resolution of the DAC that it

contains. The DAC output voltage VAX is a staircase waveform that goes
Resolution of the ADC is
up in discrete steps until it exceeds VA. Thus, VAX is an approximation to
equal to the resolution of
the DAC that it contains.
the value of VA, and the best we can expect is that VAX is within 10 mV
of VA if the resolution (step size) is 10 mV. We can think of the
resolution as being a built-in error that is often referred to as

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quantization error. This quantization error, can be reduced by increasing

the number of bits in the counter and DAC.

Problem 10

Acertain 8-bit ADC hs a full-scale input of 2.55 V (i.e., VA = 2.55 V

produces a digital output of 11111111). It has a specified error of 0.1%
Problem 10 and Solution F.S. Determine the maximum amount by which the VAX output can differ
from the analog input.

Solution

The step size is 2.55 V/ (28 - 1), which is exactly 10 mV. This means that
even if the DAC has no inaccuracies, the VAX output could be off by as
much as 10 mV because VAX. can change only in 10-mV steps; this is the
quantization error. The specified error of 0.1% F.S. is 0.1% × 2.55 V =
2.55 mV. This means that the VAX value can be off by as much as 2.55
mV because of component inaccuracies. Thus, the total possible error
could be as much as 10 mV + 2.55 mV = 12.55 mV.

3.5. Conversion Time, TC

The conversion time is the time interval between the end of the START
pulse and the activation of the EOC output. The counter starts
counting from zero and counts up until VAX exceeds VA, at which point
Conversion Time, TC EOC goes LOW to end the conversion process. It should be clear that
the value of conversion time, to, depends on VA. A larger value will
require more steps before the staircase voltage exceeds VA.

The maximum conversion time will occur when VA is just below full
scale so that VAX has to go to the last step to activate EOC . For an N-bit
converter this will be

tc (max) = 2N - 1 clock cycles

Sometimes, average conversion time is specified; it is half of the

maximum conversion time.

tc (max)
tc ( avg ) = ≈ 2 N − 1 clock cyles
2

The major disadvantage of the digital-ramp method is that conversion

time essentially doubles for each bit that is added to the counter, so that
resolution can be improved only at the cost of a longer tc. Applications,

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however, the relative simplicity of the digital-ramp converter is an

advantage over the more complex, higher-speed ADCs.

3.6. Applications

Almost any measurable quantity present as a voltage can be digitized by

an A/D converter and displayed. A/D converters are the heart of digital
voltmeters and digital MultiMate’s. Analog voice signals are converted
Applications to digital form for transmission over long distances. At their destination
they are reconverted to analog. In digital audio record- the analog audio
signal produced by a microphone is digitized (using an ADC), then
stored on some medium such as magnetic tope, magnetic disk or optical
disk. Later the stored data are played back by sending them to a DAC to
reconstruct the analog signal, which is fed to the amplifier and speaker
system to produce the recorded sound.

3.7. Exercise

3.7.1. Multiple choice question

a) The number of total steps of a 9-bit ADC is,

i) 255
ii) 256
iii) 511
iv) 512.

3.7.2. Questions for short answers

a) What do you know about quantization error?

b) Define conversion time.
c) What is the major disadvantage of the digital ramp type ADC?
d) What is the function of the comparator in the ADC?
e) What is the function of the comparator in the ADC?
f) Where is the approximate digital equivalent of VA when the
conversion is complete?
g) What is the function of the EOC signal?

3.7.3. Analytical question

a) Draw digital ramp ADC and write down its operation.

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