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Question Paper Code:: Reg. No.

The document is a question paper for a Digital Systems exam that contains 15 multiple choice and short answer questions covering various topics in digital logic design including: 1) Boolean algebra, logic minimization techniques like minterm expansion. 2) Types of memory like DRAM and differences between EPROM and EEPROM. 3) Design of combinational and sequential logic circuits like decoders, counters. 4) Hazards in sequential circuits and conditions for reversibility. 5) Implementation of functions using multiplexers, decoders and other gates.

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Monica Naresh
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213 views2 pages

Question Paper Code:: Reg. No.

The document is a question paper for a Digital Systems exam that contains 15 multiple choice and short answer questions covering various topics in digital logic design including: 1) Boolean algebra, logic minimization techniques like minterm expansion. 2) Types of memory like DRAM and differences between EPROM and EEPROM. 3) Design of combinational and sequential logic circuits like decoders, counters. 4) Hazards in sequential circuits and conditions for reversibility. 5) Implementation of functions using multiplexers, decoders and other gates.

Uploaded by

Monica Naresh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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*X64251*

Reg. No. :

Question Paper Code : X64251


B.E./B.Tech. Degree Examinations, NOVEMBER/DECEMBER 2020
Third Semester
Computer Science and Engineering
CS 232 – Digital Systems
(Regulations 2001)

Time : Three Hours Maximum : 100 Marks

Answer all questions


Part – A (10×2=20 Marks)
1. State a single rule, which can be used to form the complement of a Boolean
expression in one step.
2. Find the minterm expansion of f(a, b, c, d) = a′ (b′ + d) + acd′.
3. Write down the limitations of DRAM.
4. Differentiate EPROM and EEPROM.
5. Implement the function S(x, y, z) = S(1, 2, 4, 7) using a decoder.
6. What is the difference between sequential and combinational circuits ? Give
examples.
7. What is meant by the term edge triggered ?
8. What is the output frequency of a decade counter that is clocked from a 50 KHz
signal ?
9. What is static 0 hazard ?
10. When is a sequential machine said to be reversible ?
Part – B (5×16=80 Marks)
11. a) Find all of the minimum sum of products and all minimum products of sum
solutions and also indicate which solutions are equal for
g(w, x, y, z) = Σm(1, 3, 4, 6, 11) + Σd(0, 8, 10, 12, 13) (16)
(OR)
b) Determine the prime implicants and essential prime implicants of the function.
F(w, x, y, z) = Σm (1, 4, 6, 7, 8, 9, 10, 11, 15) using tabulation method. (16)
X64251 *X64251*

12. a) i) Design a network with four inputs and three outputs which realizes the
following functions.
F1(a, b, c, d) = Σm (11, 12, 13, 14, 15)
F2(a, b, c, d) = Σm (3, 7, 11, 12, 13, 15)
F3(a, b, c, d) = Σm (3, 7, 12, 13, 14, 15) (8)
ii) Explain the operation of the tristate TTL inverter. (8)
(OR)
b) i) Design a combinational logic circuit that will generate the square of all
the combinations of a 3-bit binary number. (8)
ii) Find the reduced POS form of the following equation
F(a, b, c, d) = Σm(1, 3, 7, 11, 15) + d(0, 2, 5). Implement using NAND logic. (8)

13. a) i) Design and implement a full adder with two half adders and an OR gate. (8)
ii) Design a combinational circuit with three inputs and one output. The
output is 1, when the binary value of the inputs is less than 3. The output
is 0 otherwise. (8)
(OR)
b) i) Design and implement a four bit magnitude comparator. (8)
ii) Implement the function F(A, B, C, D) = Σ(0, 1, 3, 4, 8, 9, 15) using a
multiplexer. (8)

14. a) Explain the operation of 4-bit binary ripple counter. (16)


(OR)
b) Explain the operation of BCD counter. (16)

15. a) i) Determine if there is any race condition in the following transition table : (8)

00 01 11 10
00 00 , 0 00 , 0 11, 1 01, -
01 00, - 11, - 01 , 0 01 , 0
11 00, - 11 , 1 11 , 1 01, -
10 - - - -
ii) State two rules of thumb for getting reasonably good state assignment. (8)
(OR)
b) i) Consider asynchronous sequential circuits with pulse inputs, state the
two restrictions that must be placed on the duration of the input pulses. (6)
ii) Design a static hazard free two level AND-OR gate network to implement
the switching function F = Σ(1, 3, 4, 5). (10)
–––––––––––––

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