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Term Project Proposal: Capital University of Science & Technology, Islamabad

The document is a term project proposal for an electrical engineering course. It proposes developing a stopwatch and countdown timer with a seven segment display interface using an FPGA. The project objectives are to create a stopwatch, timer, and seven segment display, and include set mode and up/down buttons to adjust between modes. A counter module will be implemented in HDL to count up and down, with the output displayed on a seven segment display using a BCD decoder. The final module will be tested on an FPGA.

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Hassham Ali
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20 views2 pages

Term Project Proposal: Capital University of Science & Technology, Islamabad

The document is a term project proposal for an electrical engineering course. It proposes developing a stopwatch and countdown timer with a seven segment display interface using an FPGA. The project objectives are to create a stopwatch, timer, and seven segment display, and include set mode and up/down buttons to adjust between modes. A counter module will be implemented in HDL to count up and down, with the output displayed on a seven segment display using a BCD decoder. The final module will be tested on an FPGA.

Uploaded by

Hassham Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Capital University of Science & Technology,

Islamabad

Term Project Proposal


Electrical Engineering Department

Project Title
STOP WATCH ,COUNTDOWN TIMER WITH SEVEN SEGMENT DISPLAY INTERFACE
Course Name
ASIC DESIGN AND FPGA
S# Student Name Registration Number
1
SYED HASSHAM ALI BEE173071
2
FARAKH ALI BEE173096
3
ATIF SADIQ BEE173111

Project Idea

The design and development of field programmable gate array based digital stopwatch with
additional feature of timer. The main top module consists of clock divider module, counter
module, BCD decoder module and 7-segment display module and user interface like reset, start,
stop, hold, selection button etc.

Project Objectives

The objectives of the project are:


i. Stop watch, countdown timer and 7-segment display
ii. Set mode and up down buttons to move between the modes and adjust accordingly
Problem Statement

A counter module implementation in HDL that can count in both was up and down. The counter
module run on the lower clock and the output of the counter will be displayed on the 7-segment
display using BCD decoder. The final module will be tested on the FPGA using .bit file.
Project Block Diagram

Student 1 Sig.

Student 2 Sig.

Student 3 Sig.

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