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Assignment 2 Solutions

This is the assignment work of b.tech 3rd year in electronics engineering branch. And the topic on which the assignment based is data communication network.

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Yogendra Singh Rajpoot
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77 views5 pages

Assignment 2 Solutions

This is the assignment work of b.tech 3rd year in electronics engineering branch. And the topic on which the assignment based is data communication network.

Uploaded by

Yogendra Singh Rajpoot
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment - 2 Solutions

(Q 2.1)
Ans: d) 1.036 V

Apply KVL in the loop as shown in figure

⇒ 12 = 10 IE + VEB + 100 IB

⇒ 12 = 10 (IB + IC ) + VEB + 100 IB

⇒ 12 = 10 (IB + βIB ) + VEB + 100 IB

⇒ 12 = 10 (100 IB ) + VEB + 100 IB [∵𝝱=99

⇒ 1100 IB = 12 – VEB

⇒ 1100 IB = 11.4 [∵ 𝑉𝐸𝐵 ≈ 0.6V


11.4
⇒ IB = mA
1100

11.4
∴ VB = 100k ∙ IB = 100 × = 1.036 V
1100
________________________________________________________________

(Q 2.2)
Ans: a) –1.74 V

From the figure of the circuit given in the question,

VC = 10k ∙ IC – 12
11.4
VC = 10 × 99 × – 12 [∵ 𝝱IB = IC
1100

⇒ 𝐕𝐂 = – 1.74 V

(Q 2.3)
Ans: e) 12.66
∂VBE VBE2 − VBE1
Input resistance, rπ = =
∂IB IB2 − IB1

Here, VBE1 and VBE2 are chosen w.r.t. VBE = 0.535 V


0.54 − 0.53
⇒ rπ = (2.4 ≈ 𝟏𝟐. 𝟔𝟔 𝐤𝛀
−1.61) µ

(Q 2.4)
Ans: f) 7.6 mS
∂IC IC2 – IC1
Transconductance, g m = =
∂VBE VBE2 − VBE1

(0.22 − 0.144) m
⇒ gm = = 7.6 mS
0.52 − 0.51

(Q 2.5)
Ans: b) and c)

(Q 2.6)
Ans: b) 24

From the circuit, VG = 1V

From circuit, VD = ISD . R ------------------- 1

To maintain MOS in saturation (i.e, channel is pinched off),

VDG ≤ ǀ Vthp ǀ

⇒ VD – VG ≤ ǀ Vthp ǀ

⇒ ISD ∙ R – VG ≤ ǀ Vthp ǀ [∵ Eq. (1), VD = ISD . R

⇒ ISD ∙ R ≤ VG + ǀ Vthp ǀ
VG + ǀ Vthp ǀ βP 2
⇒R≤ βP 2 [∵ MOS is in saturation, then ISD = (VSG − Vthp )
(VSG − Vthp) 2
2

1+0.5
⇒R≤ 0.5 m
(2 −1 −0.5)2
2

1.5 × 2000
⇒R≤ (0.5)3

⇒ R ≤ 24 kΩ i. e, 𝐑 𝐦𝐚𝐱 = 𝟐𝟒 𝐤𝛀

(Q 2.7)
Ans: d) 11
Assume initially, MOSFET is in saturation region.

Voltage across resistor, R is VR = IDS ∙18k = 100µ∙18k = 1.8 V

⇒ VDS = 2 – VR = 0.2V

2ID
⇒ VGS = √ + Vthn
βn

2 X 100 µ
⇒ VGS = √ + 0.5 = 0.9472 V
1m

∴ VGS – Vthn > VDS i.e., MOSFET is not in saturation region as we assumed initially.

Hence, MOSFET should be operated in triode region.


VDS
⇒ IDS = βn (VGS − Vthn − ) VDS
2

0.2
⇒ 100 µ = 1m (VGS − 0.5 − ) 0.2
2

1
⇒ + 0.5 + 0.1 = VGS
2

⇒ VGS = 1.1 V

∴ VGS – Vth > VDS ⇒ Condition is satisfied for triode region. So MOSFET is operating
in triode region only.
R2
∴ VGS = 1.1 = 2
R1 + R2

R2
⇒ 1.1 = 2
9 + R2

⇒ 9.9 + 1.1 R 2 = 2R 2
9.9
⇒ R2 = = 11 kΩ
0.9

(Q 2.8)
Ans: a) 100 kΩ
VA VA
Output resistance, ro = =
Ic β IB

VA 48
⇒ ro = 1 − 0.7 = 0.3 = 100 kΩ
β( ) 120 ( )
75 kΩ 75k
(Q 2.9)
Ans: e) 673.44 mV

C I
VEB = VT × ln ( (C) )
IS

0.5m
VEB = 25m × ln ( )
10−12 m

𝐕𝐄𝐁 = 673.44 mV

(Q 2.10)
Ans: d) 25 kΩ

From Circuit,
4 − VGS βn
= 120 µA = (VGS − Vth )2
R 2

⇒ 120µ × 2 = 120µ × 8 (VGS − 0.5)2


1
⇒ VGS = + 0.5 = 1V
√4

4 −1 1
∴R= = = 25 kΩ
120µ 40µ

(Q 2.11)
Ans: c) 0.5 V to 1.4 V

From the given circuit, VGSn = VSGp = 0.9 V

VDSn (min) = VDSn – Vthn = 0.9 – 0.4

⇒ VDn (min) = 0.5 V

Similarly, VSDp (min) = VSGp – ǀ Vthp ǀ = 0.9 – 0.5

⇒ VSDp (min) = 0.4 V

⇒ VDP (max) = VSp – 0.4 =1.8 – 0.4 = 1.4 V

i.e, VO(DC) = VDn (min) to VDp (max)

∴ 𝐕𝐎(𝐃𝐂) = 0.5 V to 1.4 V


Here, VDn (min) = 0.5V i.e, the minimum voltage at drain of NMOS transistor to
maintain NMOS in saturation region. If VD < 0.5 V then NMOS will go to triode
region but not a problem to PMOS (i.e., PMOS is in saturation region for VD < 0.5 V
also). Hence, 𝐕𝐃 ≥ 0.5V to maintain NMOS in saturation. As VD increases towards
Vdd (here, Vdd is 1.8 V), NMOS may not face any problem (i.e., NMOS operates in
saturation region for VD ≥ 0.5 V), but for PMOS if VD > 1.4V then PMOS goes to
triode region. Hence, 𝐕𝐃 ≤ 1.4V to maintain PMOS in saturation.
(Q 2.12)
Ans: a) 14 µA

From circuit,
3 − VCE (Sat)
IC = = βIβ
2K

3−0.2
⇒ IB = = 14µA
200K

(Q 2.13)
Ans: b) 3.1 mA
α
Given, α = 0.99 ⇒ 𝝱 = = 99
1−α

Apply KVL around the loop – 1, then

10 = 1k (IB + IC ) + 97k ∙IB + 1k ∙ IE + VBE

⇒ 10 = 2k (IB + IC ) + 97k ∙ IB + 0.7

9.3 = 2k ∙ IC + 99k ∙ IB
I
⇒ 9.3 = 2k ∙ IC + 99k( C )
99

9.3 = 3k ∙ IC

⇒ IC = 3.1 mA

********* THE END **********

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