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Advanced UVM: Architecting A UVM Testbench

The document discusses the architectural design of a UVM testbench. It describes various components of a UVM testbench including agents, environments, tests, and phases. Agents contain interfaces, monitors, drivers, and sequencers. Tests and environments control stimulus generation and coverage collection.

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manchurico
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
711 views

Advanced UVM: Architecting A UVM Testbench

The document discusses the architectural design of a UVM testbench. It describes various components of a UVM testbench including agents, environments, tests, and phases. Agents contain interfaces, monitors, drivers, and sequencers. Tests and environments control stimulus generation and coverage collection.

Uploaded by

manchurico
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced UVM

Architecting a UVM Testbench


Tom Fitzpatrick
Strategic Verification Architect
UVM Testbench - Architectural Design
For Each Interface:
• How does the interface work?
• What information is transferred?
• Transaction variants? DUT
• Uni/bidirectional? Pipelined? APB

SPI
For the Design: IRQ I/F

• What does it do?


• What are the use cases?
• Which test cases are required?
• What type of stimulus scenarios are required?
• What represents correct behavior?
• What kind of functional coverage do I need?
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UVM Structural Building Block: Agent

Analysis port: Send Detects transactions


transactions for checking on the interface

- Contains virtual Agent


interface handle One per
Configuration interface
- Pass information Monitor
on how agent Object
should behave
Sequencer
DUT
Sends stimulus Driver
seq_item
to Driver

Stimulus Converts seq_item to pin wiggles


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UVM Architecture: Block-Level Env/Test

Test
Test
Test
Test
Test
Test
Test
Environment
Coverage
Test
seq Collector
Seqs

Agent
Bkgrnd
seq Configuration
Seqs Object
Monitor DUT
Env Config Config Sequencer
A Config A Config Driver

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UVM Architecture: Block-Level Env/Test
Test
Test
Test
Environment

Agent2
Test Configuration
Monitor
Seqs Environment Object

Coverage Sequencer
Collector Driver

Score

Agent1
Bkgrnd Configuration
Seqs Monitor
Object

Env Config Config Sequencer DUT


A2 Config A2 Config Driver
A1 Config A1 Config

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UVM Architecture: Integration-Level Env/Test
Test
Test
Test
Environment

Agent2
Test Configuration
Seqs Object
Monitor DUT
Score
Coverage Sequencer
Collector Driver

Score

Agent1
Bkgrnd Configuration
Seqs Monitor
Object

Env Config Config Sequencer DUT


E2 Config E2 Config
A2 Driver
E1 Config E1 Config
A1

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Introducing Phasing
UVM execution is controlled by phases
<task/func> phasename_phase(uvm_phase phase);
build
Build is called top-down
connect
• Facilitates hierarchical instantiation and
end_of_elab
configuration
start_of_sim
All others called bottom-up
run_phase() is the only task run
• All run_phase methods execute in parallel (task)
Don’t use alternate run-time phases extract
check
report
final

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Building the Agent
class if_agent extends uvm_component;
`uvm_component_utils(if_agent)
if_agent_cfg cfg;
if_driver driver;
if_sequencer seqr;
if_monitor monitor;
uvm_analysis_port #(if_txn) ap;

function void new(string name, uvm_component parent);


super.new(name, parent); Agent
endfunction Configuration
Object Monitor

Sequencer
endclass Driver DUT

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Agent: The Build Phase
class if_agent extends uvm_component;
function void build_phase(uvm_phase phase);
if(!uvm_config_db #(if_agent_cfg)::get(this,“”,“cfg”, cfg))
`uvm_fatal(“Config fatal”,“Can’t get config”);
if(cfg.active == UVM_ACTIVE) begin
seqr = if_sequencer::type_id::create(“seqr”,this);
driver = if_driver::type_id::create(“driver”,this);
end
monitor = if_monitor::type_id::create(“monitor”,this);
… Agent
endfunction Configuration
Object Monitor

endclass
Sequencer
Driver DUT

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Agent: The Connect Phase
class if_agent extends uvm_component;
function void connect_phase(uvm_phase phase);
monitor.vif = cfg.vif;
ap = m_monitor.ap;
if(cfg.active == UVM_ACTIVE) begin
driver.seq_item_port.connect(seqr.seq_item_export);
driver.vif = cfg.vif;
end
…
endfunction Agent

Configuration
Object Monitor

endclass
Sequencer
Driver DUT

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The Environment: Declaration
class my_env extends uvm_env;
`uvm_component_utils(my_env)
if1_agent agent1;
if2_agent agent2;
my_score score;
my_cov cov;
my_env_config cfg;

function new(string name, uvm_component); Environment

super.new(name, parent); Agent2

endfunction
Environment
Coverage
Collector

Score

Agent1

endclass Config
A2 Config
DUT
A1 Config

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The Environment: Build_phase
class my_env extends uvm_env;
function void build_phase(uvm_phase phase);
if(!uvm_config_db #( my_env_config )::get( this , "",
“my_env_config" , cfg ) begin
`uvm_fatal("build_phase", "unable to get my_env_config")
end
uvm_config_db #(if1_agent_config)::set(this , "m_agent1*",
"agent1_config", cfg.agent1_cfg );
agent1 = if1_agent::type_id::create( Environment

"agent1", this); Agent2

…
Environment
Coverage
Collector

endfunction:build_phase Score

endclass
Agent1

Config
A2 Config
DUT
A1 Config

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The Environment: Build_phase
class my_env extends uvm_env;
function void build_phase(uvm_phase phase);
…
uvm_config_db #(if2_agent_config)::set(this , "agent2*",
“if2_agent_config", m_cfg. agent2_cfg );
agent2 = if2_agent2::type_id::create("agent2", this);
if(cfg.has_my_score)
score = my_score::type_id::create("score", this);
if(cfg.has_coverage) Environment

cov = my_cov::type_id::create(“cov”, Agent2

this);
Environment
Coverage
Collector

endfunction:build_phase Score

endclass
Agent1

Config
A2 Config
DUT
A1 Config

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The Environment: Connect_phase
class my_env extends uvm_env;
function void connect_phase(uvm_phase phase);
if(cfg.has_my_score) begin
agent1.ap.connect(score.apb.analysis_export);
agent2.ap.connect(score.spi.analysis_export);
end
if(cfg.has_coverage)
agent1.ap.connect(cov.analysis_export);
endfunction: connect_phase Environment

Agent2

Environment
Coverage
Collector

Score

endclass
Agent1

Config
A2 Config
DUT
A1 Config

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The Base Test
class my_test_base extends uvm_test;
`uvm_component_utils(my_test_base)

my_env env;
my_agent1_config a1_cfg;
my_agent2_config a2_cfg;
my_env_cfg cfg; Config
A2 Config
A1 Config

function new(string name, uvm_component); Environment

super.new(name, parent); Agent2

endfunction
Environment
Coverage
Collector

Score

endclass
Agent1

Config
A2 Config
DUT
A1 Config

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The Base Test: Build_phase
class my_test_base extends uvm_test;
`uvm_component_utils(my_test_base)

function void build_phase( uvm_phase phase );


cfg = my_env_cfg::type_id::create(“cfg”);
configure_env();// setup configuration for env and agents
uvm_config_db#(my_env_cfg)::set(this,"*",
“my_env_config", cfg);
Config
A2 Config
A1 Config

env = my_env::type_id::create("env", Environment

this); Agent2

endfunction
Environment
Coverage
Collector

Score

endclass
Agent1

Config
A2 Config
DUT
A1 Config

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The Actual Test
class my_test extends uvm_test_base;
`uvm_component_utils(my_test)
my_virt_seq m_vseq;

function new(string name, uvm_component parent);


super.new(name, parent);
endfunction
Config
A2 Config vseq
A1 Config

function void build_phase(uvm_phase phase);


super.build_phase(phase); Agent2

endfunction Coverage
Collector

endclass Score

Agent1

Config
A2 Config
DUT
A1 Config

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The Actual Test
class my_test extends uvm_test_base;
`uvm_component_utils(my_test)

task run_phase(uvm_phase phase);


vseq = my_virt_seq::type_id::create(“vseq”);
phase.raise_objection(this, “Starting virtual sequence”);
vseq.start();
phase.drop_objection(this,
Config
vseq
seq2
seq1 A2 Config
A1 Config

“Finished virtual sequence”); Environment

endtask Agent2

Environment
Coverage
Collector

Score

endclass
Agent1

Config
A2 Config
DUT
A1 Config

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Architecture Summary
Agents are protocol-specific
Environments define the testbench topology
• Which agents and how many
• Other components
Base Test instantiates env and handles default configuration
Extend the base test to define your test
• Tweek configuration and/or factory settings
• Start (virtual) sequence(s)
• Test handles phase objections
Keep to basic phasing

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Advanced UVM
Architecting a UVM Testbench
Tom Fitzpatrick
Strategic Verification Architect

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