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Unit 1-MCQ

This document contains 30 multiple choice questions about operational features of Peripheral Interface Controllers (PIC), including brown-out reset, watchdog timer, register banks, addressing modes, oscillator types, and other specifications of PIC microcontrollers. The questions cover topics like clock cycles, reset triggers, register usage, oscillator outputs, and clocking mechanisms.

Uploaded by

Shubham Marshettiwar
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© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
210 views

Unit 1-MCQ

This document contains 30 multiple choice questions about operational features of Peripheral Interface Controllers (PIC), including brown-out reset, watchdog timer, register banks, addressing modes, oscillator types, and other specifications of PIC microcontrollers. The questions cover topics like clock cycles, reset triggers, register usage, oscillator outputs, and clocking mechanisms.

Uploaded by

Shubham Marshettiwar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Unit 1:

MCQ

1) Which operational feature of PIC allows it to reset especially when the


power supply drops the voltage below 4V?

a) Built-in Power-on-reset
b) Brown-out reset
c) Both a & b
d) None of the above

Ans: b) : Brown-out reset

2) How many clock pulses are confined by each machine cycle of


Peripheral-Interface Controllers?
a) 4
b) 8
c) 12
d) 16
Ans: a). 4

3) Which timer/s possess an ability to prevent an endless loop hanging


condition of PIC along with its own on-chip RC oscillator by
contributing to its reliable operation?
a) Power-Up Timer (PWRT)
b) Oscillator Start-Up Timer (OST)
c) Watchdog Timer (WDT)
d) All of the above
Ans:C): Watchdog Timer (WDT)

4) How many RPO status bits are required for the selection of two register
banks ?
a) 1
b) 2
c) 8
d) 16
Ans: a) 1
Which statement is precise in relation to FSR, INDF and indirect addressing
mode?
a. Address byte must be written in FSR before executing INDF instruction in
indirect addressing mode
b. Address byte must be written in FSR after executing INDF instruction in
indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of
INDF instruction in indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any
instruction in indirect addressing mode

a) Only A
b) Only B
c) Only A & B
d) A & D
Ans: a). Only A

5) Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a) High
b) Low
c) Moderate
d) All of the above
Ans: b):Low

6) Generation of Power-on-reset pulse can occur only after __________


a) the detection of increment in VDD from 1.5 V to 2.1 V
b) the detection of decrement in VDD from 2.1 V to 1.5 V
c) the detection of variable time delay on power up mode
d) the detection of current limiting factor

Ans: a)the detection of increment in VDD from 1.5 V to 2.1 V

7) Which kind of mode is favourable for MCLR pin for indulging in reset
operations?
a) Normal mode
b) Sleep mode
c) Power-down mode
d) Any flexible mode
Ans: b).Sleep mode

8) Which program location is allocated to the program counter by the reset


function in Power-on-Reset (POR) action modes?
a) Initial address
b) Middle address
c) Final address
d) At any address reliable for reset operations
Ans: a) Initial address
9) Which crucial feature/function of Brown-Out-Reset (BOR) makes the
PIC to be completely unique and distinct from other microcontrollers?
a) It can reset the PIC automatically in running condition
b) It can reset the PIC even when the supply voltage increases above 4V
c) It can reset the PIC without enabling the power-up timer
d) All of the above
Ans: a) It can reset the PIC automatically in running condition

10) What happens when the supply voltage falls below 4V during the
power-up timer delay of 72ms in PIC?
a) CPU resets PIC once again in BOR mode
b) BOR reset mode gets disabled
c) PIC does not remain in BOR mode until the voltage increases irrespective
of stability
d) Power-up timer kills 72ms more again
Ans: a)CPU resets PIC once again in BOR mode

11) What output is generated by OSC2 pin in PIC oscillator comprising


RC components for sychronizing the peripherals with PIC
microcontroller?
a) (1/2) x frequency of OSC1
b) (1/4) x frequency of OSC1
c) (1/8) x frequency of OSC1
d) (1/16) x frequency of OSC1
Ans: c) (1/8) x frequency of OSC1

12) Which form of clocking mechanism is highly efficient and reliable for
crystal or ceramic clock sources for operating at the range of 5- 200 kHz
in PIC?
a) RC
b) LP (Low-Power Clocking)
c) XT
d) HS (High Speed)
Ans: b) LP (Low-Power Clocking)

13) Which significant feature/s of crystal source contribute/s to its


maximum predilection and utility as compared to other clock sources?
a) High accuracy
b) Proficiency in time generation
c) Applicability in real-time operations
d) All of the above
Ans: d) All of the above
14) What is the executable frequency range of High speed (HS) clocking
method by using cystal/ ceramic/ resonator or any other external clock
source?
a) 0-4 MHz
b) 5-200 KHz
c) 100kHz- 4 MHZ
d) 4-20 MHz
Ans: d) 4-20 MHz

15) How many bits are utilized by the instruction of direct addressing
mode in order to address the register files in PIC?
a) 2
b) 5
c) 7
d) 8
Ans: c) 7

16) Which registers are adopted by CPU and peripheral modules so as to


control and handle the operation of device inhibited in RFS?
a) General Purpose Register
b) Special Purpose Register
c) Special Function Registers
d) All of the above
Ans: c) Special Function Registers

17 ) What is the execution speed of instructions in PIC especially while


operating at the maximum value of clock rate?
0.1 μs
0.2 μs
0.4 μs
0.8 μs
Ans: 0.2μs

18)The PIC 18 uses the last bank for the SFRs.


a) True
b) False
Ans: a) True

19)The PIC 18 uses a total o f - - - - - bytes for each bank.


a) 128 byte
b) 256byte
c) 16 byte
d) 8 bit

Ans: b) 256 byte

20)The first 128 bytes of RAM in the PIC18 are used for the access
bank.
a) True
b) False
Ans: a) True
21)The instruction "MOVWF Ox40" uses which addressing mode?
a) Direct Addressing Mode
b) Immediate Addressing Mode
c) Index ROM
d) Register indirect Addressing Mode
Ans: b) Immediate Addressing Mode

22)Which registers are allowed to be used for register ind irect


addressing mod e if the data is in the data RAM file register.
a) FSR
b) SFR
c) WREG
d) INDF
Ans: d) INDF

23)In PIC 18, the WREG register is not part of the SFR.
a) True
b) False
Ans: a)True
24)Which pin is used to reset the PIC18F458 chip?
a) MCLR
b) Vcc
c) Vdd
d) OSC1
Ans. a) MCLR

25)MCLR is an active- pin.


a) Low
b) High

Ans: a) Low

26)How many Vdd and Gnd pins are in the PIC 18F458 chip?
a) 3 pins
b) 4 pins
c) 2 pins
d) 1 pin
Ans: c):2 pin

27)Upon pow er-up, the power-up timer keeps the CPU in the reset state
until the voltage source is stable.
a) True b) false.
Ans: a)True
28)The configuration registers are located within the ROM program
address space.
a) True b) false.
Ans:
29)The high er the clock frequency for the system, the lower the
power dissipation.
a) True b) false.
Ans:
30)If we have the statement BORV = 42 in a given source code, what is
the lowest Vdd voltage level at which the CPU goes i nto the reset state?
a) 4.5 V
b) 4.2 V
c) 2.7 V
d) 2.0 V
Ans: b) 4.2V

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