Practice Exam with Solutions |

Introduction to Digital System

Design | ECE 27000
Digital Systems Design
Purdue University
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ECE 270 Outcome 2 Assessment -1- Practice Exam / Solution
______________________________________________________________________________
OUTCOME #2: “An ability to map and minimize Boolean functions as well as represent
them in various standard forms.”
Multiple Choice – select the single most appropriate response for each question.

Note that none of the above MAY be a VALID ANSWER.

Place answers on the supplied BUBBLE SHEET only – nothing
written here will be graded. Please REATTACH your completed
bubble sheet to this document and TURN BOTH IN TOGETHER.

1. The expression (X+Y)·(X+Z) = X + Y·Z is an example of:

(A) commutitivity
(B) associativity
(C) distributivity
(D) consensus
(E) none of the above

2. The fact that any combinational logic circuit can be realized using only 2-input
NAND gates (or, using only 2-input NOR gates) is called:
(A) DeMorgan’s Law
(B) logical completeness
(C) perfect induction
(D) logical equivalence
(E) none of the above

3. If the function F(X,Y,Z) is represented by the ON SET ∑X,Y,Z(0,3,5,6), then the

complement of this function F′′(X,Y,Z) is represented by the ON SET:
(A) ∑X,Y,Z(0,3,5,6)
(B) ∑X,Y,Z(1,2,4,7)
(C) ∑X,Y,Z(1,2,4,6)
(D) ∑X,Y,Z(1,3,5,7)
(E) none of the above

4. If the function F(X,Y,Z) is represented by the ON SET ∑X,Y,Z(0,3,5,6), then the dual
of this function FD(X,Y,Z) is represented by the ON SET:
(A) ∑X,Y,Z(0,3,5,6)
(B) ∑X,Y,Z(1,2,4,7)
(C) ∑X,Y,Z(1,2,4,6)
(D) ∑X,Y,Z(1,3,5,7)
(E) none of the above

© 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means.

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ECE 270 Outcome 2 Assessment -2- Practice Exam / Solution
______________________________________________________________________________
5. The XOR property listed below that is NOT true is:
(A) X ⊕ 0 = X
(B) X ⊕ 1 = X′
(C) X ⊕ X = X
(D) X ⊕ X′ = 1
(E) none of the above

6. A NOR gate is logically equivalent to:

(A) an AND gate with inverted inputs
(B) an OR gate with inverted inputs
(C) a NAND gate with inverted inputs
(D) a NOR gate with inverted inputs
(E) none of the above

7. A circuit consisting of a level of NOR gates followed by a level of AND gates is

logically equivalent to:
2
(A) a multi-input OR gate 3
1

(B) a multi-input AND gate 2

1
(C) a multi-input NOR gate 2
3

1
(D) a multi-input NAND gate 3

(E) none of the above

8. The circuit shown exhibits the following type of hazard when its input, X,
transitions from low-to-high:
(A) a static-zero hazard
2 1 2
(B) a static-one hazard X 1 Y
(C) a dynamic hazard 3

(D) a consensus hazard

(E) none of the above

______________________________________________________________________
The following K-map applies to questions 10 through 12:

W′′ W
9. The number of prime implicants is:
0 1 0 0 Z′′
(A) 1 (B) 2 (C) 3 (D) 4 (E) 5
Y′′
0 1 1 1
10. The number of essential prime implicants is:
Z
1 1 1 0 (A) 1 (B) 2 (C) 3 (D) 4 (E) 5
Y
0 0 1 0 Z′′ 11. The number of non-essential prime implicants is:
X′′ X X′′ (A) 1 (B) 2 (C) 3 (D) 4 (E) 5

© 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means.

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ECE 270 Outcome 2 Assessment -3- Practice Exam / Solution
______________________________________________________________________________
The following K-map applies to questions 12 through 17:

X′′ X

Z′′ 0 1 0 0

Z 1 0 d 1

Y′′ Y Y′′

12. The cost of a minimal sum of products realization of this function (assuming both
true and complemented variables are available) would be:
(A) 10 (B) 11 (C) 12 (D) 13 (E) none of the above

13. The cost of a minimal product of sums realization of this function (assuming both
true and complemented variables are available) would be:
(A) 10 (B) 11 (C) 12 (D) 13 (E) none of the above

14. Assuming the availability of only true input variables, the fewest number of
2-input NAND gates that are needed to realize this function is:
(A) 5 (B) 6 (C) 7 (D) 8 (E) none of the above

15. Assuming the availability of only true input variables, the fewest number of
2-input NOR gates that are needed to realize this function is:
(A) 5 (B) 6 (C) 7 (D) 8 (E) none of the above

16. Assuming the availability of only true input variables, the fewest number of
2-input open-drain NAND gates that are needed to realize this function is:
(A) 5 (B) 6 (C) 7 (D) 8 (E) none of the above

17. Assuming the availability of only true input variables, the number of pull-up
resistors required to realize this function using 2-input open-drain NAND gates is:
(A) 1 (B) 2 (C) 3 (D) 4 (E) none of the above

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ECE 270 Outcome 2 Assessment -4- Practice Exam / Solution
______________________________________________________________________________
The following K-map applies to question 18:

W′′ W

0 d 1 0 Z′′
Y′′
1 0 1 d
Z
d 1 0 1
Y
0 1 1 0 Z′′

X′′ X X′′

18. Assuming the availability of both true and complemented variables, the simplest
(lowest cost) realization of this function is depicted by the following circuit:

(A) W 2
1 2
Y 3 1 2
X' 3 1 F(W,X,Y,Z)
3

X 2
1
Z 3

(B) W 2
1 2
Y 3 1 2
X 3 1 F(W,X,Y,Z)
3

X' 2
1
Z 3

(C) W 2
1 2
Y 3 1 2
X 3 1 F(W,X,Y,Z)
3

X 2
1
Z 3

(D) W 2
3 1
X 4
Y'
2 2
X' 1 3 1
3 4
F(W,X,Y,Z)
Z
2
W' 3 1
X 4
Y
(E) none of the above

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ECE 270 Outcome 2 Assessment -5- Practice Exam / Solution
______________________________________________________________________________
The following circuit applies to questions 19 through 22:
VCC VCC

12
OD
X 11 1
OD
13 3
2
F(X,Y,Z)
Z
4
OD
X 6
5
Y
9
OD
X 8
10
Z

19. Expressed in a minimum sum-of-products form, the function realized by this

circuit is:
(A) X·Y + X·Z + X′′·Z
(B) X′′·Z′′ + Y′′·Z′′
(C) Y·Z′′ + Y′′·Z′′ + X′′·Y′′
(D) Z + X·Y
(E) none of the above

20. The ON-SET of the function realized by this circuit is:

(A) ∑X,Y,Z(0,2,4)
(B) ∑X,Y,Z(1,3,5,6,7)
(C) ∑X,Y,Z(3,5,7)
(D) ∑X,Y,Z(0,1,2,4,6)
(E) none of the above

21. Expressed in a minimum product-of-sums form, the function realized by this

circuit is:
(A) (X+Z)·(Y+Z)
(B) (X′′+Y′′)·(X+Y)·(Y+Z′′)
(C) Z′′·(X′′+Y′′)
(D) (X′′+Z′′)·(Y′′+Z′′)
(E) none of the above

22. Assuming the availability of only true variables, realization of this same function
using only 2-input NOR gates would require:
(A) two (2-input NOR) gates
(B) three (2-input NOR) gates
(C) four (2-input NOR) gates
(D) five (2-input NOR) gates
(E) none of the above

© 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means.

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 ECE 270 Outcome 2 Assessment -6- Practice Exam / Solution
______________________________________________________________________________
The following circuit and timing chart apply to questions 24 through 25:

2 1
A 2
X 1
C
3

2
1 F(X,Y)
3

2
1
Y 2 1 3 D
B

X
10 ns

F(X,Y)

23. Steady-state (static) analysis of the function realized by this circuit predicts that the
output F(X,Y) should:
(A) always be low
(B) always be high
(C) be equal to the input X
(D) be equal to the input Y
(E) none of the above

24. The dynamic behavior of the circuit (depicted in the timing chart) does NOT match
the steady-state analysis of the function because:
(A) the circuit does not contain a complete sum
(B) a consensus term needs to be added
(C) more than one input changes simultaneously
(D) all of the above
(E) none of the above
© 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means.

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