Design and Simulation of Reduced Instruction Set

Computer (RISC) Processor in VerilogHDL

Abdualaziz Yahya S Alsalem

Mohammad Jaber

December 2020
 Design and Simulation of Reduced Instruction Set Computer
(RISC) Processor in VerilogHDL
by

Abdualaziz Yahya S Alsalem

Mohammad Jaber

Senior Design Project submitted to the Department of Electrical Engineering, College of Engineering, King
Khalid University in partial fulfilment of the requirements for the graduation degree of Bachelor of Science
in Electrical Engineering

Project Assessment Board Project Supervisor (s)

Prof. Fazle Azeem Dr. Neeraj Kumar Shukla

Dr. Mohammed Zubair
Dr. Fakher Eldin Mohamed Suliman

COLLEGE OF ENGINEERING, KING KHALID UNIVERSITY, KINGDOM OF SAUDI ARABIA

 Disclaimer

This document describes work undertaken as part of a programme of study at College of Engineering,
King Khalid University. All views and opinions expressed therein remain the sole responsibility of the
author, and do not necessarily represent those of the institute.
Abstract

In modern day processors architectures, Reduced Instruction Set Computer (RISC) is an efficient and basic
design architecture among Complex Instruction Set Computer (CISC) and RISC as it uses simple commands
that can be divided into several instructions which achieves low-level operations with a single clock cycle.
Compared with CISC which takes a complex time to execute the instructions was reducing the performance
of computing where the speed was drowning when CPU contacts the data memory. In this project work we
have designed the 16-bit RISC processor components in VerilogHDL. The RISC processor are used in
today’s RISC CPUs (and microcontrollers) and represent the vast majority of all CPUs in use. In this work,
the VerilogHDL Coding has been performed for RISC Processor components such as register, ALU, Control
unit, Instruction memory, and data memory for their functional performance and device utilization. It is
found in the synthesis that the Register, ALU, Control Unit, Instruction Memory, and data memory have
number IOBs (Input/Output Block to implement I/O functions) 25%, 21%, 6%, 8%, and 7%. Here, the
memory registers are occupying 25% area whereas control unit has lowest 6%. By improving the
VerilogHDL synthesizable constructs, the area efficiency may be achieved by lowering the IOBs in future.

i
Acknowledgements

First, we thank Almighty Allah for completing our project with all success and competence.

We would specially thank to Chairman of Electrical Engineering Department Dr. Saad Fahd Al-Qahtani for
constantly motivating us to work harder and giving us great support.

We would like to express our special thanks to our Project Supervisor Dr. Neeraj Kumar Shukla for
providing his invaluable guidance, comments, and suggestions throughout the course of the project. and who
gave us the golden opportunity to do this wonderful project on the topic Design and Simulation of Reduced
Instruction Set Computer (RISC) Processor in VerilogHDL, which also helped us in doing a lot of Research
and we came to know about so many new things we are really thankful to him.

Also, we are grateful to our project assessment board Prof. Fazle Azeem, Dr. Mohammed Zubair, and Dr.
Fakher Aldiyn for their encouragement, insightful comments.

Last but not the least, we would like to thank our family members and staff members of our Institution King
Khalid University for their kind cooperation and moral boost-ups that helped us to overcome each small and
big hurdle during the entire process of project development.

Abdualaziz Yahya S Alsalem

Mohammad Jaber

ii
Table of contents

Acknowledgement

Abstract

1. Introduction 7
1.1 Objective and Goals 7
1.1.1 Primary Objectives 7
1.2 Outline of the Thesis 8

2. Literature Review 9
2.1. The RISC Processor 9
2.2 RISC vs. CISC 10
2.2.1 CISC Design 10
2.3 The bridge toward RISC (Historical factors) 10
2.4. Why RISC? 11
2.4.1 Pre-fetching 11
2.4.2 Pipelining 11
2.4.3 Superscalar operation 11
2.5 Architecture Description 11
2.6 RISC Processor 13
2.7 Description of Functional Modules 13
2.7.1 Program Counter Unit (PCU) 13
2.7.2 Instruction Memory 14
2.7.3 Control Unit 14
2.7.4 Data Memory 14
2.7.5 ALU Unit 14
2.7.6 Accumulator 15
2.7.7 Register set 15
2.7.8 Interrupt module 15
2.7.9 1/0 Module 15

3. Methodology 16
3.1 Hardware Description Language 16
3.1.1 What is Verilog HDL? 16
3.1.2 Module Syntax 16
3.1.3 Example: Simple ALU Design at Xilinx ISE 14.7 17

4. Design of RISC Processor Components in VerilogHDL 20

4.1. Register Code 20
4.1.1 RTL Schematic 20
4.1.2 Simulation 22
4.1.3 Device Utilization Report 23
4.2 ALU Code 23
4.2.1 RTL Schematic 23
4.2.2 Simulation 25
4.2.3 Device Utilization Report 26
4.3 ALU Control Unit 26
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 4.3.1 RTL Schematic 27
4.3.2 Simulation 28
4.3.3 Device Utilization Report 29
4.4 Control Unit 29
4.4.1 RTL Schematic 33
4.4.2 Simulation 35
4.4.3 Device Utilization Report 35
4.5 Instruction Memory Unit 35
4.5.1 RTL Schematic 36
4.5.2 Simulation 38
4.5.3 Device Utilization Report 39
4.6 Data Memory Unit 39
4.6.1 RTL Schematic 40
4.6.2 Simulation 41
4.6.3 Device Utilization Report 42
4.7 Control Unit Integration Unit 42

5. Results Analysis 45
5.1 Study of Device Utilization 45
5.2 Results and Analysis 46

6. Conclusions and Recommendations 47

7. Standard and Constraints 48

7.1 Standards 48
7.2 Constraints 48

8. References 49

Appendix 50

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List of figures

Figure 2.1 (a) RISC Architecture (b) Architecture of 16-bit RISC Processor 12

Figure 3.1 ALU Design at Xilinx ISE 14.7 Platform. (a) VerilogHDL Code (b) 18
RTL View-Top Level (c) RTL Schematic-Block Level (d)
Technology Schematic (e) Simulation Waveforms (f) XPower
Analysis

Figure 4.1 (a) Register Module-Top level View (b) Register Module-Block level 21
View (c) Register Module-Technology View (d) Register Module –
Simulation Waveforms

Figure 4.2 (a) ALU Module-Top level View (b) ALU Module-Block level View 24
(c) ALU Module-Technology View (d) ALU Module – Simulation
Waveforms

Figure 4.3 (a) ALU Control Logic Module-Top level View (b) ALU Control 27
Logic Module-Block level View (c) ALU Control Logic Module-
Technology View (d) ALU Control Logic Module – Simulation
Waveforms

Figure 4.4 (a) Control Unit Logic Module-Top level View (b) Control Unit 33
Logic Module-Block level View (c) Control Unit Logic Module-
Technology View (d) Control Unit Logic Module – Simulation
Waveforms

Figure 4.5 (a) Instruction Memory Unit Logic Module-Top level View (b) 36
Instruction Memory Unit Logic Module-Block level View (c)
Instruction Memory Unit Logic Module-Technology View (d)
Instruction Memory Unit Logic Module – Simulation Waveforms

Figure 4.6 (a) Data Memory Unit Logic Module-Top level View (b) Data 40
Memory Unit Logic Module-Block level View (c) Data Memory
Unit Logic Module-Technology View (d) Data Memory Unit Logic
Module – Simulation Waveforms

Figure 5.1 Simulation Waveforms with IOB Summary of Different Logic 46

Blocks

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List of tables

Table 2.1 Comparison of CISC and RISC Architectures 11

Table 4.1 Register Module: Device Utilization Summary and IOB Report 23

Table 4.2 ALU Module: Device Utilization Summary and IOB Report 26

Table 4.3 ALU Control Unit: Device Utilization Summary and IOB Report 29

Table 4.4 Control Module: Device Utilization Summary and IOB Report 35

Table 4.5 Instruction Memory Module: Device Utilization Summary and IOB 39
Report

Table 4.6 Instruction Memory Module: Device Utilization Summary and IOB 42
Report

Table 5.1 Comparative Table of Logic Utilization in Different Logic Blocks 46

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

1. Introduction

The Reduced Instruction Set Computer (RISC) is a microprocessor CPU design philosophy that favours a
smaller and simpler set of instructions that all take about the same amount of time to execute. The most
common RISC microprocessors are ARM, DEC Alpha, PA-RISC, SPARC, MIPS, and IBM's PowerPC.

The idea was inspired by the discovery that many of the features that were included in traditional CPU
designs to facilitate coding were being ignored by the programs that were running on them. Also these more
complex features took several processor cycles to be performed. Additionally, the performance gap between
the processor and main memory was increasing. This led to a number of techniques to streamline processing
within the CPU, while at the same time attempting to reduce the total number of memory accesses.

When the controller design become more complex in CISC and the performance was also not up to
expectations, people started looking on some other alternatives. It had been found that when a processor talks
to the memory the speed gets killed. So the one improvement on CPI was to keep the instruction set very
simple. Simple in not the way it works but the way it looks. That’s why we have very few instructions in any
typical RISC architecture where processor asks data from memory probably not other than Load and Store.
We avoid keeping such addressing modes. The complexity of controller design has been overcome with the
help of operands and Opcode bits fixed in instruction register. At the end the pipelining added a new
dimension in the speed just with the help of some additional registers. Now what pipeline does is it increases
throughput by reducing CPI. The instruction can be executed effectively in one clock cycle. The pipelining
in any kind of architecture took birth from the inherent parallelism and the idle states of components. The
pipelined architecture could be further enhanced with the concepts known as super-scaling. There we provide
more than one execution unit. The time when one unit is busy with the current execution task, the fetch unit
can probably fetch the next instruction which would be executed with the help of some other execution unit
present in system.

Features which are generally found in RISC designs are:

Uniform instruction encoding (for example the op-code is always in the same bit position in each instruction,
which is always one word long), which allows faster decoding. A homogeneous register set, allowing any
register to be used in any context and simplifying compiler design.

Simple addressing modes (complex addressing modes are replaced by sequences of simple arithmetic
instructions). Few data types supported in hardware (for example, some CISC machines had instructions for
dealing with byte strings. Others had support for polynomials and complex numbers. Such instructions are
unlikely to be found on a RISC machine). Over many years, RISC instruction sets have tended to grow in
size. Thus, some have started using the term "load-store" to describe RISC processors, since this is the key
element of all such designs. Instead of the CPU itself handling many addressing modes, load-store
architecture uses a separate unit dedicated to handling very simple forms of load and store operations. CISC
processors are then termed "register-memory" or "memory-memory".

1.1. Objectives and Goals

The purpose of this study was to design and simulate RISC processors components for a general-purpose
processor application, also to analyse the functional performance of the components.

The Software Implementation of RISC processor components using RTL design methodologies.

1.1.1. Primary Objectives

The primary objective of this project are as follows:
• To study and design RISC processor components ALU, Registers, Control Units, etc. for their functional
performances using RTL design methodologies
• To implement and write RTL code for RISC processor components
• To synthesize the RISC processor components and perform their devices utilization analysis

1.2. Outline of the Thesis

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

This thesis is organized as follows, The Chapter 1 provides a brief introduction and review on the design and
implementation of RISC processor and it’s components for a general purpose processor as a primary
objectives of the project. The Chapter 2 provides a literature survey on the RISC processor and its
implementation methodologies. Chapter 3 starts with the review on the detailed explanation regarding the
design components of the system. This chapter is the core of the project. It explains the proposed system
model and technique used in this project, which is the RTL design and synthesis. The Chapter 4 presents the
implementation method, results and associated discussions and Chapter 5 concludes the thesis followed by
the references and appendix.

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

2. Literature Review

2.1. The RISC Processor

Today RISC CPUs (and microcontrollers) represent the vast majority of all CPUs in use. The RISC
is a design methodology which supports small and simple set of instructions that all requires the
same amount of time to execute. The RISC design technique offers power in even small sizes, and
thus has come to completely dominate the market for low-power "embedded" CPUs. Embedded
CPUs are by far the largest market for processors. RISC had also completely taken over the market
for larger workstations for much of the 90s. After the release of the Sun SPARCstation the other
vendors rushed to compete with RISC based solutions of their own. Even the mainframe world is
now completely RISC based.

The central unit of all smart devices are Processors, whether they be electronic devices or
otherwise. Their smartness comes as a direct result of the decisions and controls that processor
makes. The existing commercial microprocessors are provided as black box units; with which users
are unable to monitor internal signals and operation process, neither can they modify the original
structure. In order to solve this problem 16-bit fully functional single cycle processor is designed in
terms of its architecture and its functional capabilities. The procedure of design and verification for
a 16-bit processor is introduced in this paper. The key architecture elements are being described, as
well as the hardware block diagram and internal structure. The summary of instruction set is
presented. This processor is modify as a VERILOG Hardware Description Language
(VERILOGHDL) and gives access to every internal signal. In order to consume fewer resources,
the design of arithmetic logical unit (ALU) is optimized. The RTL views and verified simulation
results of processor are shown in this paper. The synthesis report of the design is also described.
The design architecture is written in VERILOG Hardware Description Language (VERILOGHDL)
code using Xilinx ISE tool for synthesis and simulation [1].

In [2] the Reduced Instruction Set Computer (RISC) processor for better performance has been
presented. The designed processor was simulated and synthesized using Xilinx 14.7 ISE design
suite. The processor executes each and every instruction in more than one cycle that's why the term
multi-cycle. Each instruction is divided into three main states namely the Fetch state, the Decode
state and the Execution state. The first two sates remain the same for all the instruction the last state,
however depends on the type of operation performed in that instruction.

Shraddha M. Bhagat, etal, presented a design of 16-bit RISC processor in [3] using the
VerilogHDL. The RISC processor comprises of the blocks mainly ALU, Controller, Register files,
and Data memory unit. The proposed processor carried out with the help of von Neumann
architecture, having only one shared memory for instruction and data. The proposed RISC
processor which can be very, simple and clean to investigate contains 15 instructions. ModelSim is
used for logical verification. The proposed RISC processor is analyzed using Xilinx ISE tool.

According to the authors in [4], RISC is a design philosophy to reduce the complexity of instruction
set that in turn reduces the amount of space, cycle time, and cost, power consumption taken into
account during the implementation of the design. The existing system is an Arithmetic and Logical
Unit which performs only Arithmetic operations such as ADD, SUB, MUL, DIV and logical
operations such as AND, OR, NAND, NOR, NOT, XOR, XNOR operations and consumes more
power .The execution delay is also high. To overcome the above mentioned problems, 16-bit RISC

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

processor is proposed. 16-bit low power RISC processor consists of the blocks mainly ALU,
Universal shift register and Barrel Shifter. This system consumes less power and the execution
delay is also less. The processor is designed using XILINX ISE Design suit 14.3 & the total power
estimation is done by the X Power analyzer.

2.2 RISC vs. CISC

A comparison based study of the RISC and CISC processor is presented here.

2.2.1 CISC Designs:

An overriding characteristic of CISC machines is an approach to instruction set architecture that
emphasizes doing more with each instruction. As a result, CISC machines have a wide variety of
addressing modes. CISC machines take a “has it your way” approach to the location and number of
operands in various instructions. As a result instructions are of widely varying length and execution
times.

2.3 The bridge toward RISC (Historical factors):

The capabilities of CISC allowed more operations to be performed into the same program size.
During that period, program and data storage were given more importance since cost of memory
was high. An attempt was made to narrow the semantic gap, that is, the gap that existed between
machine instruction sets and high level language constructs with complicated instructions and
addressing modes to obtain performance increase. Most of these “improvements” were rejected by
compiler writers on the context that they did not fit well with the language requirements and were
of only limited usefulness. At the same time, research conducted by David Patterson and Donald
Knuth showed that 85% of a program’s statements were assignments, conditional or procedure
calls. Nearly 80% of the assignment statements were MOVE instructions with no arithmetic
operations.

As more and more capabilities were added to the processors, it was found increasingly difficult to
support higher clock speeds that would otherwise have been possible. Complex instructions and
addressing modes worked against higher clock speeds, because of the greater number of
microscopic actions that had to be performed per instruction. Moreover, RAM prices dropped
sufficiently so that the pressure on system designers was less to design instructions that did more
that it was to design systems that were faster. It was also becoming cost-effective to employ small
amounts of higher-speed cache memory to reduce memory latency i.e. the writing time between
when a memory is made and when it has been satisfied. The comparison of CISC and RISC
Architectures is presented in Table 2.1.

TABLE 2.1: Comparison of CISC and RISC Architectures

CISC RISC

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Multiple clock cycle Single clock cycle

Any instructions may refer memory. Only LOAD/STORE refer memory.
Not pipelined or less pipelined Highly pipelined
Instructions interpreted by the micro Instructions executed by the hardware.
program.
Variable format instructions Fixed format instruction
Many instructions and modes Few instructions and modes
Complexity in micro program Complexity in the compiler
Single register set Multiple register set

2.4 Why RISC?

Various attempts have been made to increase the instruction execution rates by overlapping the
execution of more than one instruction since the earliest day of computing. The most common ways
of overlapping are pre-fetching, pipelining and superscalar operation.

2.4.1 Pre-fetching: The process of fetching next instruction or instructions into an event queue
before the current instruction is complete is called pre-fetching. The earliest 16-bit
microprocessor, the Intel 8086/8, pre-fetches into a non-board queue up to six bytes following
the byte currently being executed thereby making them immediately available for decoding and
execution, without latency.

2.4.2 Pipelining: Pipelining instructions means starting or issuing an instruction prior to the
completion of the currently executing one. The current generation of machines carries this to a
considerable extent. The PowerPC 601 has 20 separate pipeline stages in which various portions
of various instructions are executing simultaneously.

2.4.3 Superscalar operation: Superscalar operation refers to a processor that can issue more
than one instruction simultaneously. The PPC 601 has independent integer, floating-point and
branch units, each of which can be executing an instruction simultaneously.

CISC machine designers incorporated pre-fetching, pipelining and superscalar operation in their
designs but with instructions that were long and complex and operand access depending on complex
address arithmetic, it was difficult to make efficient use of these new speed-up techniques.
Furthermore, complex instructions and addressing modes hold down clock speed compared to
simple instructions. RISC machines were designed to efficiently exploit the caching, pre-fetching,
pipelining and superscalar methods that were invented in the days of CISC machines.

2.5 Architecture Description

Reduced Instruction Set Computers (RISC) are designed to have a small set of instructions that
execute in short clock cycles, with a small number of cycles per instruction. RISC machines are
optimized to achieve efficient pipelining of their instruction streams. In general the architecture of
the processor is selected according to power consumption or speed requirement of an application. If
power consumption needs to be low then RISC is the better architecture to use. Once architecture

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

has been selected then hardware description languages (HDLs) are used for modeling the system
which serves as a descriptive medium that can be used by a synthesis tool.

Figure 2.1(a): RISC Architecture

The internal architecture of a RISC Processor is shown in Figure. The processor consists of
arithmetic logic unit (ALU), a controller, register set, internal buses and multiplexers. Program to be
executed on the processor and data are stored in the external memory. Instructions are fetched
synchronously from memory, decoded, and executed by the processor.

Processor performs the following operations according to the instructions fetched from the memory.

(1) operate on data within the arithmetic and logic unit (ALU)
(2) change the contents of storage registers
(3) change the contents of the program counter (PC) instruction register (IR) and the address
register (Add_Reg)
(4) change the contents of memory
(5) retrieve data and instructions from memory
(6) control the movement of data on the system busses.

The instruction register contains the instruction that is currently being executed; the program
counter contains the address of the next instruction to be executed; and the address register
(Add_Reg), holds the address of the memory location that will be addressed next by a read or write
operation.

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 2.1(b). Architecture of 16-bit RISC Processor

2.6 RISC Processor

The processor includes registers, data paths, control lines, and an ALU capable of performing
arithmetic and logic operations on its operands, subject to the opcode held in the instruction
register. A multiplexer, Mux_1, determines the source of data that is bound for Bus_1, and a second
multiplexer, Mux_2, determines the source of data bound for Bus_2, The input data paths to
Mux_1 are from seven general purpose registers (R0,R1,R2,R3,R4,R5,R6) and from the program
counter(PC). The contents of Bus_1 can be steered to the ALU, to memory, or to Bus_2 through
Mux_2. The input data paths to Mux_2 are from the ALU_out, Mux_1, and the memory unit. Thus
an instruction can be fetched from memory, placed on Bus_2, and loaded into the instruction
register (IR). A word of data can be fetched from memory, and steered to a general-purpose register
or to the operand register (Reg_Y) prior to an operation of the ALU. The result of an ALU
operation can be placed on Bus_2, loaded into a register, and subsequently transferred to memory.
The dedicated register Reg_z holds a flag to indicate the result of an ALU operation is zero and
Reg_c holds a flag to indicate carry generated.

2.7 Description of Functional Modules

In the present work, the RISC processor consists of blocks namely, Program Counter Unit (PCU),
Instruction Memory, Data Memory, Control Unit, Register set, Arithmetic & Logical Unit (ALU),
110 module and Interrupt module.

2.7.1 Program Counter Unit (PCU)

Program Counter unit consists of Program Counter (PC), Program Counter Save (PCS), Program
Counter Register (PCR). In the proposed processor, Program Counter (PC) is 18-bit wide register

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

that contains the address (location) of the instruction being executed at the current time. As each
instruction is fetched, the program counter increases its stored value by one. In fetch cycle, an 18-
bit address bus known as IM ADDRBUS transfers Program Counter content to Instruction Memory
(IM) when the corresponding control signal is enabled. The Program Counter Save (PCS) stores (l8-
bit), Program Counter incremented by two value, when SA V PC instruction is executed. A
Program Counter Register (PCR) is used to store address of the instruction, when a jump instruction
is executed. ST ACKPC is used to store the current PC value during the execution of interrupt
service routine.

2.7.2 Instruction Memory

Instruction Memory is 16-bit wide and having 256 Kilobytes of address locations, so that any
practical real time programs can be fitted into it. In fetch cycle, when the corresponding control
signals are enabled, a 16-bit data bus known as IM DA TABUS transfers Instruction Memory (IM)
content to Instruction Register (IR), if IM ADDRBUS provides an address location to IM at the
same instance of time.

2.7.3 Control Unit

The contro1 unit contains Instruction Register (IR), Instruction RegisterX (IRX), tstate counter,
Low Power Unit (LPU) and instruction decoder. The Instruction Register gets the instruction for
decoding during fetch cycle. While executing one instruction next instruction is being fetched,
therefore IR content should be stored in another register for execution of the instruction. For this
purpose, Instruction Register (IR) content is moved to Instruction RegisterX (IRX) during every
rising edge of c10ck of execution cyc1e. Tstate counter generates fetch and execution cyc1es
required for the proper working of processor. The Tstates TF1 (fetch cycle), TX1 (execution cycle),
TX2 (execution cycle2 only for jump instruction) are generated at rising edge of clock. The
pipelining feature is applied in the Tstate counter module. Interrupt priority and exceptions in
instructions, like jump, are also taken in account in Tstate counter module. Instruction decoder will
generate controls signals required for the modules whenever IRX is loaded with a valid instruction.
As IRX is loaded at every rising edge of execution cycle, so control signals are generated at the
same instance of time. Clock gating for Data Memory and general-purpose register set are done in
Low Power Unit of Control Unit. Control Unit will receive inputs from flag register and Interrupt
Module. The Control Unit will take input clock from source clock of FPGA and generate 56 control
signals and 3 clock signals for the proper working of all modules. The three clock signals include
gated clock signals for register set and Data Memory modules and 25 MHz output c10ck signal for
all other modules.

2.7.4 Data Memory

Data Memory is 8-bit wide and having 4 Kilobytes of address locations. Data Memory gets the
required address location by 12-bit address bus known DM ADDRBUS from control unit. Data
memory provides read and write control, can be accessed by 8-bit data bus known as system data
bus.

2.7.5 ALU Unit

ALU is connected to Accumulator and general-purpose registers by its 8-bit buses ALU DAT
ABUS A and ALU DATABUS B. ALU unit consists of AND, OR, XOR, ADD, SUB operations.
The result of operation is stored in Accumulator. The result also contains zero flag (Z), Carry
flag(C), Borrow flag (B) and parity flag, which will be stored in 4-bit Flag Register. Parity flag is
set when resultant of ALU operation contains odd number of ones.

2.7.6 Accumulator

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Accumulator is an 8-bit wide register, integral part of the proposed processor, as data transfer, ALU
operations and 1/0 operations takes place through it. Accumulator also contains increment,
decrement, and compliment, rotate right and rotate left operations.

2.7.7 Register set

Register set contains eight 8-bit registers RO, R1, R2, R3, R4, R5, R6 and R7, which can be used
for storing data that are frequently used. Register set is connected to ALU unit for arithmetic and
logic operations. It is also connected to SYSTEM_DATABUS for loading and storing data.

2.7.8 Interrupt module:

The interrupt module contains two external interrupts IO and 11. The interrupts are priority based,
the IO interrupt having highest priority. The 11 interrupt is mask able and IO is not mask able. The
interrupt module is having a 2-bit register INTCON to control the functions in interrupt module. Its
bit 1 is used for enabling and disabling interrupt and bit 0 is used for masking 11.

2.7.9 1/0 Module:

The 1/0 module has one 8-bit input port and one 8-bit output port for communicating with external
environment. The input port and output port are directly connected to Accumulator. It will transfer
data to and from Accumulator when corresponding control signals are enabled.

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

3. Methodology
The VerilogHDL (Verify Logic Hardware Description Language)
IEEE Std. 1364-2001 & 2005

3.1 Hardware Description Language

Have high-level language constructs to describe the functionality and connectivity of the circuit Can
describe a design at some levels of abstraction – Behavioral (Algoritmic, RTL), Structural (Gate-
level), main reasons of important role of HDL in modern design methodology: - Design
functionality can be verified early in the design process. Design simulation at this higher level,
before implementation at the gate level, allows you to evaluate architectural and design decisions
[5,6,7].

3.1.1 What is VerilogHDL?

Verilog is hardware language only for digital IC. - Verilog was started initially as a proprietary
hardware modeling language by Gateway Design Automation Inc. around 1984. It is rumored that
the original language was designed by taking features from the most popular HDL language of the
time, called HiLo, as well as from traditional computer languages such as C. Verilog simulator was
first used beginning in 1985 and was extended substantially through 1987. The implementation was
the Verilog simulator sold by Gateway. The first major extension was Verilog-XL, which added a
few features and implemented the infamous "XL algorithm" which was a very efficient method for
doing gate-level simulation. Verilog Hardware Description Language - The time was late 1990.
Cadence Design System, whose primary product at that time included Thin film process simulator,
decided to acquire Gateway Automation System. Along with other Gateway products, Cadence now
became the owner of the Verilog language.

Verilog digital logic simulator tools allow to perform the following tasks in the design process
without building a hardware prototype.

- Determine the feasibility of new design ideas

- Try more than one approach to a design problem
- Verify functionality
- Identify design problems

3.1.2 Module Syntax

module <module name > (input, output);
…………..
<logic of program>
……………
……………
end module

Number Representation

<size><base format><number>
549 // decimal number
'h 8FF // hex number
'o765 // octal number

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

4'b11 // 4-bit binary number 0011

3'b10x // 3-bit binary number with least significant bit unknown
5'd3 // 5-bit decimal number
-4'b11 // 4-bit two's complement of 0011 or 1101

3.1.3 Example: Simple ALU Design at Xilinx ISE 14.7 Software

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:31:32 11/26/2020
// Design Name: RISC Processor
// Module Name: ALU_Code
//////////////////////////////////////////////////////////////////////////////////
//Code for ALU
module ALU(input [15:0] a, input [15:0] b, input [2:0] alu_control, output reg [15:0] result, output zero );
always @(*)
begin
case(alu_control)
3'b000: result = a + b; // add
3'b001: result = a - b; // sub
3'b010: result = ~a;
3'b011: result = a<<b;
3'b100: result = a>>b;
3'b101: result = a & b; // and
3'b110: result = a | b; // or
3'b111: begin if (a<b) result = 16'd1;
else result = 16'd0;
end
default:result = a + b; // add
endcase
end
assign zero = (result==16'd0) ? 1'b1: 1'b0;
endmodule

Figure 3.1 (a)

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DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 3.1 (b)

Figure 3.1 (c)

Figure 3.1 (d)

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 3.1 (e)

Figure 3.1 (f)

Figure 3: ALU Design at Xilinx ISE 14.7 Platform. (a) VerilogHDL Code (b) RTL View-Top Level (c)
RTL Schematic-Block Level (d) Technology Schematic (e) Simulation Waveforms (f) XPower Analysis

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

4. Design of RISC Processor Components in VerilogHDL

Simulation of 16-bit RISC Processor Components and Device Utilization Analysis

4.1. Register Code

Register is a very fast computer memory, used to store data/instruction in-execution. A Register is a
group of flip-flops with each flip-flop capable of storing one bit of information. A register consists
of a group of flip-flops and gates.
Registers Holds values of internal operation, such as the address of the instruction being executed
and the data being processed. Example: ALU Register (AC), Program Counter Register(PC), Status
Register(Flag), Data Registers, etc.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:16:45 11/26/2020
// Design Name:
// Module Name: Registers_Code
// Project Name:RISC Processor
///////////////////////////////////////////////////////////////////////////////////
//Code for registers
module GPRs (input clk,input wr, input [2:0] wr_dest, input[15:0] wr_data,input [2:0]
read_addr_1,output [15:0] read_data_1,input [2:0] read_addr_2, output [15:0] read_data_2);
reg [15:0] reg_array [7:0];
integer i;
initial
begin
for(i=0;i<8;i=i+1)
reg_array[i] <= 16'd0;
end
always @ (posedge clk )
begin
if(wr)
begin
reg_array[wr_dest] <= wr_data;
end
end
assign read_data_1 = reg_array[read_addr_1];
assign read_data_2 = reg_array[read_addr_2];
endmodule

4.1.1 RTL SCHEMATIC

The Register Transfer Level (RTL) schematic of Register Module is shown in Figure 4.1 Register
Module-Top level View, Register Module-Block level View, and Register Module-Technology
View.

A: Top Level View

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.1 (a)

B: Block Level View

Figure 4.1 (b)

C. Technology Schematic

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.1 (C)

4.1.2 Simulation
The simulation waveform of Register module is presented in Figure 6.

Figure 4.1 (d)

Figure 4: (a) Register Module-Top level View (b) Register Module-Block level View (c) Register
Module-Technology View (d) Register Module – Simulation Waveforms
4.1.3 Device Utilization Report

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

The device utilization summary (estimated values) and IOB report is presented in Table 4.1. The
number of IOBs is 25%.

Table 4.1: Register Module: Device Utilization Summary and IOB Report

4.2 ALU Code

ALU is in the execution stage of pipelining which performs all computations i.e. arithmetic (ADD,
SUB, MUL, DIV) and logical (AND, OR, NOT, XOR) operations.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:31:32 11/26/2020
// Design Name: RISC Processor
// Module Name: ALU_Code
//////////////////////////////////////////////////////////////////////////////////
//Code for ALU
module ALU(input [15:0] a, input [15:0] b, input [2:0] alu_control, output reg [15:0] result );
always @(*)
begin
case(alu_control)
3'b000: result = a + b; // add
3'b001: result = a - b; // sub
3'b010: result = ~a;
3'b011: result = a<<b;
3'b100: result = a>>b;
3'b101: result = a & b; // and
3'b110: result = a | b; // or
3'b111: begin if (a<b) result = 16'd1;
else result = 16'd0;
end
default:result = a + b; // add
endcase
end
assign zero = (result==16'd0) ? 1'b1: 1'b0;
endmodule

4.2.1 RTL SCHEMATIC

The Register Transfer Level (RTL) schematic of Register Module is shown in Figure 4.2 Register
Module-Top level View, Register Module-Block level View, and Register Module-Technology
View.

A. Top Level View

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.2(a)

B. Block Level View

Figure 4.2(b)

C. Technology Schematic

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.2(c)

4.2.2 Simulation

Figure 4.2(d)

Figure 4.2: (a) ALU Module-Top level View (b) ALU Module-Block level View (c) ALU Module-
Technology View (d) ALU Module – Simulation Waveforms

4.2.3 Device Utilization Report

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

The device utilization summary (estimated values) and IOB report is presented in Table 4.2. The
number of IOBs is 21%.

Table 4.2: ALU Module: Device Utilization Summary and IOB Report

4.3. ALU Control Unit Code

An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations.
The control unit tells the ALU what operation to perform on that data, and the ALU stores the result
in an output register. The control unit moves the data between these registers, the ALU, and
memory.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:43:57 11/26/2020
// Design Name: ALU Control Unit
// Module Name: ALU_Control_Unit
//////////////////////////////////////////////////////////////////////////////////
//Code for ALU Control Unit
module alu_control( ALU_Cnt, ALUOp, Opcode);
output reg[2:0] ALU_Cnt;
input [1:0] ALUOp;
input [3:0] Opcode;
wire [5:0] ALUControlIn;
assign ALUControlIn = {ALUOp,Opcode};
always @(ALUControlIn)
casex (ALUControlIn)
6'b10xxxx: ALU_Cnt=3'b000;
6'b01xxxx: ALU_Cnt=3'b001;
6'b000010: ALU_Cnt=3'b000;
6'b000011: ALU_Cnt=3'b001;
6'b000100: ALU_Cnt=3'b010;
6'b000101: ALU_Cnt=3'b011;
6'b000110: ALU_Cnt=3'b100;
6'b000111: ALU_Cnt=3'b101;
6'b001000: ALU_Cnt=3'b110;
6'b001001: ALU_Cnt=3'b111;
default: ALU_Cnt=3'b000;
endcase
endmodule

4.3.1 RTL SCHEMATIC

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

The Register Transfer Level (RTL) schematic of Register Module is shown in Figure 4.3 Register
Module-Top level View, Register Module-Block level View, and Register Module-Technology
View.

A. Top Level View

Figure 4.3 (a)

B. Block Level View

Figure 4.3 (b)

C. Technology Schematic

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.3 (c)

4.3.2 Simulation

Figure 4.3 (d)

Figure 4.3: (a) ALU Control Logic Module-Top level View (b) ALU Control Logic Module-Block
level View (c) ALU Control Logic Module-Technology View (d) ALU Control Logic Module –
Simulation Waveforms

4.3.3 Device Utilization Report

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

The device utilization summary (estimated values) and IOB report is presented in Table 4.3. The
number of IOBs is 3%.

Table 4.3: ALU Control Unit: Device Utilization Summary and IOB Report

4.4. Control Unit Code

A control unit or CU is circuitry that directs operations within a computer's processor. It lets the
computer's logic unit, memory, and both input and output devices know how to respond to
instructions received from a program. The CU manages the sequence and timing of events carried
out within the processor.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 22:06:02 11/26/2020
// Design Name: RISC Processor
// Module Name: Control_Unit
//////////////////////////////////////////////////////////////////////////////////
//Code for Control Unit
module Control_Unit(
input[3:0] opcode,
output reg[1:0] alu_op,
output reg jump,beq,bne,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write );
always @(*)
begin
case(opcode)
4'b0000: // LW
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b1;
reg_write = 1'b1;
mem_read = 1'b1;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b10;
jump = 1'b0;
end
4'b0001: // SW
begin
reg_dst = 1'b0;
alu_src = 1'b1;
mem_to_reg = 1'b0;
reg_write = 1'b0;

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

mem_read = 1'b0;
mem_write = 1'b1;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b10;
jump = 1'b0;
end
4'b0010: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0011: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0100: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0101: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0110: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b0111: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b1000: // data_processing
begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b1001: // data_processing
begin

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
4'b1011: // BEQ
begin
reg_dst = 1'b0;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b1;
bne = 1'b0;
alu_op = 2'b01;
jump = 1'b0;
end
4'b1100: // BNE
begin
reg_dst = 1'b0;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b1;
alu_op = 2'b01;
jump = 1'b0;
end
4'b1101: // J
begin
reg_dst = 1'b0;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b0;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b1;
end

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

default: begin
reg_dst = 1'b1;
alu_src = 1'b0;
mem_to_reg = 1'b0;
reg_write = 1'b1;
mem_read = 1'b0;
mem_write = 1'b0;
beq = 1'b0;
bne = 1'b0;
alu_op = 2'b00;
jump = 1'b0;
end
endcase
end
endmodule

4.4.1 RTL SCHEMATIC

The Register Transfer Level (RTL) schematic of Register Module is shown in Figure 4.4 Register
Module-Top level View, Register Module-Block level View, and Register Module-Technology
View.

A. Top Level View

Figure 4.4 (a)

B. Block Level View

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.4 (b)

C. Technology Schematic

Figure 4.4 (c)

4.4.2 Simulation

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.4 (d)

Figure 4.4: (a) Control Unit Logic Module-Top level View (b) Control Unit Logic Module-Block
level View (c) Control Unit Logic Module-Technology View (d) Control Unit Logic Module –
Simulation Waveforms

4.4.3 Device Utilization Report

The device utilization summary (estimated values) and IOB report is presented in Table 4.4. The
number of IOBs is 6%.

Table 4.4: Control Module: Device Utilization Summary and IOB Report

4.5. Instruction Memory Code

The instruction memory stores up to 4,096 instructions (using 12-bit addresses), and the data
memory stores 256 bytes (using 8-bit addresses). The arithmetic and logical instructions operate on
8-bit data values stored in the core's general-purpose registers and store the result in the destination
register. The RISC instructions are simple and engages one word in memory. RISC instructions are
of fixed size, the opcode and the operands in the instruction are located in the same position within
a word in different instructions. One instruction in RISC architecture executes in one clock cycle.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 22:10:33 11/26/2020
// Design Name: RISC Processor
// Module Name: Instruction_Code
//////////////////////////////////////////////////////////////////////////////////
//Code for instruction memory
module Instruction_Memory(input[15:0] pc,output reg [15:0] instruction);
reg [15:0] memory [14:0];
wire [3 : 0] rom_addr = pc[4 : 1];
always@(rom_addr)begin
case (rom_addr)
4'b0000: instruction <= 16'b0000010000000000;
4'b0001: instruction <= 16'b0000010001000001;

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

4'b0010: instruction <= 16'b0010000001010000;

4'b0011: instruction <= 16'b0001001010000000;
4'b0100: instruction <= 16'b0011000001010000;
4'b0101: instruction <= 16'b0100000001010000;
4'b0110: instruction <= 16'b0101000001010000;
4'b0111: instruction <= 16'b0110000001010000;
4'b1000: instruction <= 16'b0111000001010000;
4'b1001: instruction <= 16'b1000000001010000;
4'b1010: instruction <= 16'b1001000001010000;
4'b1011: instruction <= 16'b0010000000000000;
4'b1100: instruction <= 16'b1011000001000001;
4'b1101: instruction <= 16'b1100000001000000;
4'b1110: instruction <= 16'b1101000000000000;
endcase
end
endmodule

4.5.1 RTL SCHEMATIC

The Register Transfer Level (RTL) schematic of Register Module is shown in Figure 4.5 Register
Module-Top level View, Register Module-Block level View and Register Module-Technology
View.

A. Top Level View

Figure 4.5 (a)

B. Block Level View

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.5 (b)

C. Technology Schematic

37
 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.5 (c)

4.5.2 Simulation

Figure 4.5 (d)

Figure 4.5: (a) Instruction Memory Unit Logic Module-Top level View (b) Instruction Memory
Unit Logic Module-Block level View (c) Instruction Memory Unit Logic Module-Technology
View (d) Instruction Memory Unit Logic Module – Simulation Waveforms

4.5.3 Device Utilization Report

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

The device utilization summary (estimated values) and IOB report is presented in Table 4.5. The
number of IOBs is 8%.

Table 4.5: Instruction Memory Module: Device Utilization Summary and IOB Report

4.6. Data Memory Code

Memory is the part of the computer that holds data and instructions for processing. Although
closely associated with the central processing unit, memory is separate from it. Memory stores
program instructions or data for only as long as the program they pertain to is in operation. The
Data Memory is also called as RAM which is temporary memory and used to store the data values
need for processor and data values coming from processor after processing.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 22:13:44 11/26/2020
// Design Name: RISC Processor
// Module Name: Data_Memory
//////////////////////////////////////////////////////////////////////////////////
//Code for data memory
module data_memory(input clk,input [15:0] mem_access_addr,input [15:0] mem_write_data,input
mem_write_en,input mem_read,output reg [15:0] mem_read_data);
reg [1:0] memory [1:0];
integer f;
wire [2:0] ram_addr=mem_access_addr[2:0];
always@(ram_addr)begin
case (ram_addr)
3'b000: mem_read_data <= 16'b0000000000000001;
3'b001: mem_read_data <= 16'b0000000000000010;
3'b010: mem_read_data <= 16'b0000000000000001;
3'b011: mem_read_data <= 16'b0000000000000010;
3'b100: mem_read_data <= 16'b0000000000000001;
3'b101: mem_read_data <= 16'b0000000000000010;
3'b110: mem_read_data <= 16'b0000000000000001;
3'b111: mem_read_data <= 16'b0000000000000010;
endcase
end
endmodule

4.6.1 RTL SCHEMATIC

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

The Register Transfer Level (RTL) schematic of Register Module is shown in Figure 4.6 Register
Module-Top level View, Register Module-Block level View and Register Module-Technology
View.

A. Top Level View

Figure 4.6 (a)

B. Block Level View

Figure 4.6 (b)

C. Technology Schematic

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Figure 4.6 (c)

4.6.2 Simulation

Figure 4.6 (d)

Figure 4.6: (a) Data Memory Unit Logic Module-Top level View (b) Data Memory Unit Logic
Module-Block level View (c) Data Memory Unit Logic Module-Technology View (d) Data
Memory Unit Logic Module – Simulation Waveforms
4.6.3 Device Utilization Report

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

The device utilization summary (estimated values) and IOB report is presented in Table 4.6. The
number of IOBs is 25%.

Table 4.6: Data Memory Module: Device Utilization Summary and IOB Report

4. 7. Control Unit Integration Code

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Create Date: 22:19:02 11/26/2020
// Design Name: RISCProcessor
// Module Name: Data_Path
//////////////////////////////////////////////////////////////////////////////////
//Code for data path unit
module Datapath_Unit( input clk, input
jump,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write,bne,
input[1:0] alu_op,output[3:0] opcode);
reg [15:0] pc_current;
wire [15:0] pc_next,pc2;
wire [15:0] instr;
wire [2:0] reg_write_dest;
wire [15:0] reg_write_data;
wire [2:0] reg_read_addr_1;
wire [15:0] reg_read_data_1;
wire [2:0] reg_read_addr_2;
wire [15:0] reg_read_data_2;
wire [15:0] ext_im,read_data2;
wire [2:0] ALU_Control;
wire [15:0] ALU_out;
wire zero_flag;
wire [15:0] PC_j, PC_beq, PC_2beq,PC_2bne,PC_bne;
wire beq_control;
wire [12:0] jump_shift;
wire [15:0] mem_read_data;
// PC
initial begin
pc_current <= 16'd0;
end
always @(posedge clk)
begin
pc_current <= pc_next;
end
assign pc2 = pc_current + 16'd2;

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

// instruction memory
Instruction_Memory im(.pc(pc_current),.instruction(instr));
// jump shift left 2
assign jump_shift = {instr[11:0],1'b0};
// multiplexer regdest
assign reg_write_dest = (reg_dst==1'b1) ? instr[5:3] :instr[8:6];
// register file
assign reg_read_addr_1 = instr[11:9];
assign reg_read_addr_2 = instr[8:6];

// GENERAL PURPOSE REGISTERs

GPRs reg_file
(
.clk(clk),
.reg_write_en(reg_write),
.reg_write_dest(reg_write_dest),
.reg_write_data(reg_write_data),
.reg_read_addr_1(reg_read_addr_1),
.reg_read_data_1(reg_read_data_1),
.reg_read_addr_2(reg_read_addr_2),
.reg_read_data_2(reg_read_data_2)
);
// immediate extend
assign ext_im = {{10{instr[5]}},instr[5:0]};
// ALU control unit
alu_control
ALU_Control_unit(.ALUOp(alu_op),.Opcode(instr[15:12]),.ALU_Cnt(ALU_Control));
// multiplexer alu_src
assign read_data2 = (alu_src==1'b1) ? ext_im : reg_read_data_2;
// ALU
ALU
alu_unit(.a(reg_read_data_1),.b(read_data2),.alu_control(ALU_Control),.result(ALU_out),.zero(zer
o_flag));
// PC beq add
assign PC_beq = pc2 + {ext_im[14:0],1'b0};
assign PC_bne = pc2 + {ext_im[14:0],1'b0};
// beq control
assign beq_control = beq & zero_flag;
assign bne_control = bne & (~zero_flag);
// PC_beq
assign PC_2beq = (beq_control==1'b1) ? PC_beq : pc2;
// PC_bne
assign PC_2bne = (bne_control==1'b1) ? PC_bne : PC_2beq;
// PC_j
assign PC_j = {pc2[15:13],jump_shift};
// PC_next
assign pc_next = (jump == 1'b1) ? PC_j : PC_2bne;

/// Data memory

data_memory

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

(
.clk(clk),
.mem_access_addr(ALU_out),
.mem_write_data(reg_read_data_2),
.mem_write_en(mem_write),
.mem_read(mem_read),
.mem_read_data(mem_read_data)
);

// write back
assign reg_write_data = (mem_to_reg == 1'b1)? mem_read_data: ALU_out;
// output to control unit
assign opcode = instr[15:12];
endmodule

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

5. Results Analysis

5.1 Study of Device Utilization

A study of the simulated work has been carried-out on the device utilization and summary is
presented for different processor components.

Register (Table: 4.1)

ALU (Table: 4.2)

ALU Control Unit (Table: 4.3)

Control Unit (Table: 4.4)

Instruction Memory (Table: 4.5)

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Data Memory (Table: 4.6)

Table 5.1: Comparative Table of Logic Utilization in Different Logic Blocks

Number of Bonded IOBs in Logic Blocks Utilization
Register 25%
ALU 21%
ALU CU 3%
Control Unit 6%
Instruction Memory 8%
Data Memory 7%

5.2 Results and Analysis

The VerilogHDL Coding has been performed for RISC Processor components such as register,
ALU, Control unit, Instruction memory, and data memory for their functional performance and
device utilization. It is found in the synthesis that the Register, ALU, Control Unit, Instruction
Memory, and data memory have number IOBs (Input/Output Block to implement I/O functions)
25%, 21%, 6%, 8%, and 7%. Here, the memory registers are occupying 25% area whereas control
unit has lowest 3%.

Comparative Table of Logic Utilization in Different Logic Blocks

30%
Number of Bonded IOBs in Logic Blocks

25%
25%
20% 21%

15%

10%
8%
5% 7%
6%
3%
0%
Register ALU ALU CU Control Unit Instruction Data Memory
Memory

Device Utilization

Figure 5.1: Simulation Waveforms with IOB Summary of Different Logic Blocks

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

6. Conclusions and Recommendations

In this work, the VerilogHDL Coding has been performed for RISC Processor components such as
register, ALU, Control unit, Instruction memory, and data memory for device utilization. It is found
in the synthesis that the Register, ALU, Control Unit, Instruction Memory, and data memory have
number IOBs (Input/Output Block to implement I/O functions) 25%, 21%, 6%, 8%, and 7%. Here,
the memory registers are occupying 25% area whereas control unit has lowest 3%. By improving
the VerilogHDL synthesizable constructs, the area efficiency may be achieved by lowering the
IOBs in future. The components may be tested for its functional and electrical verification at the
Field Programmable Gate Arrays (FPGA) levels and power analysis and optimization can be done
at the RTL levels.

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

7. Standards and Constraints

7.1 Standards
The following list includes the IEEE strandards and constraints used in the project

Code Modeling and Simulation

1995-2001 IEEE Std. 1364-1995, IEEE Std. 2001-1364 and IEEE Std. 2005-1364
Code Health & Safety
C2-2017 IEEE Standard Reference Designation for Electrical and Electronic Parts and
Equipments

7.2 Constraints
Time: Important constraint was the time and learning a new and state of the art Hardware
Description Language, the VerilogHDL. Through continuous meeting, the language learning,
project design and implementation criterion were discussed and decided. It took at least three to
four months to do literature survey, analysis, design the RISC processors compnents for general
purpose applications, also to analyze performance of RISC processor.
For the project: The Software implementation of RISC Processor components using HDL was
finished within 4 months. The language learning and coding part took much time and then it was
simulated and verified for it performance and contraints anlysis.
Teamwork: We have spitted the task among us and managed it to complete in time.
Ethics: We have maintained the ethics throughout the project.

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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

8. References
1. M. Zaid and P. Mustajab, "Design and application of RISC processor," 2017 International
Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT),
Aligarh, 2017, pp. 242-246, doi: 10.1109/MSPCT.2017.8364013.

2. Manoj Barfa, Deepak Sharma, “Implementation of 16 bit RISC Processor by FSM,” International
Journal Of Innovative Research In Technology, Vol. 4, Issue 12, May 2018, ISSN: 2349-6002

3. S. M. Bhagat and S. U. Bhandari, "Design and Analysis of 16-bit RISC Processor," 2018 Fourth
International Conference on Computing Communication Control and Automation (ICCUBEA),
Pune, India, 2018, pp. 1-4, doi: 10.1109/ICCUBEA.2018.8697859.

4. P Brundavani, Dupakuntla Vishnu Vardhan, P Mahesh, and Raja Suresh, “Design And Analysis
Of 16-Bit Risc Processor Using Low Power Pipeline,” in the Proc. National Conference on
Emerging trends in Information, management and Engineering sciences, “NC’ea-TIMES#1.0”-
2018, At: Rajampeta, June 2019

5. J. Bhasker, A VHDL Primer, Third Edition, Pub. Pearson, 1999.

6. M. Mano, Digital Design, Third Edition, Pub. erason Edition, 2000

7. D. J. Smith, HDL Chip Design, International Edition, Doone Publications, 2000

Appendix
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 DESIGN AND SIMULATION OF REDUCED INSTRUCTION SET COMPUTER (RISC) PROCESSOR IN VERILOGHDL

Checklist for Minimum Requirements

Dr. Neeraj Kumar Shukla Supervisor Name

Design and Simulation of Reduced Instruction Set Computer (RISC) Project Title
Processor in VerilogHDL
Abdualaziz Yahya S Alsalem (Student ID: 437801394) Student Names (s)
Mohammad Jaber (Student ID: 436800861)
IMPLEMENTED ITEM*
Indicate page(s) in the report for yes, cite reason(s) for
No Yes
no**

Real life problem
Not having a multidisciplinary nature One from
industry Advisory
From other committee
specializations
8 
Situation description
Performance analysis and hardware utilization of RISC 
Problem definition
processor components
8 
Open-ended
VerilogHDL or VHDL at different Software IDE platforms 
Alternative solutions
18 
Aesthetics
Literature 
Specifications and regulations
NA 
Statistics and reliability
48 
Teamwork

Professional ethics
NA 
Environmental impact statement
NA 
Cultural and social assessment
NA. VerilogHDL Language Simulation 
Financial analysis and marketing
Used VerilogHDL to design and check the performance 
analysis of RISC Processor Components and Hardware Final product
Utilization.
(*) See Appendix A for definitions
(**) Student(s): Indicate page(s) in the report for yes, cite reason(s) for no
Supervisor(s):Verify page(s) in the report for yes and reason(s) for no
Examiner(s):Verify reason(s) for yes or no

50