EE141-Fall 2010

Digital Integrated
Circuits

MOS Capacitance
Lecture 11
MOS Capacitance
and Delay

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Announcements MOS Capacitances

G
‰ No lab Fri., Mon.
ƒ Labs restart next week CGS CGD
= CGCS + CGSO = CGCD + CGDO
‰ Midterm #1 Thurs. Oct. 7th, 6:30-8:00pm S D
ƒ Exam is open notes, book, calculators, etc.
CSB CGB CDB
= Cdiff = Cdiff
= CGCB
B

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Class Material Gate Capacitance

‰ Last lecture
ƒ Using the MOS model: Inverter VTC
‰ Today’s lecture
ƒ MOS Capacitance
ƒ Using the MOS Model: Delay
‰ Reading (3.3.2, 5.4.2) ‰ Capacitance (per area) from gate across
the oxide is W·L·Cox, where Cox=εox/tox

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 Gate Capacitance Transistor in Linear Region
G

S W D
L

C OL CG C OL
xj
C JC
C jSB C jDB

‰ Distribution between terminals is complex LD

ƒ Capacitance is really distributed ƒ Channel is formed and acts as the other terminal
– CGCB drops to zero (shielded by channel)
– Useful models lump it to the terminals
ƒ Several operating regions: ƒ Model by splitting oxide cap equally between
source and drain
– Way off, off, transistor linear, transistor saturated
– Changing either voltage changes the channel charge
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Transistor In Cutoff Transistor in Saturation Region

G G

S W D S W D
L L

C OL C GB C OL C OL CG C OL
xj xj
C JC
C jSB C jDB C jSB C jDB

LD
ƒ When the transistor is off, no carriers in channel ƒ Changing source voltage doesn’t change VGC
to form the other side of the capacitor.
uniformly
– Substrate acts as the other capacitor terminal
– E.g. VGC at pinch off point still VTH
– Capacitance becomes series combination of gate
oxide and depletion capacitance
ƒ Bottom line: CGCS ≈ 2/3·W·L·Cox
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Transistor In Cutoff (cont’

(cont’d) Transistor in Saturation Region (cont’
(cont’d)
G G

S W D S W D
L L

C OL C GB C OL C OL CG C OL
xj xj
C JC
C jSB C jDB C jSB C jDB

LD
ƒ When |VGS| < |VT|, total CGCB much smaller than
ƒ Drain voltage no longer affects channel charge
W·L·Cox
– Set by source and VDS_sat
– Usually just approximate with CGCB = 0 in this region.

ƒ (If VGS is “very” negative (for NMOS), depletion ƒ If change in charge is 0, CGCD = 0
region shrinks and CGCB goes back to ~W·L·Cox)
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 Gate Capacitance Diffusion Capacitance
NA+
ƒ Bottom
Side wall
– Area cap
W Source
– Cbottom = Cj·LS·W ND
Bottom

ƒ Sidewalls xj Side wall

– Perimeter cap Channel
LS Substrate
– Csw = Cjsw·(2LS+W) NA
Cgate vs. VGS Cgate vs. operating region
(with VDS = 0) ƒ GateEdge
– Cge = Cjgate·W
– Usually automatically included in the SPICE model
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Gate Overlap Capacitance Junction Capacitance (2)

Polysilicon gate 1.0

ƒ Junction caps 0.9

are nonlinear

Capacitance [arbitrary units]

Gate oxide 0.8
tox – CJ is a
Source Drain
function of
0.7

W n+ L n+
n+ xd xd n+ junction bias 0.6

N+ junction area
Cross section 0.5 N+ junction perimeter

Gate-bulk P+ junction area

ƒ SPICE model
P+ junction perimeter
Ld
overlap 0.4

CO = Cox ⋅ xd
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Top view equations: Node voltage (V)

– Area CJ = area × CJ0 / (1+ |VDB|/φΒ )mj

– Perimeter CJ = perim × CJSW / (1 + |VDB|/φΒ)mjsw
Off/Lin/Sat Æ CGSO = CGDO = CO·W – Gate edge CJ = W × CJgate / (1 + |VDB|/φΒ)mjswg

ƒ How do we deal with nonlinear capacitance?

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Gate Fringe Capacitance Linearizing the Junction Capacitance

Fringing fields
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge over voltage swing of interest
n+ n+

Cross section

ƒ COV not just from metallurgic overlap – get fringing

fields too

ƒ Typical value: ~0.2fF·W(in µm)/edge

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 Capacitance Model Summary Model Calibration - Capacitance
‰ Gate-Channel Capacitance
ƒ CGC ≈ 0 (|VGS| < |VT|) ƒ Can calculate Cg, Cd based on tech. parameters
ƒ CGC = Cox·W·Leff (Linear) – But these models are simplified too
– 50% G to S, 50% G to D
ƒ CGC = (2/3)·Cox·W·Leff (Saturation) ƒ Another approach:
– 100% G to S – Tune (e.g., in spice) the linear capacitance until it
makes the simplified circuit match the real circuit
‰ Gate Overlap Capacitance – Matching could be for delay, power, etc.
ƒ CGSO = CGDO = CO·W (Always)

Cload
‰ Junction/Diffusion Capacitance Delay1 Match Delay2

ƒ Cdiff = Cj·LS·W + Cjsw·(2LS + W) + CjgW (Always)

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Capacitances in 0.25 µm CMOS

Process Model Calibration for Delay
A
Cload
Delay1 Match Delay2

ƒ For gate capacitance:

– Make inverter fanout 4
– Adjust Cload until Delay1 = Delay2
ƒ For diffusion capacitance
– Replace inverter “A” with a diffusion capacitance load

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Simplified Model Delay Calibration

ƒ Capacitance models important for analysis 1 4 16 64
and intuition
– But often need something simpler to work with
ƒ Simple switch model: Delay
– Lump together as effective linear capacitance to "Edge Shaper" Load ???
(ac) ground
– In most processes: CG = CD = 1.5 – 2fF·W(µm) ƒ Why did we need that last inverter stage?

Vin Vout Vin Vout

CL

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The Miller Effect
MOS Transistor as a Switch
ƒ As Vin increases, Vout drops
– Once get into the transition region, gain
Cgd1 ‰ Saw that real transistors aren’t exactly
∆V Vout
from Vin to Vout > 1 resistors
Vin ∆V
ƒ Look more like current sources in saturation
ƒ So, Cgd experiences voltage swing
larger than Vin M1

– Which means you need to provide more

charge ‰ Two questions:
– Makes Cgd look larger than it really is
ƒ Which region of IV curve determines delay?
ƒ Known as the “Miller Effect” in the ƒ How can that match up with the RC model?
analog world

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Transistor Driving a Capacitor

• With a step input:
VDD Æ VDD/2 ID VGS = VDD

CMOS
Switching Delay VDS
VVSAT VDD /2 VDD

• Transistor is in (velocity) saturation during entire transition

from VDD to VDD/2
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MOS Transistor as a Switch Switching Delay

• Discharging a capacitor • In saturation, transistor basically acts like a current source:
VOUT
i D = i D (v DS ) VOUT
VDD
C
dVDS IDSAT C
iD = C VDD/2
dt
• We modeled this with: t
R
tp

C tp = ln (2) RC VOUT = VDD - (IDSAT/C)t tp = C(VDD/2)/IDSAT

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 Switching Delay (with Output Conductance) The Book’s Method
• Including output conductance:
VOUT

IDSAT 1/(λIDSAT) C

VOUT = (VDD + λ −1 ) e
-t ( C λI DSAT )
- λ −1

C (VDD 2 )
• For “small” λ: tp ≈
(1 + λVDD ) I DSAT
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RC Model The Transistor as a Switch

• Transistor current not linear on VOUT – how is the RC 7
x 10
5

model going to work?

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• Look at waveforms: 2.5

5
2.3

• Voltage looks like a

(Ohm)

2.1 4

ramp for RC too 1.9

eq

3
NMOS
R
OUT

1.7
V

1.5 2

1.3 1
RC
1.1
0
0.9 0.5 1 1.5 2 2.5
V (V)
DD
0 0.2 0.4 0.6 0.8 1
t/τ
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Finding Req The Transistor as a Switch

• Match the delay of the RC model with the actual delay:
tp = t p , RC
C (VDD 2 ) (VDD 2 )
= ln ( 2 ) Req C Req =
(1 + λVDD ) I DSAT ln ( 2 )(1 + λVDD ) I DSAT

1 VDD
• Often just: Req ≈
2 ⋅ ln ( 2 ) I DSAT

• Note that the book uses a different method and gets

0.75·VDD/IDSAT instead of ~0.72·VDD/IDSAT.
• Why did we do it this way vs. the book’s method?

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