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Tanner Lab Record

The document describes a 10-bit controlled oscillator circuit including a schematic diagram, SPICE simulation report, and SPICE netlist. The report shows the circuit contains 24 MOSFETs, is simulated over 16 nodes, and the total simulation time is 1.95 seconds. The SPICE netlist defines the devices and simulation settings to analyze the circuit behavior over time.

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Merlin James
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0% found this document useful (0 votes)
559 views

Tanner Lab Record

The document describes a 10-bit controlled oscillator circuit including a schematic diagram, SPICE simulation report, and SPICE netlist. The report shows the circuit contains 24 MOSFETs, is simulated over 16 nodes, and the total simulation time is 1.95 seconds. The SPICE netlist defines the devices and simulation settings to analyze the circuit behavior over time.

Uploaded by

Merlin James
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

CMOS INVERTER

1.SCHEMATIC DIAGRAM:

2.REPORT:

Reading library entry "TT_NMOS_PARAMETERS" from "Generic_250nm.lib"


Reading library entry "TT_PMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "MOS_BIN_MODEL" from "Generic_250nm.lib"
Reading library entry "Typ" from "Generic_250nm.lib"
Reading library entry "RES_CAP" from "Generic_250nm.lib"
Loaded BSIM3v31 model library, Berkeley BSIM3 VERSION 3.1 with extensions

Opening simulation database


"C:\DOCUME~1\VLSILA~1\LOCALS~1\Temp\Cell0.tsim"
General options:
threads = 2
Device and node counts:
MOSFETs - 2 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 2 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 1 Boundary nodes - 3
Total nodes - 4

Parsing 0.03 seconds


Setup 0.36 seconds
DC operating point 0.03 seconds
Transient Analysis 0.25 seconds
Overhead 1.94 seconds
-----------------------------------------
Total 2.61 seconds

3. SPICE SIMULATION
********* Simulation Settings - General Section *********
.lib "C:\Documents and Settings\VLSI LAB\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" tt

*-------- Devices With SPICE.ORDER == 0.0 --------


***** Top Level *****
MPMOS_2_5v_1 Out In Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=3893 $y=5500 $w=414 $h=600
MPMOS_2_5v_2 Out In Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=3893 $y=4200 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------


VVoltageSource_2 Vdd Gnd DC 5 $ $x=2300 $y=5600 $w=400 $h=600
VVoltageSource_1 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=1400 $y=4500 $w=400
$h=600
.PRINT TRAN V(In) $ $x=2550 $y=4650 $w=1500 $h=300
.PRINT TRAN V(Out) $ $x=5350 $y=4750 $w=1500 $h=300

********* Simulation Settings - Analysis Section *********


.tran 15n 1.5u

.end

\
4.OUTPUT:
CMOS NAND GATE

1.SCHEMATIC DIAGRAM:

2.REPORT:

Reading library entry "TT_NMOS_PARAMETERS" from "Generic_250nm.lib"


Reading library entry "TT_PMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "MOS_BIN_MODEL" from "Generic_250nm.lib"
Reading library entry "Typ" from "Generic_250nm.lib"
Reading library entry "RES_CAP" from "Generic_250nm.lib"
Loaded BSIM3v31 model library, Berkeley BSIM3 VERSION 3.1 with extensions
Opening simulation database
"C:\DOCUME~1\VLSILA~1\LOCALS~1\Temp\Cell0.tsim"
General options:
threads = 2
Device and node counts:
MOSFETs - 4 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 3 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 2 Boundary nodes - 4
Total nodes - 6

Parsing 0.03 seconds


Setup 0.06 seconds
DC operating point 0.00 seconds
Transient Analysis 0.16 seconds
Overhead 1.22 seconds
-----------------------------------------
Total 1.47 seconds

3. SPICE SIMULATION

********* Simulation Settings - General Section *********


.lib "C:\Documents and Settings\VLSI LAB\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" tt

*-------- Devices With SPICE.ORDER == 0.0 --------


***** Top Level *****
MNMOS_2_5v_1 Out a N_2 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=6093 $y=8300 $w=414 $h=600
MNMOS_2_5v_2 N_2 b Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u $ $x=6093 $y=7100 $w=414 $h=600
MPMOS_2_5v_1 Out a Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=6093 $y=9200 $w=414 $h=600
MPMOS_2_5v_2 Out b Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=4193 $y=9100 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------


VVoltageSource_3 Vdd Gnd DC 5 $ $x=7800 $y=10000 $w=400 $h=600
VVoltageSource_1 a Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=4300 $y=8000 $w=400
$h=600
VVoltageSource_2 b Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=4400 $y=6800 $w=400
$h=600
.PRINT TRAN V(a) $ $x=5250 $y=8150 $w=1500 $h=300
.PRINT TRAN V(b) $ $x=5350 $y=6950 $w=1500 $h=300
.PRINT TRAN V(Out) $ $x=7550 $y=8650 $w=1500 $h=300
********* Simulation Settings - Analysis Section *********
.tran 100n 1u

.end

4.OUTPUT:
CMOS NOR GATE

1.SCHEMATIC DIAGRAM:

2.REPORT:

Reading library entry "TT_NMOS_PARAMETERS" from "Generic_250nm.lib"


Reading library entry "TT_PMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "MOS_BIN_MODEL" from "Generic_250nm.lib"
Reading library entry "Typ" from "Generic_250nm.lib"
Reading library entry "RES_CAP" from "Generic_250nm.lib"

General options:
threads = 2

Device and node counts:


MOSFETs - 4 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 3 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 2 Boundary nodes - 4
Total nodes - 6

Parsing 0.28 seconds


Setup 0.06 seconds
DC operating point 0.06 seconds
Transient Analysis 0.42 seconds
Overhead 1.95 seconds
-----------------------------------------
Total 2.78 seconds

3. SPICE SIMULAION

lib "C:\Documents and Settings\VLSI LAB\My Documents\Tanner EDA\Tanner Tools


v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" tt

*-------- Devices With SPICE.ORDER < 0.0 --------


.TEMP 0 10 25 40 55 70 $ $x=1400 $y=2250 $w=1200 $h=300

*-------- Devices With SPICE.ORDER == 0.0 --------


***** Top Level *****
MNMOS_2_5v_1 Out In2 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=2193 $y=1100 $w=414 $h=600
MNMOS_2_5v_2 Out In1 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=4793 $y=1100 $w=414 $h=600
MPMOS_2_5v_1 N_1 In1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=2893 $y=3600 $w=414 $h=600
MPMOS_2_5v_2 Out In2 N_1 Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=2893 $y=3000 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------


VVoltageSource_3 Vdd Gnd DC 5 $ $x=1800 $y=5800 $w=400 $h=600
VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=1700 $y=1800 $w=400
$h=600
.PRINT TRAN V(In1) $ $x=250 $y=3450 $w=1500 $h=300 $r=180
.PRINT TRAN V(In2) $ $x=1150 $y=2250 $w=1500 $h=300 $r=180
.PRINT TRAN V(Out) $ $x=4950 $y=2150 $w=1500 $h=300
********* Simulation Settings - Analysis Section *********
.tran 12n 2u

.end

4. OUTPUT
10BIT CONTROLLED OSCILLATOR

1.SCHEMATIC DIAGRAM

2.REPORT

Reading library entry "TT_NMOS_PARAMETERS" from "Generic_250nm.lib"


Reading library entry "TT_PMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "MOS_BIN_MODEL" from "Generic_250nm.lib"
Reading library entry "Typ" from "Generic_250nm.lib"
Reading library entry "RES_CAP" from "Generic_250nm.lib"
Opening simulation database
"C:\DOCUME~1\VLSILA~1\LOCALS~1\Temp\Cell0.tsim"

General options:
threads = 2

Device and node counts:


MOSFETs - 24 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 2 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 13 Boundary nodes - 3
Total nodes - 16
Parsing 0.33 seconds
Setup 0.08 seconds
DC operating point 0.11 seconds
Transient Analysis 0.31 seconds
Overhead 1.13 seconds
-----------------------------------------
Total 1.95 seconds

3. SPICE SIMULATION

.lib "C:\Documents and Settings\VLSI LAB\My Documents\Tanner EDA\Tanner Tools


v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" tt

********* Simulation Settings - General Section *********


.lib "C:\Documents and Settings\VLSI LAB\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" tt

*-------- Devices With SPICE.ORDER == 0.0 --------


***** Top Level *****
M_SPACE_ N_1 N_10 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=6293 $y=5700 $w=414 $h=600
MNMOS_2_5v_1 Out In N_12 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=1593 $y=4100 $w=414 $h=600
MPMOS_2_5v_1 N_1 Gnd Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=1793 $y=5700 $w=414 $h=600
MPMOS_2_5v_2 N_1 N_2 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=2293 $y=5700 $w=414 $h=600
MPMOS_2_5v_3 N_1 N_3 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=2793 $y=5700 $w=414 $h=600
MPMOS_2_5v_4 N_1 N_4 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=3293 $y=5700 $w=414 $h=600
MPMOS_2_5v_5 N_1 N_5 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=3793 $y=5700 $w=414 $h=600
MPMOS_2_5v_6 N_1 N_6 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=4293 $y=5700 $w=414 $h=600
MPMOS_2_5v_7 N_1 N_7 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=4793 $y=5700 $w=414 $h=600
MPMOS_2_5v_8 N_1 N_8 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=5293 $y=5700 $w=414 $h=600
MPMOS_2_5v_9 N_1 N_9 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=5793 $y=5700 $w=414 $h=600
MPMOS_2_5v_11 N_1 N_11 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=6793 $y=5700 $w=414 $h=600
MPMOS_2_5v_12 N_12 Vdd Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=1793 $y=3300 $w=414 $h=600
MPMOS_2_5v_13 N_12 N_2 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=2293 $y=3300 $w=414 $h=600
MPMOS_2_5v_14 N_12 N_3 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=2793 $y=3300 $w=414 $h=600
MPMOS_2_5v_15 N_12 N_4 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=3293 $y=3300 $w=414 $h=600
MPMOS_2_5v_16 N_12 N_5 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=3793 $y=3300 $w=414 $h=600
MPMOS_2_5v_17 N_12 N_6 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=4293 $y=3300 $w=414 $h=600
MPMOS_2_5v_18 N_12 N_7 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=4793 $y=3300 $w=414 $h=600
MPMOS_2_5v_19 N_12 N_8 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=5293 $y=3300 $w=414 $h=600
MPMOS_2_5v_20 N_12 N_9 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=5793 $y=3300 $w=414 $h=600
MPMOS_2_5v_21 N_12 N_10 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=6293 $y=3300 $w=414 $h=600
MPMOS_2_5v_22 N_12 N_11 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u
AD=975f PD=4.3u $ $x=6793 $y=3300 $w=414 $h=600
MPMOS_2_5v_23 Out In N_1 Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u
AD=1.95p PD=7.3u $ $x=1593 $y=5000 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------


VVoltageSource_1 Vdd Gnd DC 5 $ $x=800 $y=6100 $w=400 $h=600
VVoltageSource_2 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=600 $y=3900 $w=400
$h=600
.PRINT TRAN V(In) $ $x=1250 $y=2550 $w=1500 $h=300
.PRINT TRAN V(Out) $ $x=2750 $y=2650 $w=1500 $h=300

********* Simulation Settings - Analysis Section *********


.tran 10n 1u start=0

.end

\
4. OUTPUT

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