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Beng Hons Electrical & Electronic Engineering

The document describes a student project to program an Intel DE0-Nano board to implement a pedestrian crossing control system using sequential logic. It includes: 1) Block diagrams showing the inputs (clock, reset, start button) and outputs (LEDs) of the system. 2) Code for the design including debouncing, a state machine with 3 states (wait, train arriving, train passed), and output logic. 3) A testbench simulating the design through different states by toggling inputs and verifying outputs.

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mohammed
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114 views

Beng Hons Electrical & Electronic Engineering

The document describes a student project to program an Intel DE0-Nano board to implement a pedestrian crossing control system using sequential logic. It includes: 1) Block diagrams showing the inputs (clock, reset, start button) and outputs (LEDs) of the system. 2) Code for the design including debouncing, a state machine with 3 states (wait, train arriving, train passed), and output logic. 3) A testbench simulating the design through different states by toggling inputs and verifying outputs.

Uploaded by

mohammed
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 12

Name: MOAHMMED ALHMIDAWI.

Student ID: 17828902.


Course Title: BENG HONS ELECTRICAL & ELECTRONIC
ENGINEERING.
Module Title: Digital Systems Design EO528.
marker of assessment: Simon Busbridge, Gavin Denman.
Assessment title: Main project
Date of submission: Wednesday 18th August 2021 before 15:00
Introduction:

This report will demonstrate the steps that were required to program the DE0-Nano board
from Intel, the required design was to implement a crossing control using sequential logic, the
crossing control consist of a switch that represent the train signal with a rest button, the whole
system consist of the pedestrian cross (Red and Green LEDs), a flashing Red and a green
LED for the train with a Green and Red LEDs for the traffic.
Testbench and sublimation for the code and block diagrams are included in the report and
discussed.
The code was approached using modular approach apart from the Length statement.

The assignment was done individually, there is no task splitting, all done by the one student.

Block diagram and structure:

Figure 1: Block diagram represents the circuit’s diagram.

Figure one shows the inputs that has being used in the code which are, the clk (clock to run
the code cycle), rstn (active low push button that rests the cycle) and a start_sequance (push
button that signal the train and starts the sequence).
Figure 2: finite-state machine

The sequential circuit above shows the mechanism whose output (LEDs) behaviour
depending on the of the systems and the dataflow.

The code with the comments and headers (Appendix 1 , has the code for copy and paste
purpose).

1) Library declaration,

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

2) The entity that shows the inputs and outputs,

entity crossing_control5 is

generic(

debounce_delay: integer:= 50000; -- 1ms

flashing_delay: integer:= 25000000 -- flashing period is 0.5 second

);

port(

clk: in std_logic; -- 50 MHz clock for the system

rstn: in std_logic; -- active low reset

start_sequence: in std_logic; -- Button to start the sequency

train_line_clear_n: in std_logic; -- Tells that train is gone and line is cleared -- active low
-- 0 bit -> flashing red light

-- 1 bit -> Amber

led_traffic: out std_logic_vector(1 downto 0); -- Amber and flashing red light for traffic

-- 0 bit -> Red

-- 1 bit -> Green

led_train: out std_logic_vector(1 downto 0); -- Red and Green led for the trains

-- 0 bit -> Red

-- 1 bit -> Green

led_pedestrian: out std_logic_vector(1 downto 0) -- Red and green leds for the pedestrians

);

end crossing_control5;

3) The architecture,

architecture arch_crossing_control of crossing_control5 is


-- Intermediate Signals
signal start_seq_reg1: std_logic;
signal start_seq_reg2: std_logic;
signal start_seq_flag: std_logic;
signal debounce_count: unsigned(15 downto 0);
signal flashing_red: std_logic;
signal flashing_count: unsigned(31 downto 0);
signal train_line_clear_n_reg: std_logic;
-- State Machine signals
type state_type is(
S0, -- wait for start sequence
S1, -- wait for train to arrive by monitoring train_line_clear_n signal
S2 -- wait for train to clear the lane
);

signal state: state_type := S0;

begin
------ Debouncing for the start sequence button
process(clk,rstn,start_sequence,train_line_clear_n) begin
if(rstn = '0') then
debounce_count <= (others => '0');
start_seq_reg1 <= '0';
start_seq_reg2 <= '0';
train_line_clear_n_reg <= '0';
elsif rising_edge(clk) then
if(debounce_count = to_unsigned(debounce_delay, debounce_count'length)) then -- push the
button for atleast 1ms
start_seq_reg1 <= start_sequence;
train_line_clear_n_reg <= train_line_clear_n;
debounce_count <= (others => '0');
else
start_seq_reg1 <= start_seq_reg1;
train_line_clear_n_reg <= train_line_clear_n_reg;
debounce_count <= debounce_count + 1;
end if;
start_seq_reg2 <= start_seq_reg1;
end if;
end process;
-- one clock cycle flag for the start sequency button
start_seq_flag <= start_seq_reg1 AND (NOT start_seq_reg2);

-- Flashing red light


-- with 0.5 second period
process(clk, rstn) begin
if(rstn = '0') then
flashing_count <= (others => '0');
flashing_red <= '0';
elsif rising_edge(clk) then
if(flashing_count = to_unsigned(flashing_delay, flashing_count'length)) then -- flashing period
is 0.5 second
flashing_count <= (others => '0');
flashing_red <= NOT flashing_red;
else
flashing_count <= flashing_count + 1;
flashing_red <= flashing_red;
end if;
end if;
end process;

4) The process for the crossing control,

---------- Crossing control


process(clk,rstn,start_seq_flag,train_line_clear_n_reg,state) begin
if(rstn = '0') then
state <= S0;
elsif rising_edge(clk) then
case(state) is
when S0 =>
if(start_seq_flag = '1') then
state <= S1;
else
state <= S0;
end if;
when S1 =>
if(train_line_clear_n_reg = '1') then
state <= S2;
else
state <= S1;
end if;
when S2 =>
if(train_line_clear_n_reg = '0') then
state <= S0;
else
state <= S2;
end if;
when others => state <= S0;
end case;
end if;
end process;
-- output
process(state, flashing_red) begin
case(state) is
when S0 =>
led_traffic <= '1' & '0';
led_train <= "01";
led_pedestrian <= "10";
when S1 =>
led_traffic <= '0' & flashing_red;
led_train <= "10";
led_pedestrian <= "01";
when S2 =>
led_traffic <= '0' & flashing_red;
led_train <= "10";
led_pedestrian <= "01";
when others =>
led_traffic <= "00";
led_train <= "00";
led_pedestrian <= "00";
end case;
end process;

end arch_crossing_control;
The Testbench code:

(Appendix 2 , has the code for copy and paste purpose).

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity testbench is
end testbench;

architecture arch_testbench of testbench is


-- Interconnecting signals
signal clk: std_logic:= '0'; -- 50 MHz clock for the system
signal rstn: std_logic; -- active low reset
signal start_sequence: std_logic; -- Button to start the sequency
signal train_line_clear_n: std_logic; -- Tells that train is gone and line is cleared -- active low
-- 0 bit -> flashing red light
-- 1 bit -> Amber
signal led_traffic: std_logic_vector(1 downto 0); -- Amber and flashing red light for traffic
-- 0 bit -> Red
-- 1 bit -> Green
signal led_train: std_logic_vector(1 downto 0); -- Red and Green led for the trains
-- 0 bit -> Red
-- 1 bit -> Green
signal led_pedestrian: std_logic_vector(1 downto 0); -- Red and green leds for the pedestrians

-- Clock period -- 50 MHz clock


constant clk_period: time := 20 ns;
signal sim_finish: std_logic:= '0';

begin
-- Design under test
dut: entity work.crossing_control
-- for simulation run them fast
generic map(
debounce_delay => 0,
flashing_delay => 1
)
port map(
clk => clk,
rstn => rstn,
start_sequence => start_sequence,
train_line_clear_n => train_line_clear_n,
led_traffic => led_traffic,
led_train => led_train,
led_pedestrian => led_pedestrian
);
-- CLock Generator
clk <= not clk after (clk_period/2) when sim_finish /= '1' else '0';

-- Testing
process begin
-- Initialize the values
rstn <= '1';
start_sequence <= '0';
train_line_clear_n <= '0';
-- Apply reset
wait for 100 ns;
rstn <= '0';
wait for 100 ns;
rstn <= '1';
wait for 100 ns;

-- Apply simulation
start_sequence <= '1';
wait for 200 ns;
-- Train is here
train_line_clear_n <= '1';
wait for 200 ns;
-- Train passed
train_line_clear_n <= '0';
start_sequence <= '0';

wait for 200 ns;


-- Finish the simulation
sim_finish <= '1';
wait;
end process;
end arch_testbench;

the Testbench simulation:


Figure 3 : Testbench simulation:

The Testbench clearly shows the outputs of the code, rest is active hight meanwhile the
start_sequance and clearnow are active low which makes the outputs (LEDs)

Pin allocation for when it was tested on the board:

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